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492 lines
13 KiB
492 lines
13 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* MCE grading rules. |
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* Copyright 2008, 2009 Intel Corporation. |
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* |
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* Author: Andi Kleen |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/seq_file.h> |
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#include <linux/init.h> |
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#include <linux/debugfs.h> |
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#include <linux/uaccess.h> |
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|
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#include <asm/mce.h> |
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#include <asm/intel-family.h> |
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#include <asm/traps.h> |
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#include <asm/insn.h> |
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#include <asm/insn-eval.h> |
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|
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#include "internal.h" |
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|
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/* |
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* Grade an mce by severity. In general the most severe ones are processed |
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* first. Since there are quite a lot of combinations test the bits in a |
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* table-driven way. The rules are simply processed in order, first |
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* match wins. |
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* |
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* Note this is only used for machine check exceptions, the corrected |
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* errors use much simpler rules. The exceptions still check for the corrected |
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* errors, but only to leave them alone for the CMCI handler (except for |
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* panic situations) |
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*/ |
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|
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enum context { IN_KERNEL = 1, IN_USER = 2, IN_KERNEL_RECOV = 3 }; |
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enum ser { SER_REQUIRED = 1, NO_SER = 2 }; |
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enum exception { EXCP_CONTEXT = 1, NO_EXCP = 2 }; |
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|
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static struct severity { |
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u64 mask; |
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u64 result; |
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unsigned char sev; |
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unsigned char mcgmask; |
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unsigned char mcgres; |
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unsigned char ser; |
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unsigned char context; |
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unsigned char excp; |
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unsigned char covered; |
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unsigned char cpu_model; |
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unsigned char cpu_minstepping; |
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unsigned char bank_lo, bank_hi; |
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char *msg; |
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} severities[] = { |
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#define MCESEV(s, m, c...) { .sev = MCE_ ## s ## _SEVERITY, .msg = m, ## c } |
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#define BANK_RANGE(l, h) .bank_lo = l, .bank_hi = h |
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#define MODEL_STEPPING(m, s) .cpu_model = m, .cpu_minstepping = s |
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#define KERNEL .context = IN_KERNEL |
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#define USER .context = IN_USER |
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#define KERNEL_RECOV .context = IN_KERNEL_RECOV |
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#define SER .ser = SER_REQUIRED |
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#define NOSER .ser = NO_SER |
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#define EXCP .excp = EXCP_CONTEXT |
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#define NOEXCP .excp = NO_EXCP |
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#define BITCLR(x) .mask = x, .result = 0 |
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#define BITSET(x) .mask = x, .result = x |
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#define MCGMASK(x, y) .mcgmask = x, .mcgres = y |
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#define MASK(x, y) .mask = x, .result = y |
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#define MCI_UC_S (MCI_STATUS_UC|MCI_STATUS_S) |
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#define MCI_UC_AR (MCI_STATUS_UC|MCI_STATUS_AR) |
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#define MCI_UC_SAR (MCI_STATUS_UC|MCI_STATUS_S|MCI_STATUS_AR) |
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#define MCI_ADDR (MCI_STATUS_ADDRV|MCI_STATUS_MISCV) |
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MCESEV( |
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NO, "Invalid", |
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BITCLR(MCI_STATUS_VAL) |
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), |
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MCESEV( |
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NO, "Not enabled", |
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EXCP, BITCLR(MCI_STATUS_EN) |
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), |
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MCESEV( |
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PANIC, "Processor context corrupt", |
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BITSET(MCI_STATUS_PCC) |
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), |
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/* When MCIP is not set something is very confused */ |
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MCESEV( |
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PANIC, "MCIP not set in MCA handler", |
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EXCP, MCGMASK(MCG_STATUS_MCIP, 0) |
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), |
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/* Neither return not error IP -- no chance to recover -> PANIC */ |
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MCESEV( |
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PANIC, "Neither restart nor error IP", |
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EXCP, MCGMASK(MCG_STATUS_RIPV|MCG_STATUS_EIPV, 0) |
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), |
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MCESEV( |
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PANIC, "In kernel and no restart IP", |
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EXCP, KERNEL, MCGMASK(MCG_STATUS_RIPV, 0) |
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), |
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MCESEV( |
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PANIC, "In kernel and no restart IP", |
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EXCP, KERNEL_RECOV, MCGMASK(MCG_STATUS_RIPV, 0) |
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), |
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MCESEV( |
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KEEP, "Corrected error", |
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NOSER, BITCLR(MCI_STATUS_UC) |
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), |
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/* |
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* known AO MCACODs reported via MCE or CMC: |
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* |
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* SRAO could be signaled either via a machine check exception or |
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* CMCI with the corresponding bit S 1 or 0. So we don't need to |
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* check bit S for SRAO. |
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*/ |
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MCESEV( |
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AO, "Action optional: memory scrubbing error", |
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SER, MASK(MCI_UC_AR|MCACOD_SCRUBMSK, MCI_STATUS_UC|MCACOD_SCRUB) |
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), |
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MCESEV( |
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AO, "Action optional: last level cache writeback error", |
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SER, MASK(MCI_UC_AR|MCACOD, MCI_STATUS_UC|MCACOD_L3WB) |
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), |
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/* |
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* Quirk for Skylake/Cascade Lake. Patrol scrubber may be configured |
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* to report uncorrected errors using CMCI with a special signature. |
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* UC=0, MSCOD=0x0010, MCACOD=binary(000X 0000 1100 XXXX) reported |
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* in one of the memory controller banks. |
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* Set severity to "AO" for same action as normal patrol scrub error. |
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*/ |
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MCESEV( |
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AO, "Uncorrected Patrol Scrub Error", |
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SER, MASK(MCI_STATUS_UC|MCI_ADDR|0xffffeff0, MCI_ADDR|0x001000c0), |
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MODEL_STEPPING(INTEL_FAM6_SKYLAKE_X, 4), BANK_RANGE(13, 18) |
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), |
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/* ignore OVER for UCNA */ |
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MCESEV( |
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UCNA, "Uncorrected no action required", |
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SER, MASK(MCI_UC_SAR, MCI_STATUS_UC) |
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), |
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MCESEV( |
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PANIC, "Illegal combination (UCNA with AR=1)", |
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SER, |
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MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_STATUS_UC|MCI_STATUS_AR) |
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), |
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MCESEV( |
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KEEP, "Non signalled machine check", |
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SER, BITCLR(MCI_STATUS_S) |
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), |
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MCESEV( |
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PANIC, "Action required with lost events", |
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SER, BITSET(MCI_STATUS_OVER|MCI_UC_SAR) |
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), |
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|
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/* known AR MCACODs: */ |
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#ifdef CONFIG_MEMORY_FAILURE |
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MCESEV( |
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KEEP, "Action required but unaffected thread is continuable", |
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SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR, MCI_UC_SAR|MCI_ADDR), |
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MCGMASK(MCG_STATUS_RIPV|MCG_STATUS_EIPV, MCG_STATUS_RIPV) |
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), |
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MCESEV( |
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AR, "Action required: data load in error recoverable area of kernel", |
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SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_DATA), |
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KERNEL_RECOV |
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), |
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MCESEV( |
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AR, "Action required: data load error in a user process", |
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SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_DATA), |
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USER |
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), |
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MCESEV( |
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AR, "Action required: instruction fetch error in a user process", |
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SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_INSTR), |
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USER |
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), |
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MCESEV( |
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PANIC, "Data load in unrecoverable area of kernel", |
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SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_DATA), |
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KERNEL |
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), |
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MCESEV( |
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PANIC, "Instruction fetch error in kernel", |
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SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_INSTR), |
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KERNEL |
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), |
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#endif |
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MCESEV( |
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PANIC, "Action required: unknown MCACOD", |
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SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_UC_SAR) |
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), |
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MCESEV( |
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SOME, "Action optional: unknown MCACOD", |
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SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_UC_S) |
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), |
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MCESEV( |
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SOME, "Action optional with lost events", |
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SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR, MCI_STATUS_OVER|MCI_UC_S) |
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), |
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MCESEV( |
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PANIC, "Overflowed uncorrected", |
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BITSET(MCI_STATUS_OVER|MCI_STATUS_UC) |
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), |
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MCESEV( |
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UC, "Uncorrected", |
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BITSET(MCI_STATUS_UC) |
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), |
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MCESEV( |
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SOME, "No match", |
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BITSET(0) |
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) /* always matches. keep at end */ |
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}; |
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#define mc_recoverable(mcg) (((mcg) & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) == \ |
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(MCG_STATUS_RIPV|MCG_STATUS_EIPV)) |
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static bool is_copy_from_user(struct pt_regs *regs) |
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{ |
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u8 insn_buf[MAX_INSN_SIZE]; |
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struct insn insn; |
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unsigned long addr; |
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if (copy_from_kernel_nofault(insn_buf, (void *)regs->ip, MAX_INSN_SIZE)) |
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return false; |
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kernel_insn_init(&insn, insn_buf, MAX_INSN_SIZE); |
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insn_get_opcode(&insn); |
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if (!insn.opcode.got) |
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return false; |
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switch (insn.opcode.value) { |
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/* MOV mem,reg */ |
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case 0x8A: case 0x8B: |
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/* MOVZ mem,reg */ |
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case 0xB60F: case 0xB70F: |
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insn_get_modrm(&insn); |
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insn_get_sib(&insn); |
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if (!insn.modrm.got || !insn.sib.got) |
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return false; |
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addr = (unsigned long)insn_get_addr_ref(&insn, regs); |
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break; |
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/* REP MOVS */ |
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case 0xA4: case 0xA5: |
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addr = regs->si; |
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break; |
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default: |
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return false; |
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} |
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if (fault_in_kernel_space(addr)) |
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return false; |
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current->mce_vaddr = (void __user *)addr; |
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return true; |
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} |
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/* |
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* If mcgstatus indicated that ip/cs on the stack were |
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* no good, then "m->cs" will be zero and we will have |
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* to assume the worst case (IN_KERNEL) as we actually |
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* have no idea what we were executing when the machine |
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* check hit. |
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* If we do have a good "m->cs" (or a faked one in the |
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* case we were executing in VM86 mode) we can use it to |
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* distinguish an exception taken in user from from one |
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* taken in the kernel. |
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*/ |
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static int error_context(struct mce *m, struct pt_regs *regs) |
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{ |
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enum handler_type t; |
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if ((m->cs & 3) == 3) |
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return IN_USER; |
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if (!mc_recoverable(m->mcgstatus)) |
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return IN_KERNEL; |
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t = ex_get_fault_handler_type(m->ip); |
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if (t == EX_HANDLER_FAULT) { |
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m->kflags |= MCE_IN_KERNEL_RECOV; |
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return IN_KERNEL_RECOV; |
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} |
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if (t == EX_HANDLER_UACCESS && regs && is_copy_from_user(regs)) { |
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m->kflags |= MCE_IN_KERNEL_RECOV; |
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m->kflags |= MCE_IN_KERNEL_COPYIN; |
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return IN_KERNEL_RECOV; |
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} |
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return IN_KERNEL; |
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} |
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static int mce_severity_amd_smca(struct mce *m, enum context err_ctx) |
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{ |
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u32 addr = MSR_AMD64_SMCA_MCx_CONFIG(m->bank); |
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u32 low, high; |
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/* |
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* We need to look at the following bits: |
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* - "succor" bit (data poisoning support), and |
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* - TCC bit (Task Context Corrupt) |
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* in MCi_STATUS to determine error severity. |
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*/ |
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if (!mce_flags.succor) |
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return MCE_PANIC_SEVERITY; |
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if (rdmsr_safe(addr, &low, &high)) |
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return MCE_PANIC_SEVERITY; |
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/* TCC (Task context corrupt). If set and if IN_KERNEL, panic. */ |
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if ((low & MCI_CONFIG_MCAX) && |
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(m->status & MCI_STATUS_TCC) && |
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(err_ctx == IN_KERNEL)) |
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return MCE_PANIC_SEVERITY; |
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/* ...otherwise invoke hwpoison handler. */ |
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return MCE_AR_SEVERITY; |
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} |
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/* |
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* See AMD Error Scope Hierarchy table in a newer BKDG. For example |
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* 49125_15h_Models_30h-3Fh_BKDG.pdf, section "RAS Features" |
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*/ |
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static int mce_severity_amd(struct mce *m, struct pt_regs *regs, int tolerant, |
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char **msg, bool is_excp) |
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{ |
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enum context ctx = error_context(m, regs); |
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/* Processor Context Corrupt, no need to fumble too much, die! */ |
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if (m->status & MCI_STATUS_PCC) |
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return MCE_PANIC_SEVERITY; |
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if (m->status & MCI_STATUS_UC) { |
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if (ctx == IN_KERNEL) |
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return MCE_PANIC_SEVERITY; |
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/* |
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* On older systems where overflow_recov flag is not present, we |
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* should simply panic if an error overflow occurs. If |
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* overflow_recov flag is present and set, then software can try |
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* to at least kill process to prolong system operation. |
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*/ |
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if (mce_flags.overflow_recov) { |
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if (mce_flags.smca) |
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return mce_severity_amd_smca(m, ctx); |
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/* kill current process */ |
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return MCE_AR_SEVERITY; |
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} else { |
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/* at least one error was not logged */ |
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if (m->status & MCI_STATUS_OVER) |
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return MCE_PANIC_SEVERITY; |
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} |
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/* |
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* For any other case, return MCE_UC_SEVERITY so that we log the |
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* error and exit #MC handler. |
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*/ |
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return MCE_UC_SEVERITY; |
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} |
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/* |
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* deferred error: poll handler catches these and adds to mce_ring so |
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* memory-failure can take recovery actions. |
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*/ |
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if (m->status & MCI_STATUS_DEFERRED) |
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return MCE_DEFERRED_SEVERITY; |
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/* |
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* corrected error: poll handler catches these and passes responsibility |
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* of decoding the error to EDAC |
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*/ |
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return MCE_KEEP_SEVERITY; |
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} |
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static int mce_severity_intel(struct mce *m, struct pt_regs *regs, |
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int tolerant, char **msg, bool is_excp) |
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{ |
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enum exception excp = (is_excp ? EXCP_CONTEXT : NO_EXCP); |
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enum context ctx = error_context(m, regs); |
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struct severity *s; |
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for (s = severities;; s++) { |
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if ((m->status & s->mask) != s->result) |
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continue; |
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if ((m->mcgstatus & s->mcgmask) != s->mcgres) |
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continue; |
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if (s->ser == SER_REQUIRED && !mca_cfg.ser) |
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continue; |
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if (s->ser == NO_SER && mca_cfg.ser) |
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continue; |
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if (s->context && ctx != s->context) |
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continue; |
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if (s->excp && excp != s->excp) |
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continue; |
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if (s->cpu_model && boot_cpu_data.x86_model != s->cpu_model) |
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continue; |
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if (s->cpu_minstepping && boot_cpu_data.x86_stepping < s->cpu_minstepping) |
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continue; |
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if (s->bank_lo && (m->bank < s->bank_lo || m->bank > s->bank_hi)) |
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continue; |
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if (msg) |
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*msg = s->msg; |
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s->covered = 1; |
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if (s->sev >= MCE_UC_SEVERITY && ctx == IN_KERNEL) { |
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if (tolerant < 1) |
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return MCE_PANIC_SEVERITY; |
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} |
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return s->sev; |
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} |
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} |
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/* Default to mce_severity_intel */ |
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int (*mce_severity)(struct mce *m, struct pt_regs *regs, int tolerant, char **msg, bool is_excp) = |
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mce_severity_intel; |
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void __init mcheck_vendor_init_severity(void) |
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{ |
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if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD || |
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boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) |
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mce_severity = mce_severity_amd; |
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} |
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|
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#ifdef CONFIG_DEBUG_FS |
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static void *s_start(struct seq_file *f, loff_t *pos) |
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{ |
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if (*pos >= ARRAY_SIZE(severities)) |
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return NULL; |
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return &severities[*pos]; |
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} |
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static void *s_next(struct seq_file *f, void *data, loff_t *pos) |
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{ |
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if (++(*pos) >= ARRAY_SIZE(severities)) |
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return NULL; |
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return &severities[*pos]; |
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} |
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static void s_stop(struct seq_file *f, void *data) |
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{ |
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} |
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static int s_show(struct seq_file *f, void *data) |
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{ |
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struct severity *ser = data; |
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seq_printf(f, "%d\t%s\n", ser->covered, ser->msg); |
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return 0; |
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} |
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static const struct seq_operations severities_seq_ops = { |
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.start = s_start, |
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.next = s_next, |
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.stop = s_stop, |
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.show = s_show, |
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}; |
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static int severities_coverage_open(struct inode *inode, struct file *file) |
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{ |
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return seq_open(file, &severities_seq_ops); |
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} |
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static ssize_t severities_coverage_write(struct file *file, |
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const char __user *ubuf, |
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size_t count, loff_t *ppos) |
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{ |
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int i; |
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for (i = 0; i < ARRAY_SIZE(severities); i++) |
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severities[i].covered = 0; |
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return count; |
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} |
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|
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static const struct file_operations severities_coverage_fops = { |
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.open = severities_coverage_open, |
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.release = seq_release, |
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.read = seq_read, |
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.write = severities_coverage_write, |
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.llseek = seq_lseek, |
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}; |
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|
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static int __init severities_debugfs_init(void) |
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{ |
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struct dentry *dmce; |
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dmce = mce_get_debugfs_dir(); |
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debugfs_create_file("severities-coverage", 0444, dmce, NULL, |
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&severities_coverage_fops); |
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return 0; |
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} |
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late_initcall(severities_debugfs_init); |
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#endif /* CONFIG_DEBUG_FS */
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