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199 lines
5.3 KiB
199 lines
5.3 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#ifndef __X86_MCE_INTERNAL_H__ |
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#define __X86_MCE_INTERNAL_H__ |
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#undef pr_fmt |
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#define pr_fmt(fmt) "mce: " fmt |
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#include <linux/device.h> |
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#include <asm/mce.h> |
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/* Pointer to the installed machine check handler for this CPU setup. */ |
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extern void (*machine_check_vector)(struct pt_regs *); |
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enum severity_level { |
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MCE_NO_SEVERITY, |
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MCE_DEFERRED_SEVERITY, |
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MCE_UCNA_SEVERITY = MCE_DEFERRED_SEVERITY, |
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MCE_KEEP_SEVERITY, |
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MCE_SOME_SEVERITY, |
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MCE_AO_SEVERITY, |
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MCE_UC_SEVERITY, |
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MCE_AR_SEVERITY, |
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MCE_PANIC_SEVERITY, |
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}; |
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extern struct blocking_notifier_head x86_mce_decoder_chain; |
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#define INITIAL_CHECK_INTERVAL 5 * 60 /* 5 minutes */ |
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struct mce_evt_llist { |
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struct llist_node llnode; |
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struct mce mce; |
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}; |
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void mce_gen_pool_process(struct work_struct *__unused); |
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bool mce_gen_pool_empty(void); |
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int mce_gen_pool_add(struct mce *mce); |
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int mce_gen_pool_init(void); |
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struct llist_node *mce_gen_pool_prepare_records(void); |
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extern int (*mce_severity)(struct mce *a, struct pt_regs *regs, |
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int tolerant, char **msg, bool is_excp); |
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struct dentry *mce_get_debugfs_dir(void); |
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extern mce_banks_t mce_banks_ce_disabled; |
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#ifdef CONFIG_X86_MCE_INTEL |
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unsigned long cmci_intel_adjust_timer(unsigned long interval); |
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bool mce_intel_cmci_poll(void); |
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void mce_intel_hcpu_update(unsigned long cpu); |
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void cmci_disable_bank(int bank); |
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void intel_init_cmci(void); |
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void intel_init_lmce(void); |
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void intel_clear_lmce(void); |
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bool intel_filter_mce(struct mce *m); |
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#else |
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# define cmci_intel_adjust_timer mce_adjust_timer_default |
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static inline bool mce_intel_cmci_poll(void) { return false; } |
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static inline void mce_intel_hcpu_update(unsigned long cpu) { } |
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static inline void cmci_disable_bank(int bank) { } |
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static inline void intel_init_cmci(void) { } |
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static inline void intel_init_lmce(void) { } |
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static inline void intel_clear_lmce(void) { } |
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static inline bool intel_filter_mce(struct mce *m) { return false; }; |
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#endif |
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void mce_timer_kick(unsigned long interval); |
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#ifdef CONFIG_ACPI_APEI |
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int apei_write_mce(struct mce *m); |
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ssize_t apei_read_mce(struct mce *m, u64 *record_id); |
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int apei_check_mce(void); |
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int apei_clear_mce(u64 record_id); |
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#else |
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static inline int apei_write_mce(struct mce *m) |
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{ |
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return -EINVAL; |
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} |
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static inline ssize_t apei_read_mce(struct mce *m, u64 *record_id) |
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{ |
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return 0; |
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} |
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static inline int apei_check_mce(void) |
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{ |
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return 0; |
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} |
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static inline int apei_clear_mce(u64 record_id) |
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{ |
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return -EINVAL; |
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} |
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#endif |
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/* |
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* We consider records to be equivalent if bank+status+addr+misc all match. |
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* This is only used when the system is going down because of a fatal error |
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* to avoid cluttering the console log with essentially repeated information. |
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* In normal processing all errors seen are logged. |
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*/ |
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static inline bool mce_cmp(struct mce *m1, struct mce *m2) |
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{ |
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return m1->bank != m2->bank || |
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m1->status != m2->status || |
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m1->addr != m2->addr || |
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m1->misc != m2->misc; |
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} |
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extern struct device_attribute dev_attr_trigger; |
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#ifdef CONFIG_X86_MCELOG_LEGACY |
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void mce_work_trigger(void); |
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void mce_register_injector_chain(struct notifier_block *nb); |
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void mce_unregister_injector_chain(struct notifier_block *nb); |
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#else |
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static inline void mce_work_trigger(void) { } |
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static inline void mce_register_injector_chain(struct notifier_block *nb) { } |
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static inline void mce_unregister_injector_chain(struct notifier_block *nb) { } |
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#endif |
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struct mca_config { |
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bool dont_log_ce; |
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bool cmci_disabled; |
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bool ignore_ce; |
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bool print_all; |
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__u64 lmce_disabled : 1, |
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disabled : 1, |
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ser : 1, |
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recovery : 1, |
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bios_cmci_threshold : 1, |
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__reserved : 59; |
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s8 bootlog; |
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int tolerant; |
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int monarch_timeout; |
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int panic_timeout; |
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u32 rip_msr; |
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}; |
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extern struct mca_config mca_cfg; |
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DECLARE_PER_CPU_READ_MOSTLY(unsigned int, mce_num_banks); |
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struct mce_vendor_flags { |
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/* |
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* Indicates that overflow conditions are not fatal, when set. |
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*/ |
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__u64 overflow_recov : 1, |
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/* |
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* (AMD) SUCCOR stands for S/W UnCorrectable error COntainment and |
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* Recovery. It indicates support for data poisoning in HW and deferred |
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* error interrupts. |
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*/ |
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succor : 1, |
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/* |
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* (AMD) SMCA: This bit indicates support for Scalable MCA which expands |
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* the register space for each MCA bank and also increases number of |
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* banks. Also, to accommodate the new banks and registers, the MCA |
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* register space is moved to a new MSR range. |
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*/ |
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smca : 1, |
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/* AMD-style error thresholding banks present. */ |
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amd_threshold : 1, |
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__reserved_0 : 60; |
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}; |
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extern struct mce_vendor_flags mce_flags; |
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struct mca_msr_regs { |
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u32 (*ctl) (int bank); |
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u32 (*status) (int bank); |
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u32 (*addr) (int bank); |
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u32 (*misc) (int bank); |
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}; |
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extern struct mca_msr_regs msr_ops; |
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/* Decide whether to add MCE record to MCE event pool or filter it out. */ |
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extern bool filter_mce(struct mce *m); |
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#ifdef CONFIG_X86_MCE_AMD |
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extern bool amd_filter_mce(struct mce *m); |
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#else |
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static inline bool amd_filter_mce(struct mce *m) { return false; }; |
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#endif |
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__visible bool ex_handler_rdmsr_fault(const struct exception_table_entry *fixup, |
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struct pt_regs *regs, int trapnr, |
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unsigned long error_code, |
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unsigned long fault_addr); |
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__visible bool ex_handler_wrmsr_fault(const struct exception_table_entry *fixup, |
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struct pt_regs *regs, int trapnr, |
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unsigned long error_code, |
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unsigned long fault_addr); |
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#endif /* __X86_MCE_INTERNAL_H__ */
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