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705 lines
17 KiB
705 lines
17 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Machine check injection support. |
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* Copyright 2008 Intel Corporation. |
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* |
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* Authors: |
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* Andi Kleen |
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* Ying Huang |
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* |
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* The AMD part (from mce_amd_inj.c): a simple MCE injection facility |
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* for testing different aspects of the RAS code. This driver should be |
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* built as module so that it can be loaded on production kernels for |
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* testing purposes. |
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* |
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* Copyright (c) 2010-17: Borislav Petkov <[email protected]> |
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* Advanced Micro Devices Inc. |
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*/ |
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|
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#include <linux/cpu.h> |
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#include <linux/debugfs.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/notifier.h> |
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#include <linux/pci.h> |
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#include <linux/uaccess.h> |
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|
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#include <asm/amd_nb.h> |
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#include <asm/apic.h> |
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#include <asm/irq_vectors.h> |
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#include <asm/mce.h> |
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#include <asm/nmi.h> |
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#include <asm/smp.h> |
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#include "internal.h" |
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|
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/* |
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* Collect all the MCi_XXX settings |
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*/ |
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static struct mce i_mce; |
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static struct dentry *dfs_inj; |
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|
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#define MAX_FLAG_OPT_SIZE 4 |
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#define NBCFG 0x44 |
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|
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enum injection_type { |
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SW_INJ = 0, /* SW injection, simply decode the error */ |
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HW_INJ, /* Trigger a #MC */ |
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DFR_INT_INJ, /* Trigger Deferred error interrupt */ |
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THR_INT_INJ, /* Trigger threshold interrupt */ |
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N_INJ_TYPES, |
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}; |
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|
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static const char * const flags_options[] = { |
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[SW_INJ] = "sw", |
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[HW_INJ] = "hw", |
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[DFR_INT_INJ] = "df", |
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[THR_INT_INJ] = "th", |
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NULL |
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}; |
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|
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/* Set default injection to SW_INJ */ |
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static enum injection_type inj_type = SW_INJ; |
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|
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#define MCE_INJECT_SET(reg) \ |
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static int inj_##reg##_set(void *data, u64 val) \ |
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{ \ |
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struct mce *m = (struct mce *)data; \ |
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\ |
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m->reg = val; \ |
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return 0; \ |
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} |
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MCE_INJECT_SET(status); |
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MCE_INJECT_SET(misc); |
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MCE_INJECT_SET(addr); |
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MCE_INJECT_SET(synd); |
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|
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#define MCE_INJECT_GET(reg) \ |
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static int inj_##reg##_get(void *data, u64 *val) \ |
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{ \ |
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struct mce *m = (struct mce *)data; \ |
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\ |
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*val = m->reg; \ |
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return 0; \ |
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} |
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MCE_INJECT_GET(status); |
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MCE_INJECT_GET(misc); |
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MCE_INJECT_GET(addr); |
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MCE_INJECT_GET(synd); |
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DEFINE_SIMPLE_ATTRIBUTE(status_fops, inj_status_get, inj_status_set, "%llx\n"); |
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DEFINE_SIMPLE_ATTRIBUTE(misc_fops, inj_misc_get, inj_misc_set, "%llx\n"); |
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DEFINE_SIMPLE_ATTRIBUTE(addr_fops, inj_addr_get, inj_addr_set, "%llx\n"); |
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DEFINE_SIMPLE_ATTRIBUTE(synd_fops, inj_synd_get, inj_synd_set, "%llx\n"); |
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static void setup_inj_struct(struct mce *m) |
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{ |
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memset(m, 0, sizeof(struct mce)); |
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m->cpuvendor = boot_cpu_data.x86_vendor; |
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m->time = ktime_get_real_seconds(); |
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m->cpuid = cpuid_eax(1); |
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m->microcode = boot_cpu_data.microcode; |
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} |
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|
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/* Update fake mce registers on current CPU. */ |
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static void inject_mce(struct mce *m) |
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{ |
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struct mce *i = &per_cpu(injectm, m->extcpu); |
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|
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/* Make sure no one reads partially written injectm */ |
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i->finished = 0; |
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mb(); |
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m->finished = 0; |
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/* First set the fields after finished */ |
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i->extcpu = m->extcpu; |
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mb(); |
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/* Now write record in order, finished last (except above) */ |
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memcpy(i, m, sizeof(struct mce)); |
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/* Finally activate it */ |
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mb(); |
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i->finished = 1; |
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} |
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static void raise_poll(struct mce *m) |
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{ |
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unsigned long flags; |
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mce_banks_t b; |
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memset(&b, 0xff, sizeof(mce_banks_t)); |
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local_irq_save(flags); |
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machine_check_poll(0, &b); |
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local_irq_restore(flags); |
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m->finished = 0; |
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} |
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static void raise_exception(struct mce *m, struct pt_regs *pregs) |
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{ |
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struct pt_regs regs; |
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unsigned long flags; |
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if (!pregs) { |
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memset(®s, 0, sizeof(struct pt_regs)); |
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regs.ip = m->ip; |
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regs.cs = m->cs; |
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pregs = ®s; |
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} |
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/* do_machine_check() expects interrupts disabled -- at least */ |
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local_irq_save(flags); |
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do_machine_check(pregs); |
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local_irq_restore(flags); |
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m->finished = 0; |
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} |
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static cpumask_var_t mce_inject_cpumask; |
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static DEFINE_MUTEX(mce_inject_mutex); |
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static int mce_raise_notify(unsigned int cmd, struct pt_regs *regs) |
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{ |
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int cpu = smp_processor_id(); |
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struct mce *m = this_cpu_ptr(&injectm); |
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if (!cpumask_test_cpu(cpu, mce_inject_cpumask)) |
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return NMI_DONE; |
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cpumask_clear_cpu(cpu, mce_inject_cpumask); |
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if (m->inject_flags & MCJ_EXCEPTION) |
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raise_exception(m, regs); |
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else if (m->status) |
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raise_poll(m); |
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return NMI_HANDLED; |
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} |
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static void mce_irq_ipi(void *info) |
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{ |
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int cpu = smp_processor_id(); |
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struct mce *m = this_cpu_ptr(&injectm); |
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if (cpumask_test_cpu(cpu, mce_inject_cpumask) && |
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m->inject_flags & MCJ_EXCEPTION) { |
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cpumask_clear_cpu(cpu, mce_inject_cpumask); |
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raise_exception(m, NULL); |
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} |
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} |
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/* Inject mce on current CPU */ |
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static int raise_local(void) |
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{ |
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struct mce *m = this_cpu_ptr(&injectm); |
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int context = MCJ_CTX(m->inject_flags); |
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int ret = 0; |
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int cpu = m->extcpu; |
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if (m->inject_flags & MCJ_EXCEPTION) { |
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pr_info("Triggering MCE exception on CPU %d\n", cpu); |
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switch (context) { |
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case MCJ_CTX_IRQ: |
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/* |
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* Could do more to fake interrupts like |
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* calling irq_enter, but the necessary |
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* machinery isn't exported currently. |
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*/ |
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fallthrough; |
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case MCJ_CTX_PROCESS: |
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raise_exception(m, NULL); |
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break; |
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default: |
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pr_info("Invalid MCE context\n"); |
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ret = -EINVAL; |
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} |
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pr_info("MCE exception done on CPU %d\n", cpu); |
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} else if (m->status) { |
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pr_info("Starting machine check poll CPU %d\n", cpu); |
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raise_poll(m); |
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mce_notify_irq(); |
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pr_info("Machine check poll done on CPU %d\n", cpu); |
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} else |
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m->finished = 0; |
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return ret; |
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} |
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static void __maybe_unused raise_mce(struct mce *m) |
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{ |
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int context = MCJ_CTX(m->inject_flags); |
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inject_mce(m); |
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if (context == MCJ_CTX_RANDOM) |
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return; |
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if (m->inject_flags & (MCJ_IRQ_BROADCAST | MCJ_NMI_BROADCAST)) { |
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unsigned long start; |
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int cpu; |
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get_online_cpus(); |
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cpumask_copy(mce_inject_cpumask, cpu_online_mask); |
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cpumask_clear_cpu(get_cpu(), mce_inject_cpumask); |
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for_each_online_cpu(cpu) { |
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struct mce *mcpu = &per_cpu(injectm, cpu); |
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if (!mcpu->finished || |
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MCJ_CTX(mcpu->inject_flags) != MCJ_CTX_RANDOM) |
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cpumask_clear_cpu(cpu, mce_inject_cpumask); |
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} |
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if (!cpumask_empty(mce_inject_cpumask)) { |
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if (m->inject_flags & MCJ_IRQ_BROADCAST) { |
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/* |
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* don't wait because mce_irq_ipi is necessary |
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* to be sync with following raise_local |
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*/ |
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preempt_disable(); |
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smp_call_function_many(mce_inject_cpumask, |
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mce_irq_ipi, NULL, 0); |
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preempt_enable(); |
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} else if (m->inject_flags & MCJ_NMI_BROADCAST) |
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apic->send_IPI_mask(mce_inject_cpumask, |
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NMI_VECTOR); |
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} |
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start = jiffies; |
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while (!cpumask_empty(mce_inject_cpumask)) { |
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if (!time_before(jiffies, start + 2*HZ)) { |
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pr_err("Timeout waiting for mce inject %lx\n", |
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*cpumask_bits(mce_inject_cpumask)); |
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break; |
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} |
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cpu_relax(); |
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} |
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raise_local(); |
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put_cpu(); |
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put_online_cpus(); |
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} else { |
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preempt_disable(); |
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raise_local(); |
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preempt_enable(); |
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} |
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} |
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static int mce_inject_raise(struct notifier_block *nb, unsigned long val, |
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void *data) |
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{ |
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struct mce *m = (struct mce *)data; |
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if (!m) |
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return NOTIFY_DONE; |
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mutex_lock(&mce_inject_mutex); |
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raise_mce(m); |
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mutex_unlock(&mce_inject_mutex); |
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return NOTIFY_DONE; |
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} |
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static struct notifier_block inject_nb = { |
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.notifier_call = mce_inject_raise, |
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}; |
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/* |
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* Caller needs to be make sure this cpu doesn't disappear |
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* from under us, i.e.: get_cpu/put_cpu. |
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*/ |
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static int toggle_hw_mce_inject(unsigned int cpu, bool enable) |
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{ |
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u32 l, h; |
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int err; |
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err = rdmsr_on_cpu(cpu, MSR_K7_HWCR, &l, &h); |
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if (err) { |
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pr_err("%s: error reading HWCR\n", __func__); |
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return err; |
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} |
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enable ? (l |= BIT(18)) : (l &= ~BIT(18)); |
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err = wrmsr_on_cpu(cpu, MSR_K7_HWCR, l, h); |
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if (err) |
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pr_err("%s: error writing HWCR\n", __func__); |
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return err; |
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} |
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static int __set_inj(const char *buf) |
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{ |
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int i; |
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for (i = 0; i < N_INJ_TYPES; i++) { |
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if (!strncmp(flags_options[i], buf, strlen(flags_options[i]))) { |
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inj_type = i; |
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return 0; |
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} |
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} |
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return -EINVAL; |
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} |
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static ssize_t flags_read(struct file *filp, char __user *ubuf, |
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size_t cnt, loff_t *ppos) |
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{ |
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char buf[MAX_FLAG_OPT_SIZE]; |
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int n; |
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n = sprintf(buf, "%s\n", flags_options[inj_type]); |
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return simple_read_from_buffer(ubuf, cnt, ppos, buf, n); |
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} |
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static ssize_t flags_write(struct file *filp, const char __user *ubuf, |
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size_t cnt, loff_t *ppos) |
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{ |
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char buf[MAX_FLAG_OPT_SIZE], *__buf; |
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int err; |
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if (cnt > MAX_FLAG_OPT_SIZE) |
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return -EINVAL; |
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if (copy_from_user(&buf, ubuf, cnt)) |
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return -EFAULT; |
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buf[cnt - 1] = 0; |
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/* strip whitespace */ |
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__buf = strstrip(buf); |
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err = __set_inj(__buf); |
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if (err) { |
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pr_err("%s: Invalid flags value: %s\n", __func__, __buf); |
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return err; |
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} |
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*ppos += cnt; |
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return cnt; |
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} |
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static const struct file_operations flags_fops = { |
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.read = flags_read, |
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.write = flags_write, |
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.llseek = generic_file_llseek, |
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}; |
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/* |
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* On which CPU to inject? |
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*/ |
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MCE_INJECT_GET(extcpu); |
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static int inj_extcpu_set(void *data, u64 val) |
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{ |
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struct mce *m = (struct mce *)data; |
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if (val >= nr_cpu_ids || !cpu_online(val)) { |
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pr_err("%s: Invalid CPU: %llu\n", __func__, val); |
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return -EINVAL; |
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} |
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m->extcpu = val; |
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return 0; |
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} |
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DEFINE_SIMPLE_ATTRIBUTE(extcpu_fops, inj_extcpu_get, inj_extcpu_set, "%llu\n"); |
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static void trigger_mce(void *info) |
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{ |
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asm volatile("int $18"); |
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} |
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static void trigger_dfr_int(void *info) |
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{ |
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asm volatile("int %0" :: "i" (DEFERRED_ERROR_VECTOR)); |
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} |
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static void trigger_thr_int(void *info) |
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{ |
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asm volatile("int %0" :: "i" (THRESHOLD_APIC_VECTOR)); |
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} |
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static u32 get_nbc_for_node(int node_id) |
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{ |
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struct cpuinfo_x86 *c = &boot_cpu_data; |
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u32 cores_per_node; |
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cores_per_node = (c->x86_max_cores * smp_num_siblings) / amd_get_nodes_per_socket(); |
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return cores_per_node * node_id; |
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} |
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static void toggle_nb_mca_mst_cpu(u16 nid) |
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{ |
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struct amd_northbridge *nb; |
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struct pci_dev *F3; |
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u32 val; |
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int err; |
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nb = node_to_amd_nb(nid); |
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if (!nb) |
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return; |
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F3 = nb->misc; |
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if (!F3) |
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return; |
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err = pci_read_config_dword(F3, NBCFG, &val); |
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if (err) { |
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pr_err("%s: Error reading F%dx%03x.\n", |
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__func__, PCI_FUNC(F3->devfn), NBCFG); |
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return; |
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} |
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if (val & BIT(27)) |
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return; |
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pr_err("%s: Set D18F3x44[NbMcaToMstCpuEn] which BIOS hasn't done.\n", |
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__func__); |
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val |= BIT(27); |
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err = pci_write_config_dword(F3, NBCFG, val); |
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if (err) |
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pr_err("%s: Error writing F%dx%03x.\n", |
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__func__, PCI_FUNC(F3->devfn), NBCFG); |
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} |
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static void prepare_msrs(void *info) |
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{ |
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struct mce m = *(struct mce *)info; |
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u8 b = m.bank; |
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wrmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus); |
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if (boot_cpu_has(X86_FEATURE_SMCA)) { |
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if (m.inject_flags == DFR_INT_INJ) { |
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wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(b), m.status); |
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wrmsrl(MSR_AMD64_SMCA_MCx_DEADDR(b), m.addr); |
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} else { |
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wrmsrl(MSR_AMD64_SMCA_MCx_STATUS(b), m.status); |
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wrmsrl(MSR_AMD64_SMCA_MCx_ADDR(b), m.addr); |
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} |
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wrmsrl(MSR_AMD64_SMCA_MCx_MISC(b), m.misc); |
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wrmsrl(MSR_AMD64_SMCA_MCx_SYND(b), m.synd); |
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} else { |
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wrmsrl(MSR_IA32_MCx_STATUS(b), m.status); |
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wrmsrl(MSR_IA32_MCx_ADDR(b), m.addr); |
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wrmsrl(MSR_IA32_MCx_MISC(b), m.misc); |
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} |
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} |
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static void do_inject(void) |
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{ |
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u64 mcg_status = 0; |
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unsigned int cpu = i_mce.extcpu; |
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u8 b = i_mce.bank; |
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i_mce.tsc = rdtsc_ordered(); |
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if (i_mce.misc) |
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i_mce.status |= MCI_STATUS_MISCV; |
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if (i_mce.synd) |
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i_mce.status |= MCI_STATUS_SYNDV; |
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if (inj_type == SW_INJ) { |
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mce_log(&i_mce); |
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return; |
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} |
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/* prep MCE global settings for the injection */ |
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mcg_status = MCG_STATUS_MCIP | MCG_STATUS_EIPV; |
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if (!(i_mce.status & MCI_STATUS_PCC)) |
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mcg_status |= MCG_STATUS_RIPV; |
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|
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/* |
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* Ensure necessary status bits for deferred errors: |
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* - MCx_STATUS[Deferred]: make sure it is a deferred error |
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* - MCx_STATUS[UC] cleared: deferred errors are _not_ UC |
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*/ |
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if (inj_type == DFR_INT_INJ) { |
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i_mce.status |= MCI_STATUS_DEFERRED; |
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i_mce.status &= ~MCI_STATUS_UC; |
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} |
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|
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/* |
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* For multi node CPUs, logging and reporting of bank 4 errors happens |
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* only on the node base core. Refer to D18F3x44[NbMcaToMstCpuEn] for |
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* Fam10h and later BKDGs. |
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*/ |
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if (boot_cpu_has(X86_FEATURE_AMD_DCM) && |
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b == 4 && |
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boot_cpu_data.x86 < 0x17) { |
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toggle_nb_mca_mst_cpu(topology_die_id(cpu)); |
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cpu = get_nbc_for_node(topology_die_id(cpu)); |
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} |
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get_online_cpus(); |
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if (!cpu_online(cpu)) |
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goto err; |
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toggle_hw_mce_inject(cpu, true); |
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|
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i_mce.mcgstatus = mcg_status; |
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i_mce.inject_flags = inj_type; |
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smp_call_function_single(cpu, prepare_msrs, &i_mce, 0); |
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toggle_hw_mce_inject(cpu, false); |
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|
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switch (inj_type) { |
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case DFR_INT_INJ: |
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smp_call_function_single(cpu, trigger_dfr_int, NULL, 0); |
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break; |
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case THR_INT_INJ: |
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smp_call_function_single(cpu, trigger_thr_int, NULL, 0); |
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break; |
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default: |
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smp_call_function_single(cpu, trigger_mce, NULL, 0); |
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} |
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err: |
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put_online_cpus(); |
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|
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} |
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|
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/* |
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* This denotes into which bank we're injecting and triggers |
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* the injection, at the same time. |
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*/ |
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static int inj_bank_set(void *data, u64 val) |
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{ |
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struct mce *m = (struct mce *)data; |
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u8 n_banks; |
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u64 cap; |
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|
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/* Get bank count on target CPU so we can handle non-uniform values. */ |
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rdmsrl_on_cpu(m->extcpu, MSR_IA32_MCG_CAP, &cap); |
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n_banks = cap & MCG_BANKCNT_MASK; |
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|
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if (val >= n_banks) { |
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pr_err("MCA bank %llu non-existent on CPU%d\n", val, m->extcpu); |
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return -EINVAL; |
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} |
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m->bank = val; |
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do_inject(); |
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|
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/* Reset injection struct */ |
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setup_inj_struct(&i_mce); |
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|
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return 0; |
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} |
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MCE_INJECT_GET(bank); |
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|
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DEFINE_SIMPLE_ATTRIBUTE(bank_fops, inj_bank_get, inj_bank_set, "%llu\n"); |
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|
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static const char readme_msg[] = |
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"Description of the files and their usages:\n" |
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"\n" |
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"Note1: i refers to the bank number below.\n" |
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"Note2: See respective BKDGs for the exact bit definitions of the files below\n" |
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"as they mirror the hardware registers.\n" |
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"\n" |
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"status:\t Set MCi_STATUS: the bits in that MSR control the error type and\n" |
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"\t attributes of the error which caused the MCE.\n" |
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"\n" |
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"misc:\t Set MCi_MISC: provide auxiliary info about the error. It is mostly\n" |
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"\t used for error thresholding purposes and its validity is indicated by\n" |
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"\t MCi_STATUS[MiscV].\n" |
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"\n" |
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"synd:\t Set MCi_SYND: provide syndrome info about the error. Only valid on\n" |
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"\t Scalable MCA systems, and its validity is indicated by MCi_STATUS[SyndV].\n" |
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"\n" |
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"addr:\t Error address value to be written to MCi_ADDR. Log address information\n" |
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"\t associated with the error.\n" |
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"\n" |
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"cpu:\t The CPU to inject the error on.\n" |
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"\n" |
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"bank:\t Specify the bank you want to inject the error into: the number of\n" |
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"\t banks in a processor varies and is family/model-specific, therefore, the\n" |
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"\t supplied value is sanity-checked. Setting the bank value also triggers the\n" |
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"\t injection.\n" |
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"\n" |
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"flags:\t Injection type to be performed. Writing to this file will trigger a\n" |
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"\t real machine check, an APIC interrupt or invoke the error decoder routines\n" |
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"\t for AMD processors.\n" |
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"\n" |
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"\t Allowed error injection types:\n" |
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"\t - \"sw\": Software error injection. Decode error to a human-readable \n" |
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"\t format only. Safe to use.\n" |
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"\t - \"hw\": Hardware error injection. Causes the #MC exception handler to \n" |
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"\t handle the error. Be warned: might cause system panic if MCi_STATUS[PCC] \n" |
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"\t is set. Therefore, consider setting (debugfs_mountpoint)/mce/fake_panic \n" |
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"\t before injecting.\n" |
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"\t - \"df\": Trigger APIC interrupt for Deferred error. Causes deferred \n" |
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"\t error APIC interrupt handler to handle the error if the feature is \n" |
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"\t is present in hardware. \n" |
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"\t - \"th\": Trigger APIC interrupt for Threshold errors. Causes threshold \n" |
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"\t APIC interrupt handler to handle the error. \n" |
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"\n"; |
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|
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static ssize_t |
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inj_readme_read(struct file *filp, char __user *ubuf, |
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size_t cnt, loff_t *ppos) |
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{ |
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return simple_read_from_buffer(ubuf, cnt, ppos, |
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readme_msg, strlen(readme_msg)); |
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} |
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|
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static const struct file_operations readme_fops = { |
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.read = inj_readme_read, |
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}; |
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|
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static struct dfs_node { |
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char *name; |
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const struct file_operations *fops; |
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umode_t perm; |
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} dfs_fls[] = { |
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{ .name = "status", .fops = &status_fops, .perm = S_IRUSR | S_IWUSR }, |
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{ .name = "misc", .fops = &misc_fops, .perm = S_IRUSR | S_IWUSR }, |
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{ .name = "addr", .fops = &addr_fops, .perm = S_IRUSR | S_IWUSR }, |
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{ .name = "synd", .fops = &synd_fops, .perm = S_IRUSR | S_IWUSR }, |
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{ .name = "bank", .fops = &bank_fops, .perm = S_IRUSR | S_IWUSR }, |
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{ .name = "flags", .fops = &flags_fops, .perm = S_IRUSR | S_IWUSR }, |
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{ .name = "cpu", .fops = &extcpu_fops, .perm = S_IRUSR | S_IWUSR }, |
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{ .name = "README", .fops = &readme_fops, .perm = S_IRUSR | S_IRGRP | S_IROTH }, |
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}; |
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|
|
static void __init debugfs_init(void) |
|
{ |
|
unsigned int i; |
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|
|
dfs_inj = debugfs_create_dir("mce-inject", NULL); |
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|
|
for (i = 0; i < ARRAY_SIZE(dfs_fls); i++) |
|
debugfs_create_file(dfs_fls[i].name, dfs_fls[i].perm, dfs_inj, |
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&i_mce, dfs_fls[i].fops); |
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} |
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|
|
static int __init inject_init(void) |
|
{ |
|
if (!alloc_cpumask_var(&mce_inject_cpumask, GFP_KERNEL)) |
|
return -ENOMEM; |
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|
|
debugfs_init(); |
|
|
|
register_nmi_handler(NMI_LOCAL, mce_raise_notify, 0, "mce_notify"); |
|
mce_register_injector_chain(&inject_nb); |
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|
|
setup_inj_struct(&i_mce); |
|
|
|
pr_info("Machine check injector initialized\n"); |
|
|
|
return 0; |
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} |
|
|
|
static void __exit inject_exit(void) |
|
{ |
|
|
|
mce_unregister_injector_chain(&inject_nb); |
|
unregister_nmi_handler(NMI_LOCAL, "mce_notify"); |
|
|
|
debugfs_remove_recursive(dfs_inj); |
|
dfs_inj = NULL; |
|
|
|
memset(&dfs_fls, 0, sizeof(dfs_fls)); |
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|
|
free_cpumask_var(mce_inject_cpumask); |
|
} |
|
|
|
module_init(inject_init); |
|
module_exit(inject_exit); |
|
MODULE_LICENSE("GPL");
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