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334 lines
8.1 KiB
334 lines
8.1 KiB
/* |
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file "COPYING" in the main directory of this archive |
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* for more details. |
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* |
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* Numascale NumaConnect-Specific APIC Code |
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* |
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* Copyright (C) 2011 Numascale AS. All rights reserved. |
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* |
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* Send feedback to <[email protected]> |
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* |
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*/ |
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#include <linux/types.h> |
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#include <linux/init.h> |
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#include <linux/pgtable.h> |
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#include <asm/numachip/numachip.h> |
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#include <asm/numachip/numachip_csr.h> |
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#include "local.h" |
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u8 numachip_system __read_mostly; |
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static const struct apic apic_numachip1; |
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static const struct apic apic_numachip2; |
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static void (*numachip_apic_icr_write)(int apicid, unsigned int val) __read_mostly; |
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static unsigned int numachip1_get_apic_id(unsigned long x) |
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{ |
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unsigned long value; |
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unsigned int id = (x >> 24) & 0xff; |
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if (static_cpu_has(X86_FEATURE_NODEID_MSR)) { |
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rdmsrl(MSR_FAM10H_NODE_ID, value); |
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id |= (value << 2) & 0xff00; |
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} |
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return id; |
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} |
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static u32 numachip1_set_apic_id(unsigned int id) |
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{ |
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return (id & 0xff) << 24; |
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} |
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static unsigned int numachip2_get_apic_id(unsigned long x) |
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{ |
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u64 mcfg; |
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rdmsrl(MSR_FAM10H_MMIO_CONF_BASE, mcfg); |
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return ((mcfg >> (28 - 8)) & 0xfff00) | (x >> 24); |
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} |
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static u32 numachip2_set_apic_id(unsigned int id) |
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{ |
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return id << 24; |
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} |
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static int numachip_apic_id_valid(u32 apicid) |
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{ |
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/* Trust what bootloader passes in MADT */ |
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return 1; |
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} |
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static int numachip_apic_id_registered(void) |
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{ |
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return 1; |
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} |
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static int numachip_phys_pkg_id(int initial_apic_id, int index_msb) |
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{ |
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return initial_apic_id >> index_msb; |
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} |
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static void numachip1_apic_icr_write(int apicid, unsigned int val) |
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{ |
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write_lcsr(CSR_G3_EXT_IRQ_GEN, (apicid << 16) | val); |
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} |
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static void numachip2_apic_icr_write(int apicid, unsigned int val) |
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{ |
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numachip2_write32_lcsr(NUMACHIP2_APIC_ICR, (apicid << 12) | val); |
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} |
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static int numachip_wakeup_secondary(int phys_apicid, unsigned long start_rip) |
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{ |
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numachip_apic_icr_write(phys_apicid, APIC_DM_INIT); |
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numachip_apic_icr_write(phys_apicid, APIC_DM_STARTUP | |
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(start_rip >> 12)); |
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return 0; |
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} |
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static void numachip_send_IPI_one(int cpu, int vector) |
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{ |
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int local_apicid, apicid = per_cpu(x86_cpu_to_apicid, cpu); |
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unsigned int dmode; |
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preempt_disable(); |
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local_apicid = __this_cpu_read(x86_cpu_to_apicid); |
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/* Send via local APIC where non-local part matches */ |
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if (!((apicid ^ local_apicid) >> NUMACHIP_LAPIC_BITS)) { |
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unsigned long flags; |
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local_irq_save(flags); |
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__default_send_IPI_dest_field(apicid, vector, |
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APIC_DEST_PHYSICAL); |
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local_irq_restore(flags); |
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preempt_enable(); |
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return; |
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} |
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preempt_enable(); |
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dmode = (vector == NMI_VECTOR) ? APIC_DM_NMI : APIC_DM_FIXED; |
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numachip_apic_icr_write(apicid, dmode | vector); |
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} |
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static void numachip_send_IPI_mask(const struct cpumask *mask, int vector) |
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{ |
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unsigned int cpu; |
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for_each_cpu(cpu, mask) |
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numachip_send_IPI_one(cpu, vector); |
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} |
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static void numachip_send_IPI_mask_allbutself(const struct cpumask *mask, |
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int vector) |
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{ |
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unsigned int this_cpu = smp_processor_id(); |
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unsigned int cpu; |
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for_each_cpu(cpu, mask) { |
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if (cpu != this_cpu) |
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numachip_send_IPI_one(cpu, vector); |
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} |
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} |
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static void numachip_send_IPI_allbutself(int vector) |
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{ |
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unsigned int this_cpu = smp_processor_id(); |
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unsigned int cpu; |
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for_each_online_cpu(cpu) { |
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if (cpu != this_cpu) |
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numachip_send_IPI_one(cpu, vector); |
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} |
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} |
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static void numachip_send_IPI_all(int vector) |
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{ |
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numachip_send_IPI_mask(cpu_online_mask, vector); |
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} |
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static void numachip_send_IPI_self(int vector) |
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{ |
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apic_write(APIC_SELF_IPI, vector); |
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} |
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static int __init numachip1_probe(void) |
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{ |
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return apic == &apic_numachip1; |
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} |
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static int __init numachip2_probe(void) |
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{ |
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return apic == &apic_numachip2; |
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} |
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static void fixup_cpu_id(struct cpuinfo_x86 *c, int node) |
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{ |
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u64 val; |
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u32 nodes = 1; |
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this_cpu_write(cpu_llc_id, node); |
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/* Account for nodes per socket in multi-core-module processors */ |
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if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) { |
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rdmsrl(MSR_FAM10H_NODE_ID, val); |
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nodes = ((val >> 3) & 7) + 1; |
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} |
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c->phys_proc_id = node / nodes; |
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} |
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static int __init numachip_system_init(void) |
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{ |
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/* Map the LCSR area and set up the apic_icr_write function */ |
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switch (numachip_system) { |
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case 1: |
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init_extra_mapping_uc(NUMACHIP_LCSR_BASE, NUMACHIP_LCSR_SIZE); |
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numachip_apic_icr_write = numachip1_apic_icr_write; |
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break; |
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case 2: |
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init_extra_mapping_uc(NUMACHIP2_LCSR_BASE, NUMACHIP2_LCSR_SIZE); |
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numachip_apic_icr_write = numachip2_apic_icr_write; |
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break; |
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default: |
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return 0; |
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} |
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x86_cpuinit.fixup_cpu_id = fixup_cpu_id; |
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x86_init.pci.arch_init = pci_numachip_init; |
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return 0; |
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} |
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early_initcall(numachip_system_init); |
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static int numachip1_acpi_madt_oem_check(char *oem_id, char *oem_table_id) |
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{ |
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if ((strncmp(oem_id, "NUMASC", 6) != 0) || |
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(strncmp(oem_table_id, "NCONNECT", 8) != 0)) |
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return 0; |
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numachip_system = 1; |
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return 1; |
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} |
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static int numachip2_acpi_madt_oem_check(char *oem_id, char *oem_table_id) |
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{ |
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if ((strncmp(oem_id, "NUMASC", 6) != 0) || |
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(strncmp(oem_table_id, "NCONECT2", 8) != 0)) |
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return 0; |
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numachip_system = 2; |
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return 1; |
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} |
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/* APIC IPIs are queued */ |
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static void numachip_apic_wait_icr_idle(void) |
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{ |
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} |
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/* APIC NMI IPIs are queued */ |
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static u32 numachip_safe_apic_wait_icr_idle(void) |
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{ |
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return 0; |
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} |
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static const struct apic apic_numachip1 __refconst = { |
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.name = "NumaConnect system", |
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.probe = numachip1_probe, |
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.acpi_madt_oem_check = numachip1_acpi_madt_oem_check, |
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.apic_id_valid = numachip_apic_id_valid, |
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.apic_id_registered = numachip_apic_id_registered, |
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.delivery_mode = APIC_DELIVERY_MODE_FIXED, |
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.dest_mode_logical = false, |
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.disable_esr = 0, |
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.check_apicid_used = NULL, |
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.init_apic_ldr = flat_init_apic_ldr, |
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.ioapic_phys_id_map = NULL, |
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.setup_apic_routing = NULL, |
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.cpu_present_to_apicid = default_cpu_present_to_apicid, |
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.apicid_to_cpu_present = NULL, |
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.check_phys_apicid_present = default_check_phys_apicid_present, |
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.phys_pkg_id = numachip_phys_pkg_id, |
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.get_apic_id = numachip1_get_apic_id, |
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.set_apic_id = numachip1_set_apic_id, |
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.calc_dest_apicid = apic_default_calc_apicid, |
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.send_IPI = numachip_send_IPI_one, |
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.send_IPI_mask = numachip_send_IPI_mask, |
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.send_IPI_mask_allbutself = numachip_send_IPI_mask_allbutself, |
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.send_IPI_allbutself = numachip_send_IPI_allbutself, |
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.send_IPI_all = numachip_send_IPI_all, |
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.send_IPI_self = numachip_send_IPI_self, |
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.wakeup_secondary_cpu = numachip_wakeup_secondary, |
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.inquire_remote_apic = NULL, /* REMRD not supported */ |
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.read = native_apic_mem_read, |
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.write = native_apic_mem_write, |
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.eoi_write = native_apic_mem_write, |
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.icr_read = native_apic_icr_read, |
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.icr_write = native_apic_icr_write, |
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.wait_icr_idle = numachip_apic_wait_icr_idle, |
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.safe_wait_icr_idle = numachip_safe_apic_wait_icr_idle, |
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}; |
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apic_driver(apic_numachip1); |
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static const struct apic apic_numachip2 __refconst = { |
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.name = "NumaConnect2 system", |
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.probe = numachip2_probe, |
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.acpi_madt_oem_check = numachip2_acpi_madt_oem_check, |
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.apic_id_valid = numachip_apic_id_valid, |
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.apic_id_registered = numachip_apic_id_registered, |
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.delivery_mode = APIC_DELIVERY_MODE_FIXED, |
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.dest_mode_logical = false, |
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.disable_esr = 0, |
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.check_apicid_used = NULL, |
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.init_apic_ldr = flat_init_apic_ldr, |
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.ioapic_phys_id_map = NULL, |
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.setup_apic_routing = NULL, |
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.cpu_present_to_apicid = default_cpu_present_to_apicid, |
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.apicid_to_cpu_present = NULL, |
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.check_phys_apicid_present = default_check_phys_apicid_present, |
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.phys_pkg_id = numachip_phys_pkg_id, |
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.get_apic_id = numachip2_get_apic_id, |
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.set_apic_id = numachip2_set_apic_id, |
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.calc_dest_apicid = apic_default_calc_apicid, |
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.send_IPI = numachip_send_IPI_one, |
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.send_IPI_mask = numachip_send_IPI_mask, |
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.send_IPI_mask_allbutself = numachip_send_IPI_mask_allbutself, |
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.send_IPI_allbutself = numachip_send_IPI_allbutself, |
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.send_IPI_all = numachip_send_IPI_all, |
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.send_IPI_self = numachip_send_IPI_self, |
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.wakeup_secondary_cpu = numachip_wakeup_secondary, |
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.inquire_remote_apic = NULL, /* REMRD not supported */ |
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.read = native_apic_mem_read, |
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.write = native_apic_mem_write, |
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.eoi_write = native_apic_mem_write, |
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.icr_read = native_apic_icr_read, |
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.icr_write = native_apic_icr_write, |
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.wait_icr_idle = numachip_apic_wait_icr_idle, |
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.safe_wait_icr_idle = numachip_safe_apic_wait_icr_idle, |
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}; |
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apic_driver(apic_numachip2);
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