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559 lines
14 KiB
559 lines
14 KiB
/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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#ifndef _ASM_X86_XOR_32_H |
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#define _ASM_X86_XOR_32_H |
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|
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/* |
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* Optimized RAID-5 checksumming functions for MMX. |
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*/ |
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|
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/* |
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* High-speed RAID5 checksumming functions utilizing MMX instructions. |
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* Copyright (C) 1998 Ingo Molnar. |
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*/ |
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|
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#define LD(x, y) " movq 8*("#x")(%1), %%mm"#y" ;\n" |
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#define ST(x, y) " movq %%mm"#y", 8*("#x")(%1) ;\n" |
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#define XO1(x, y) " pxor 8*("#x")(%2), %%mm"#y" ;\n" |
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#define XO2(x, y) " pxor 8*("#x")(%3), %%mm"#y" ;\n" |
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#define XO3(x, y) " pxor 8*("#x")(%4), %%mm"#y" ;\n" |
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#define XO4(x, y) " pxor 8*("#x")(%5), %%mm"#y" ;\n" |
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|
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#include <asm/fpu/api.h> |
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|
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static void |
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xor_pII_mmx_2(unsigned long bytes, unsigned long *p1, unsigned long *p2) |
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{ |
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unsigned long lines = bytes >> 7; |
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kernel_fpu_begin(); |
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asm volatile( |
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#undef BLOCK |
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#define BLOCK(i) \ |
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LD(i, 0) \ |
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LD(i + 1, 1) \ |
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LD(i + 2, 2) \ |
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LD(i + 3, 3) \ |
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XO1(i, 0) \ |
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ST(i, 0) \ |
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XO1(i+1, 1) \ |
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ST(i+1, 1) \ |
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XO1(i + 2, 2) \ |
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ST(i + 2, 2) \ |
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XO1(i + 3, 3) \ |
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ST(i + 3, 3) |
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|
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" .align 32 ;\n" |
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" 1: ;\n" |
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BLOCK(0) |
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BLOCK(4) |
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BLOCK(8) |
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BLOCK(12) |
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|
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" addl $128, %1 ;\n" |
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" addl $128, %2 ;\n" |
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" decl %0 ;\n" |
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" jnz 1b ;\n" |
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: "+r" (lines), |
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"+r" (p1), "+r" (p2) |
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: |
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: "memory"); |
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|
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kernel_fpu_end(); |
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} |
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static void |
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xor_pII_mmx_3(unsigned long bytes, unsigned long *p1, unsigned long *p2, |
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unsigned long *p3) |
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{ |
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unsigned long lines = bytes >> 7; |
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kernel_fpu_begin(); |
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asm volatile( |
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#undef BLOCK |
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#define BLOCK(i) \ |
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LD(i, 0) \ |
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LD(i + 1, 1) \ |
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LD(i + 2, 2) \ |
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LD(i + 3, 3) \ |
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XO1(i, 0) \ |
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XO1(i + 1, 1) \ |
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XO1(i + 2, 2) \ |
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XO1(i + 3, 3) \ |
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XO2(i, 0) \ |
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ST(i, 0) \ |
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XO2(i + 1, 1) \ |
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ST(i + 1, 1) \ |
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XO2(i + 2, 2) \ |
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ST(i + 2, 2) \ |
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XO2(i + 3, 3) \ |
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ST(i + 3, 3) |
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|
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" .align 32 ;\n" |
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" 1: ;\n" |
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BLOCK(0) |
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BLOCK(4) |
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BLOCK(8) |
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BLOCK(12) |
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|
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" addl $128, %1 ;\n" |
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" addl $128, %2 ;\n" |
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" addl $128, %3 ;\n" |
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" decl %0 ;\n" |
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" jnz 1b ;\n" |
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: "+r" (lines), |
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"+r" (p1), "+r" (p2), "+r" (p3) |
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: |
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: "memory"); |
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kernel_fpu_end(); |
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} |
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static void |
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xor_pII_mmx_4(unsigned long bytes, unsigned long *p1, unsigned long *p2, |
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unsigned long *p3, unsigned long *p4) |
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{ |
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unsigned long lines = bytes >> 7; |
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kernel_fpu_begin(); |
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asm volatile( |
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#undef BLOCK |
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#define BLOCK(i) \ |
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LD(i, 0) \ |
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LD(i + 1, 1) \ |
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LD(i + 2, 2) \ |
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LD(i + 3, 3) \ |
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XO1(i, 0) \ |
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XO1(i + 1, 1) \ |
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XO1(i + 2, 2) \ |
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XO1(i + 3, 3) \ |
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XO2(i, 0) \ |
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XO2(i + 1, 1) \ |
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XO2(i + 2, 2) \ |
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XO2(i + 3, 3) \ |
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XO3(i, 0) \ |
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ST(i, 0) \ |
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XO3(i + 1, 1) \ |
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ST(i + 1, 1) \ |
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XO3(i + 2, 2) \ |
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ST(i + 2, 2) \ |
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XO3(i + 3, 3) \ |
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ST(i + 3, 3) |
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|
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" .align 32 ;\n" |
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" 1: ;\n" |
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BLOCK(0) |
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BLOCK(4) |
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BLOCK(8) |
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BLOCK(12) |
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" addl $128, %1 ;\n" |
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" addl $128, %2 ;\n" |
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" addl $128, %3 ;\n" |
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" addl $128, %4 ;\n" |
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" decl %0 ;\n" |
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" jnz 1b ;\n" |
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: "+r" (lines), |
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"+r" (p1), "+r" (p2), "+r" (p3), "+r" (p4) |
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: |
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: "memory"); |
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kernel_fpu_end(); |
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} |
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static void |
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xor_pII_mmx_5(unsigned long bytes, unsigned long *p1, unsigned long *p2, |
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unsigned long *p3, unsigned long *p4, unsigned long *p5) |
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{ |
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unsigned long lines = bytes >> 7; |
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kernel_fpu_begin(); |
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/* Make sure GCC forgets anything it knows about p4 or p5, |
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such that it won't pass to the asm volatile below a |
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register that is shared with any other variable. That's |
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because we modify p4 and p5 there, but we can't mark them |
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as read/write, otherwise we'd overflow the 10-asm-operands |
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limit of GCC < 3.1. */ |
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asm("" : "+r" (p4), "+r" (p5)); |
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asm volatile( |
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#undef BLOCK |
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#define BLOCK(i) \ |
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LD(i, 0) \ |
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LD(i + 1, 1) \ |
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LD(i + 2, 2) \ |
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LD(i + 3, 3) \ |
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XO1(i, 0) \ |
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XO1(i + 1, 1) \ |
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XO1(i + 2, 2) \ |
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XO1(i + 3, 3) \ |
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XO2(i, 0) \ |
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XO2(i + 1, 1) \ |
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XO2(i + 2, 2) \ |
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XO2(i + 3, 3) \ |
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XO3(i, 0) \ |
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XO3(i + 1, 1) \ |
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XO3(i + 2, 2) \ |
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XO3(i + 3, 3) \ |
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XO4(i, 0) \ |
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ST(i, 0) \ |
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XO4(i + 1, 1) \ |
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ST(i + 1, 1) \ |
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XO4(i + 2, 2) \ |
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ST(i + 2, 2) \ |
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XO4(i + 3, 3) \ |
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ST(i + 3, 3) |
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" .align 32 ;\n" |
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" 1: ;\n" |
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BLOCK(0) |
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BLOCK(4) |
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BLOCK(8) |
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BLOCK(12) |
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|
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" addl $128, %1 ;\n" |
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" addl $128, %2 ;\n" |
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" addl $128, %3 ;\n" |
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" addl $128, %4 ;\n" |
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" addl $128, %5 ;\n" |
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" decl %0 ;\n" |
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" jnz 1b ;\n" |
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: "+r" (lines), |
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"+r" (p1), "+r" (p2), "+r" (p3) |
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: "r" (p4), "r" (p5) |
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: "memory"); |
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/* p4 and p5 were modified, and now the variables are dead. |
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Clobber them just to be sure nobody does something stupid |
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like assuming they have some legal value. */ |
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asm("" : "=r" (p4), "=r" (p5)); |
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kernel_fpu_end(); |
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} |
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#undef LD |
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#undef XO1 |
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#undef XO2 |
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#undef XO3 |
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#undef XO4 |
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#undef ST |
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#undef BLOCK |
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static void |
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xor_p5_mmx_2(unsigned long bytes, unsigned long *p1, unsigned long *p2) |
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{ |
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unsigned long lines = bytes >> 6; |
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kernel_fpu_begin(); |
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asm volatile( |
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" .align 32 ;\n" |
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" 1: ;\n" |
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" movq (%1), %%mm0 ;\n" |
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" movq 8(%1), %%mm1 ;\n" |
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" pxor (%2), %%mm0 ;\n" |
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" movq 16(%1), %%mm2 ;\n" |
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" movq %%mm0, (%1) ;\n" |
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" pxor 8(%2), %%mm1 ;\n" |
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" movq 24(%1), %%mm3 ;\n" |
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" movq %%mm1, 8(%1) ;\n" |
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" pxor 16(%2), %%mm2 ;\n" |
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" movq 32(%1), %%mm4 ;\n" |
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" movq %%mm2, 16(%1) ;\n" |
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" pxor 24(%2), %%mm3 ;\n" |
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" movq 40(%1), %%mm5 ;\n" |
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" movq %%mm3, 24(%1) ;\n" |
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" pxor 32(%2), %%mm4 ;\n" |
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" movq 48(%1), %%mm6 ;\n" |
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" movq %%mm4, 32(%1) ;\n" |
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" pxor 40(%2), %%mm5 ;\n" |
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" movq 56(%1), %%mm7 ;\n" |
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" movq %%mm5, 40(%1) ;\n" |
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" pxor 48(%2), %%mm6 ;\n" |
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" pxor 56(%2), %%mm7 ;\n" |
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" movq %%mm6, 48(%1) ;\n" |
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" movq %%mm7, 56(%1) ;\n" |
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|
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" addl $64, %1 ;\n" |
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" addl $64, %2 ;\n" |
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" decl %0 ;\n" |
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" jnz 1b ;\n" |
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: "+r" (lines), |
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"+r" (p1), "+r" (p2) |
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: |
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: "memory"); |
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kernel_fpu_end(); |
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} |
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static void |
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xor_p5_mmx_3(unsigned long bytes, unsigned long *p1, unsigned long *p2, |
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unsigned long *p3) |
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{ |
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unsigned long lines = bytes >> 6; |
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kernel_fpu_begin(); |
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asm volatile( |
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" .align 32,0x90 ;\n" |
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" 1: ;\n" |
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" movq (%1), %%mm0 ;\n" |
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" movq 8(%1), %%mm1 ;\n" |
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" pxor (%2), %%mm0 ;\n" |
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" movq 16(%1), %%mm2 ;\n" |
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" pxor 8(%2), %%mm1 ;\n" |
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" pxor (%3), %%mm0 ;\n" |
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" pxor 16(%2), %%mm2 ;\n" |
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" movq %%mm0, (%1) ;\n" |
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" pxor 8(%3), %%mm1 ;\n" |
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" pxor 16(%3), %%mm2 ;\n" |
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" movq 24(%1), %%mm3 ;\n" |
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" movq %%mm1, 8(%1) ;\n" |
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" movq 32(%1), %%mm4 ;\n" |
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" movq 40(%1), %%mm5 ;\n" |
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" pxor 24(%2), %%mm3 ;\n" |
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" movq %%mm2, 16(%1) ;\n" |
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" pxor 32(%2), %%mm4 ;\n" |
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" pxor 24(%3), %%mm3 ;\n" |
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" pxor 40(%2), %%mm5 ;\n" |
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" movq %%mm3, 24(%1) ;\n" |
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" pxor 32(%3), %%mm4 ;\n" |
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" pxor 40(%3), %%mm5 ;\n" |
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" movq 48(%1), %%mm6 ;\n" |
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" movq %%mm4, 32(%1) ;\n" |
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" movq 56(%1), %%mm7 ;\n" |
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" pxor 48(%2), %%mm6 ;\n" |
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" movq %%mm5, 40(%1) ;\n" |
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" pxor 56(%2), %%mm7 ;\n" |
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" pxor 48(%3), %%mm6 ;\n" |
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" pxor 56(%3), %%mm7 ;\n" |
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" movq %%mm6, 48(%1) ;\n" |
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" movq %%mm7, 56(%1) ;\n" |
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|
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" addl $64, %1 ;\n" |
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" addl $64, %2 ;\n" |
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" addl $64, %3 ;\n" |
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" decl %0 ;\n" |
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" jnz 1b ;\n" |
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: "+r" (lines), |
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"+r" (p1), "+r" (p2), "+r" (p3) |
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: |
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: "memory" ); |
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kernel_fpu_end(); |
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} |
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static void |
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xor_p5_mmx_4(unsigned long bytes, unsigned long *p1, unsigned long *p2, |
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unsigned long *p3, unsigned long *p4) |
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{ |
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unsigned long lines = bytes >> 6; |
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kernel_fpu_begin(); |
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asm volatile( |
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" .align 32,0x90 ;\n" |
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" 1: ;\n" |
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" movq (%1), %%mm0 ;\n" |
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" movq 8(%1), %%mm1 ;\n" |
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" pxor (%2), %%mm0 ;\n" |
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" movq 16(%1), %%mm2 ;\n" |
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" pxor 8(%2), %%mm1 ;\n" |
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" pxor (%3), %%mm0 ;\n" |
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" pxor 16(%2), %%mm2 ;\n" |
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" pxor 8(%3), %%mm1 ;\n" |
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" pxor (%4), %%mm0 ;\n" |
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" movq 24(%1), %%mm3 ;\n" |
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" pxor 16(%3), %%mm2 ;\n" |
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" pxor 8(%4), %%mm1 ;\n" |
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" movq %%mm0, (%1) ;\n" |
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" movq 32(%1), %%mm4 ;\n" |
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" pxor 24(%2), %%mm3 ;\n" |
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" pxor 16(%4), %%mm2 ;\n" |
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" movq %%mm1, 8(%1) ;\n" |
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" movq 40(%1), %%mm5 ;\n" |
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" pxor 32(%2), %%mm4 ;\n" |
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" pxor 24(%3), %%mm3 ;\n" |
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" movq %%mm2, 16(%1) ;\n" |
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" pxor 40(%2), %%mm5 ;\n" |
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" pxor 32(%3), %%mm4 ;\n" |
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" pxor 24(%4), %%mm3 ;\n" |
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" movq %%mm3, 24(%1) ;\n" |
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" movq 56(%1), %%mm7 ;\n" |
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" movq 48(%1), %%mm6 ;\n" |
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" pxor 40(%3), %%mm5 ;\n" |
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" pxor 32(%4), %%mm4 ;\n" |
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" pxor 48(%2), %%mm6 ;\n" |
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" movq %%mm4, 32(%1) ;\n" |
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" pxor 56(%2), %%mm7 ;\n" |
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" pxor 40(%4), %%mm5 ;\n" |
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" pxor 48(%3), %%mm6 ;\n" |
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" pxor 56(%3), %%mm7 ;\n" |
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" movq %%mm5, 40(%1) ;\n" |
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" pxor 48(%4), %%mm6 ;\n" |
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" pxor 56(%4), %%mm7 ;\n" |
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" movq %%mm6, 48(%1) ;\n" |
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" movq %%mm7, 56(%1) ;\n" |
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|
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" addl $64, %1 ;\n" |
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" addl $64, %2 ;\n" |
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" addl $64, %3 ;\n" |
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" addl $64, %4 ;\n" |
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" decl %0 ;\n" |
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" jnz 1b ;\n" |
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: "+r" (lines), |
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"+r" (p1), "+r" (p2), "+r" (p3), "+r" (p4) |
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: |
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: "memory"); |
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kernel_fpu_end(); |
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} |
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static void |
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xor_p5_mmx_5(unsigned long bytes, unsigned long *p1, unsigned long *p2, |
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unsigned long *p3, unsigned long *p4, unsigned long *p5) |
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{ |
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unsigned long lines = bytes >> 6; |
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kernel_fpu_begin(); |
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|
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/* Make sure GCC forgets anything it knows about p4 or p5, |
|
such that it won't pass to the asm volatile below a |
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register that is shared with any other variable. That's |
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because we modify p4 and p5 there, but we can't mark them |
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as read/write, otherwise we'd overflow the 10-asm-operands |
|
limit of GCC < 3.1. */ |
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asm("" : "+r" (p4), "+r" (p5)); |
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|
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asm volatile( |
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" .align 32,0x90 ;\n" |
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" 1: ;\n" |
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" movq (%1), %%mm0 ;\n" |
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" movq 8(%1), %%mm1 ;\n" |
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" pxor (%2), %%mm0 ;\n" |
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" pxor 8(%2), %%mm1 ;\n" |
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" movq 16(%1), %%mm2 ;\n" |
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" pxor (%3), %%mm0 ;\n" |
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" pxor 8(%3), %%mm1 ;\n" |
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" pxor 16(%2), %%mm2 ;\n" |
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" pxor (%4), %%mm0 ;\n" |
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" pxor 8(%4), %%mm1 ;\n" |
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" pxor 16(%3), %%mm2 ;\n" |
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" movq 24(%1), %%mm3 ;\n" |
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" pxor (%5), %%mm0 ;\n" |
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" pxor 8(%5), %%mm1 ;\n" |
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" movq %%mm0, (%1) ;\n" |
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" pxor 16(%4), %%mm2 ;\n" |
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" pxor 24(%2), %%mm3 ;\n" |
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" movq %%mm1, 8(%1) ;\n" |
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" pxor 16(%5), %%mm2 ;\n" |
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" pxor 24(%3), %%mm3 ;\n" |
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" movq 32(%1), %%mm4 ;\n" |
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" movq %%mm2, 16(%1) ;\n" |
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" pxor 24(%4), %%mm3 ;\n" |
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" pxor 32(%2), %%mm4 ;\n" |
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" movq 40(%1), %%mm5 ;\n" |
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" pxor 24(%5), %%mm3 ;\n" |
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" pxor 32(%3), %%mm4 ;\n" |
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" pxor 40(%2), %%mm5 ;\n" |
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" movq %%mm3, 24(%1) ;\n" |
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" pxor 32(%4), %%mm4 ;\n" |
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" pxor 40(%3), %%mm5 ;\n" |
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" movq 48(%1), %%mm6 ;\n" |
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" movq 56(%1), %%mm7 ;\n" |
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" pxor 32(%5), %%mm4 ;\n" |
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" pxor 40(%4), %%mm5 ;\n" |
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" pxor 48(%2), %%mm6 ;\n" |
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" pxor 56(%2), %%mm7 ;\n" |
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" movq %%mm4, 32(%1) ;\n" |
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" pxor 48(%3), %%mm6 ;\n" |
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" pxor 56(%3), %%mm7 ;\n" |
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" pxor 40(%5), %%mm5 ;\n" |
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" pxor 48(%4), %%mm6 ;\n" |
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" pxor 56(%4), %%mm7 ;\n" |
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" movq %%mm5, 40(%1) ;\n" |
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" pxor 48(%5), %%mm6 ;\n" |
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" pxor 56(%5), %%mm7 ;\n" |
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" movq %%mm6, 48(%1) ;\n" |
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" movq %%mm7, 56(%1) ;\n" |
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|
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" addl $64, %1 ;\n" |
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" addl $64, %2 ;\n" |
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" addl $64, %3 ;\n" |
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" addl $64, %4 ;\n" |
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" addl $64, %5 ;\n" |
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" decl %0 ;\n" |
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" jnz 1b ;\n" |
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: "+r" (lines), |
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"+r" (p1), "+r" (p2), "+r" (p3) |
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: "r" (p4), "r" (p5) |
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: "memory"); |
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|
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/* p4 and p5 were modified, and now the variables are dead. |
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Clobber them just to be sure nobody does something stupid |
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like assuming they have some legal value. */ |
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asm("" : "=r" (p4), "=r" (p5)); |
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|
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kernel_fpu_end(); |
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} |
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|
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static struct xor_block_template xor_block_pII_mmx = { |
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.name = "pII_mmx", |
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.do_2 = xor_pII_mmx_2, |
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.do_3 = xor_pII_mmx_3, |
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.do_4 = xor_pII_mmx_4, |
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.do_5 = xor_pII_mmx_5, |
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}; |
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|
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static struct xor_block_template xor_block_p5_mmx = { |
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.name = "p5_mmx", |
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.do_2 = xor_p5_mmx_2, |
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.do_3 = xor_p5_mmx_3, |
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.do_4 = xor_p5_mmx_4, |
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.do_5 = xor_p5_mmx_5, |
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}; |
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|
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static struct xor_block_template xor_block_pIII_sse = { |
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.name = "pIII_sse", |
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.do_2 = xor_sse_2, |
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.do_3 = xor_sse_3, |
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.do_4 = xor_sse_4, |
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.do_5 = xor_sse_5, |
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}; |
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|
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/* Also try the AVX routines */ |
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#include <asm/xor_avx.h> |
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|
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/* Also try the generic routines. */ |
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#include <asm-generic/xor.h> |
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|
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/* We force the use of the SSE xor block because it can write around L2. |
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We may also be able to load into the L1 only depending on how the cpu |
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deals with a load to a line that is being prefetched. */ |
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#undef XOR_TRY_TEMPLATES |
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#define XOR_TRY_TEMPLATES \ |
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do { \ |
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AVX_XOR_SPEED; \ |
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if (boot_cpu_has(X86_FEATURE_XMM)) { \ |
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xor_speed(&xor_block_pIII_sse); \ |
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xor_speed(&xor_block_sse_pf64); \ |
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} else if (boot_cpu_has(X86_FEATURE_MMX)) { \ |
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xor_speed(&xor_block_pII_mmx); \ |
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xor_speed(&xor_block_p5_mmx); \ |
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} else { \ |
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xor_speed(&xor_block_8regs); \ |
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xor_speed(&xor_block_8regs_p); \ |
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xor_speed(&xor_block_32regs); \ |
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xor_speed(&xor_block_32regs_p); \ |
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} \ |
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} while (0) |
|
|
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#endif /* _ASM_X86_XOR_32_H */
|
|
|