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779 lines
23 KiB
779 lines
23 KiB
/* |
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file "COPYING" in the main directory of this archive |
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* for more details. |
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* |
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* SGI UV architectural definitions |
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* |
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* (C) Copyright 2020 Hewlett Packard Enterprise Development LP |
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* Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved. |
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*/ |
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|
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#ifndef _ASM_X86_UV_UV_HUB_H |
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#define _ASM_X86_UV_UV_HUB_H |
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#ifdef CONFIG_X86_64 |
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#include <linux/numa.h> |
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#include <linux/percpu.h> |
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#include <linux/timer.h> |
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#include <linux/io.h> |
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#include <linux/topology.h> |
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#include <asm/types.h> |
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#include <asm/percpu.h> |
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#include <asm/uv/uv.h> |
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#include <asm/uv/uv_mmrs.h> |
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#include <asm/uv/bios.h> |
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#include <asm/irq_vectors.h> |
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#include <asm/io_apic.h> |
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/* |
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* Addressing Terminology |
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* |
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* M - The low M bits of a physical address represent the offset |
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* into the blade local memory. RAM memory on a blade is physically |
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* contiguous (although various IO spaces may punch holes in |
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* it).. |
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* |
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* N - Number of bits in the node portion of a socket physical |
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* address. |
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* |
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* NASID - network ID of a router, Mbrick or Cbrick. Nasid values of |
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* routers always have low bit of 1, C/MBricks have low bit |
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* equal to 0. Most addressing macros that target UV hub chips |
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* right shift the NASID by 1 to exclude the always-zero bit. |
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* NASIDs contain up to 15 bits. |
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* |
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* GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead |
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* of nasids. |
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* |
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* PNODE - the low N bits of the GNODE. The PNODE is the most useful variant |
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* of the nasid for socket usage. |
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* |
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* GPA - (global physical address) a socket physical address converted |
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* so that it can be used by the GRU as a global address. Socket |
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* physical addresses 1) need additional NASID (node) bits added |
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* to the high end of the address, and 2) unaliased if the |
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* partition does not have a physical address 0. In addition, on |
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* UV2 rev 1, GPAs need the gnode left shifted to bits 39 or 40. |
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* |
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* |
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* NumaLink Global Physical Address Format: |
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* +--------------------------------+---------------------+ |
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* |00..000| GNODE | NodeOffset | |
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* +--------------------------------+---------------------+ |
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* |<-------53 - M bits --->|<--------M bits -----> |
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* |
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* M - number of node offset bits (35 .. 40) |
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* |
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* |
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* Memory/UV-HUB Processor Socket Address Format: |
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* +----------------+---------------+---------------------+ |
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* |00..000000000000| PNODE | NodeOffset | |
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* +----------------+---------------+---------------------+ |
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* <--- N bits --->|<--------M bits -----> |
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* |
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* M - number of node offset bits (35 .. 40) |
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* N - number of PNODE bits (0 .. 10) |
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* |
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* Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64). |
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* The actual values are configuration dependent and are set at |
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* boot time. M & N values are set by the hardware/BIOS at boot. |
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* |
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* |
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* APICID format |
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* NOTE!!!!!! This is the current format of the APICID. However, code |
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* should assume that this will change in the future. Use functions |
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* in this file for all APICID bit manipulations and conversion. |
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* |
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* 1111110000000000 |
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* 5432109876543210 |
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* pppppppppplc0cch Nehalem-EX (12 bits in hdw reg) |
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* ppppppppplcc0cch Westmere-EX (12 bits in hdw reg) |
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* pppppppppppcccch SandyBridge (15 bits in hdw reg) |
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* sssssssssss |
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* |
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* p = pnode bits |
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* l = socket number on board |
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* c = core |
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* h = hyperthread |
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* s = bits that are in the SOCKET_ID CSR |
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* |
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* Note: Processor may support fewer bits in the APICID register. The ACPI |
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* tables hold all 16 bits. Software needs to be aware of this. |
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* |
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* Unless otherwise specified, all references to APICID refer to |
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* the FULL value contained in ACPI tables, not the subset in the |
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* processor APICID register. |
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*/ |
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/* |
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* Maximum number of bricks in all partitions and in all coherency domains. |
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* This is the total number of bricks accessible in the numalink fabric. It |
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* includes all C & M bricks. Routers are NOT included. |
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* |
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* This value is also the value of the maximum number of non-router NASIDs |
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* in the numalink fabric. |
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* |
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* NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused. |
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*/ |
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#define UV_MAX_NUMALINK_BLADES 16384 |
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/* |
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* Maximum number of C/Mbricks within a software SSI (hardware may support |
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* more). |
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*/ |
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#define UV_MAX_SSI_BLADES 256 |
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/* |
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* The largest possible NASID of a C or M brick (+ 2) |
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*/ |
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#define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_BLADES * 2) |
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/* GAM (globally addressed memory) range table */ |
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struct uv_gam_range_s { |
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u32 limit; /* PA bits 56:26 (GAM_RANGE_SHFT) */ |
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u16 nasid; /* node's global physical address */ |
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s8 base; /* entry index of node's base addr */ |
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u8 reserved; |
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}; |
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/* |
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* The following defines attributes of the HUB chip. These attributes are |
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* frequently referenced and are kept in a common per hub struct. |
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* After setup, the struct is read only, so it should be readily |
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* available in the L3 cache on the cpu socket for the node. |
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*/ |
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struct uv_hub_info_s { |
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unsigned int hub_type; |
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unsigned char hub_revision; |
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unsigned long global_mmr_base; |
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unsigned long global_mmr_shift; |
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unsigned long gpa_mask; |
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unsigned short *socket_to_node; |
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unsigned short *socket_to_pnode; |
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unsigned short *pnode_to_socket; |
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struct uv_gam_range_s *gr_table; |
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unsigned short min_socket; |
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unsigned short min_pnode; |
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unsigned char m_val; |
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unsigned char n_val; |
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unsigned char gr_table_len; |
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unsigned char apic_pnode_shift; |
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unsigned char gpa_shift; |
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unsigned char nasid_shift; |
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unsigned char m_shift; |
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unsigned char n_lshift; |
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unsigned int gnode_extra; |
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unsigned long gnode_upper; |
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unsigned long lowmem_remap_top; |
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unsigned long lowmem_remap_base; |
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unsigned long global_gru_base; |
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unsigned long global_gru_shift; |
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unsigned short pnode; |
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unsigned short pnode_mask; |
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unsigned short coherency_domain_number; |
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unsigned short numa_blade_id; |
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unsigned short nr_possible_cpus; |
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unsigned short nr_online_cpus; |
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short memory_nid; |
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}; |
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/* CPU specific info with a pointer to the hub common info struct */ |
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struct uv_cpu_info_s { |
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void *p_uv_hub_info; |
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unsigned char blade_cpu_id; |
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void *reserved; |
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}; |
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DECLARE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info); |
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#define uv_cpu_info this_cpu_ptr(&__uv_cpu_info) |
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#define uv_cpu_info_per(cpu) (&per_cpu(__uv_cpu_info, cpu)) |
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/* Node specific hub common info struct */ |
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extern void **__uv_hub_info_list; |
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static inline struct uv_hub_info_s *uv_hub_info_list(int node) |
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{ |
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return (struct uv_hub_info_s *)__uv_hub_info_list[node]; |
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} |
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static inline struct uv_hub_info_s *_uv_hub_info(void) |
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{ |
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return (struct uv_hub_info_s *)uv_cpu_info->p_uv_hub_info; |
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} |
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#define uv_hub_info _uv_hub_info() |
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static inline struct uv_hub_info_s *uv_cpu_hub_info(int cpu) |
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{ |
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return (struct uv_hub_info_s *)uv_cpu_info_per(cpu)->p_uv_hub_info; |
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} |
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static inline int uv_hub_type(void) |
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{ |
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return uv_hub_info->hub_type; |
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} |
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static inline __init void uv_hub_type_set(int uvmask) |
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{ |
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uv_hub_info->hub_type = uvmask; |
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} |
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/* |
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* HUB revision ranges for each UV HUB architecture. |
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* This is a software convention - NOT the hardware revision numbers in |
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* the hub chip. |
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*/ |
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#define UV2_HUB_REVISION_BASE 3 |
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#define UV3_HUB_REVISION_BASE 5 |
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#define UV4_HUB_REVISION_BASE 7 |
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#define UV4A_HUB_REVISION_BASE 8 /* UV4 (fixed) rev 2 */ |
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#define UV5_HUB_REVISION_BASE 9 |
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static inline int is_uv(int uvmask) { return uv_hub_type() & uvmask; } |
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static inline int is_uv1_hub(void) { return 0; } |
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static inline int is_uv2_hub(void) { return is_uv(UV2); } |
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static inline int is_uv3_hub(void) { return is_uv(UV3); } |
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static inline int is_uv4a_hub(void) { return is_uv(UV4A); } |
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static inline int is_uv4_hub(void) { return is_uv(UV4); } |
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static inline int is_uv5_hub(void) { return is_uv(UV5); } |
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/* |
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* UV4A is a revision of UV4. So on UV4A, both is_uv4_hub() and |
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* is_uv4a_hub() return true, While on UV4, only is_uv4_hub() |
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* returns true. So to get true results, first test if is UV4A, |
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* then test if is UV4. |
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*/ |
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/* UVX class: UV2,3,4 */ |
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static inline int is_uvx_hub(void) { return is_uv(UVX); } |
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/* UVY class: UV5,..? */ |
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static inline int is_uvy_hub(void) { return is_uv(UVY); } |
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/* Any UV Hubbed System */ |
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static inline int is_uv_hub(void) { return is_uv(UV_ANY); } |
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union uvh_apicid { |
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unsigned long v; |
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struct uvh_apicid_s { |
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unsigned long local_apic_mask : 24; |
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unsigned long local_apic_shift : 5; |
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unsigned long unused1 : 3; |
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unsigned long pnode_mask : 24; |
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unsigned long pnode_shift : 5; |
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unsigned long unused2 : 3; |
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} s; |
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}; |
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/* |
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* Local & Global MMR space macros. |
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* Note: macros are intended to be used ONLY by inline functions |
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* in this file - not by other kernel code. |
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* n - NASID (full 15-bit global nasid) |
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* g - GNODE (full 15-bit global nasid, right shifted 1) |
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* p - PNODE (local part of nsids, right shifted 1) |
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*/ |
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#define UV_NASID_TO_PNODE(n) \ |
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(((n) >> uv_hub_info->nasid_shift) & uv_hub_info->pnode_mask) |
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#define UV_PNODE_TO_GNODE(p) ((p) |uv_hub_info->gnode_extra) |
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#define UV_PNODE_TO_NASID(p) \ |
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(UV_PNODE_TO_GNODE(p) << uv_hub_info->nasid_shift) |
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#define UV2_LOCAL_MMR_BASE 0xfa000000UL |
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#define UV2_GLOBAL_MMR32_BASE 0xfc000000UL |
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#define UV2_LOCAL_MMR_SIZE (32UL * 1024 * 1024) |
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#define UV2_GLOBAL_MMR32_SIZE (32UL * 1024 * 1024) |
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#define UV3_LOCAL_MMR_BASE 0xfa000000UL |
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#define UV3_GLOBAL_MMR32_BASE 0xfc000000UL |
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#define UV3_LOCAL_MMR_SIZE (32UL * 1024 * 1024) |
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#define UV3_GLOBAL_MMR32_SIZE (32UL * 1024 * 1024) |
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#define UV4_LOCAL_MMR_BASE 0xfa000000UL |
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#define UV4_GLOBAL_MMR32_BASE 0 |
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#define UV4_LOCAL_MMR_SIZE (32UL * 1024 * 1024) |
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#define UV4_GLOBAL_MMR32_SIZE 0 |
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#define UV5_LOCAL_MMR_BASE 0xfa000000UL |
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#define UV5_GLOBAL_MMR32_BASE 0 |
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#define UV5_LOCAL_MMR_SIZE (32UL * 1024 * 1024) |
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#define UV5_GLOBAL_MMR32_SIZE 0 |
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#define UV_LOCAL_MMR_BASE ( \ |
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is_uv(UV2) ? UV2_LOCAL_MMR_BASE : \ |
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is_uv(UV3) ? UV3_LOCAL_MMR_BASE : \ |
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is_uv(UV4) ? UV4_LOCAL_MMR_BASE : \ |
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is_uv(UV5) ? UV5_LOCAL_MMR_BASE : \ |
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0) |
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#define UV_GLOBAL_MMR32_BASE ( \ |
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is_uv(UV2) ? UV2_GLOBAL_MMR32_BASE : \ |
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is_uv(UV3) ? UV3_GLOBAL_MMR32_BASE : \ |
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is_uv(UV4) ? UV4_GLOBAL_MMR32_BASE : \ |
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is_uv(UV5) ? UV5_GLOBAL_MMR32_BASE : \ |
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0) |
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#define UV_LOCAL_MMR_SIZE ( \ |
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is_uv(UV2) ? UV2_LOCAL_MMR_SIZE : \ |
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is_uv(UV3) ? UV3_LOCAL_MMR_SIZE : \ |
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is_uv(UV4) ? UV4_LOCAL_MMR_SIZE : \ |
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is_uv(UV5) ? UV5_LOCAL_MMR_SIZE : \ |
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0) |
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#define UV_GLOBAL_MMR32_SIZE ( \ |
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is_uv(UV2) ? UV2_GLOBAL_MMR32_SIZE : \ |
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is_uv(UV3) ? UV3_GLOBAL_MMR32_SIZE : \ |
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is_uv(UV4) ? UV4_GLOBAL_MMR32_SIZE : \ |
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is_uv(UV5) ? UV5_GLOBAL_MMR32_SIZE : \ |
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0) |
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#define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base) |
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#define UV_GLOBAL_GRU_MMR_BASE 0x4000000 |
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#define UV_GLOBAL_MMR32_PNODE_SHIFT 15 |
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#define _UV_GLOBAL_MMR64_PNODE_SHIFT 26 |
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#define UV_GLOBAL_MMR64_PNODE_SHIFT (uv_hub_info->global_mmr_shift) |
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#define UV_GLOBAL_MMR32_PNODE_BITS(p) ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT)) |
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#define UV_GLOBAL_MMR64_PNODE_BITS(p) \ |
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(((unsigned long)(p)) << UV_GLOBAL_MMR64_PNODE_SHIFT) |
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#define UVH_APICID 0x002D0E00L |
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#define UV_APIC_PNODE_SHIFT 6 |
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/* Local Bus from cpu's perspective */ |
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#define LOCAL_BUS_BASE 0x1c00000 |
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#define LOCAL_BUS_SIZE (4 * 1024 * 1024) |
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/* |
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* System Controller Interface Reg |
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* |
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* Note there are NO leds on a UV system. This register is only |
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* used by the system controller to monitor system-wide operation. |
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* There are 64 regs per node. With Nahelem cpus (2 cores per node, |
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* 8 cpus per core, 2 threads per cpu) there are 32 cpu threads on |
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* a node. |
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* |
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* The window is located at top of ACPI MMR space |
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*/ |
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#define SCIR_WINDOW_COUNT 64 |
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#define SCIR_LOCAL_MMR_BASE (LOCAL_BUS_BASE + \ |
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LOCAL_BUS_SIZE - \ |
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SCIR_WINDOW_COUNT) |
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#define SCIR_CPU_HEARTBEAT 0x01 /* timer interrupt */ |
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#define SCIR_CPU_ACTIVITY 0x02 /* not idle */ |
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#define SCIR_CPU_HB_INTERVAL (HZ) /* once per second */ |
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/* Loop through all installed blades */ |
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#define for_each_possible_blade(bid) \ |
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for ((bid) = 0; (bid) < uv_num_possible_blades(); (bid)++) |
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/* |
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* Macros for converting between kernel virtual addresses, socket local physical |
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* addresses, and UV global physical addresses. |
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* Note: use the standard __pa() & __va() macros for converting |
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* between socket virtual and socket physical addresses. |
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*/ |
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/* global bits offset - number of local address bits in gpa for this UV arch */ |
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static inline unsigned int uv_gpa_shift(void) |
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{ |
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return uv_hub_info->gpa_shift; |
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} |
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#define _uv_gpa_shift |
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/* Find node that has the address range that contains global address */ |
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static inline struct uv_gam_range_s *uv_gam_range(unsigned long pa) |
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{ |
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struct uv_gam_range_s *gr = uv_hub_info->gr_table; |
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unsigned long pal = (pa & uv_hub_info->gpa_mask) >> UV_GAM_RANGE_SHFT; |
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int i, num = uv_hub_info->gr_table_len; |
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if (gr) { |
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for (i = 0; i < num; i++, gr++) { |
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if (pal < gr->limit) |
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return gr; |
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} |
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} |
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pr_crit("UV: GAM Range for 0x%lx not found at %p!\n", pa, gr); |
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BUG(); |
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} |
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/* Return base address of node that contains global address */ |
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static inline unsigned long uv_gam_range_base(unsigned long pa) |
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{ |
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struct uv_gam_range_s *gr = uv_gam_range(pa); |
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int base = gr->base; |
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if (base < 0) |
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return 0UL; |
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return uv_hub_info->gr_table[base].limit; |
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} |
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/* socket phys RAM --> UV global NASID (UV4+) */ |
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static inline unsigned long uv_soc_phys_ram_to_nasid(unsigned long paddr) |
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{ |
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return uv_gam_range(paddr)->nasid; |
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} |
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#define _uv_soc_phys_ram_to_nasid |
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|
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/* socket virtual --> UV global NASID (UV4+) */ |
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static inline unsigned long uv_gpa_nasid(void *v) |
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{ |
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return uv_soc_phys_ram_to_nasid(__pa(v)); |
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} |
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/* socket phys RAM --> UV global physical address */ |
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static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr) |
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{ |
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unsigned int m_val = uv_hub_info->m_val; |
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if (paddr < uv_hub_info->lowmem_remap_top) |
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paddr |= uv_hub_info->lowmem_remap_base; |
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if (m_val) { |
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paddr |= uv_hub_info->gnode_upper; |
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paddr = ((paddr << uv_hub_info->m_shift) |
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>> uv_hub_info->m_shift) | |
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((paddr >> uv_hub_info->m_val) |
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<< uv_hub_info->n_lshift); |
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} else { |
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paddr |= uv_soc_phys_ram_to_nasid(paddr) |
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<< uv_hub_info->gpa_shift; |
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} |
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return paddr; |
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} |
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|
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/* socket virtual --> UV global physical address */ |
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static inline unsigned long uv_gpa(void *v) |
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{ |
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return uv_soc_phys_ram_to_gpa(__pa(v)); |
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} |
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|
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/* Top two bits indicate the requested address is in MMR space. */ |
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static inline int |
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uv_gpa_in_mmr_space(unsigned long gpa) |
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{ |
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return (gpa >> 62) == 0x3UL; |
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} |
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|
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/* UV global physical address --> socket phys RAM */ |
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static inline unsigned long uv_gpa_to_soc_phys_ram(unsigned long gpa) |
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{ |
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unsigned long paddr; |
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unsigned long remap_base = uv_hub_info->lowmem_remap_base; |
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unsigned long remap_top = uv_hub_info->lowmem_remap_top; |
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unsigned int m_val = uv_hub_info->m_val; |
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|
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if (m_val) |
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gpa = ((gpa << uv_hub_info->m_shift) >> uv_hub_info->m_shift) | |
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((gpa >> uv_hub_info->n_lshift) << uv_hub_info->m_val); |
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|
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paddr = gpa & uv_hub_info->gpa_mask; |
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if (paddr >= remap_base && paddr < remap_base + remap_top) |
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paddr -= remap_base; |
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return paddr; |
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} |
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|
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/* gpa -> gnode */ |
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static inline unsigned long uv_gpa_to_gnode(unsigned long gpa) |
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{ |
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unsigned int n_lshift = uv_hub_info->n_lshift; |
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|
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if (n_lshift) |
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return gpa >> n_lshift; |
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|
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return uv_gam_range(gpa)->nasid >> 1; |
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} |
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|
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/* gpa -> pnode */ |
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static inline int uv_gpa_to_pnode(unsigned long gpa) |
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{ |
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return uv_gpa_to_gnode(gpa) & uv_hub_info->pnode_mask; |
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} |
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|
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/* gpa -> node offset */ |
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static inline unsigned long uv_gpa_to_offset(unsigned long gpa) |
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{ |
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unsigned int m_shift = uv_hub_info->m_shift; |
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|
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if (m_shift) |
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return (gpa << m_shift) >> m_shift; |
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|
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return (gpa & uv_hub_info->gpa_mask) - uv_gam_range_base(gpa); |
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} |
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|
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/* Convert socket to node */ |
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static inline int _uv_socket_to_node(int socket, unsigned short *s2nid) |
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{ |
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return s2nid ? s2nid[socket - uv_hub_info->min_socket] : socket; |
|
} |
|
|
|
static inline int uv_socket_to_node(int socket) |
|
{ |
|
return _uv_socket_to_node(socket, uv_hub_info->socket_to_node); |
|
} |
|
|
|
/* pnode, offset --> socket virtual */ |
|
static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset) |
|
{ |
|
unsigned int m_val = uv_hub_info->m_val; |
|
unsigned long base; |
|
unsigned short sockid, node, *p2s; |
|
|
|
if (m_val) |
|
return __va(((unsigned long)pnode << m_val) | offset); |
|
|
|
p2s = uv_hub_info->pnode_to_socket; |
|
sockid = p2s ? p2s[pnode - uv_hub_info->min_pnode] : pnode; |
|
node = uv_socket_to_node(sockid); |
|
|
|
/* limit address of previous socket is our base, except node 0 is 0 */ |
|
if (!node) |
|
return __va((unsigned long)offset); |
|
|
|
base = (unsigned long)(uv_hub_info->gr_table[node - 1].limit); |
|
return __va(base << UV_GAM_RANGE_SHFT | offset); |
|
} |
|
|
|
/* Extract/Convert a PNODE from an APICID (full apicid, not processor subset) */ |
|
static inline int uv_apicid_to_pnode(int apicid) |
|
{ |
|
int pnode = apicid >> uv_hub_info->apic_pnode_shift; |
|
unsigned short *s2pn = uv_hub_info->socket_to_pnode; |
|
|
|
return s2pn ? s2pn[pnode - uv_hub_info->min_socket] : pnode; |
|
} |
|
|
|
/* |
|
* Access global MMRs using the low memory MMR32 space. This region supports |
|
* faster MMR access but not all MMRs are accessible in this space. |
|
*/ |
|
static inline unsigned long *uv_global_mmr32_address(int pnode, unsigned long offset) |
|
{ |
|
return __va(UV_GLOBAL_MMR32_BASE | |
|
UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset); |
|
} |
|
|
|
static inline void uv_write_global_mmr32(int pnode, unsigned long offset, unsigned long val) |
|
{ |
|
writeq(val, uv_global_mmr32_address(pnode, offset)); |
|
} |
|
|
|
static inline unsigned long uv_read_global_mmr32(int pnode, unsigned long offset) |
|
{ |
|
return readq(uv_global_mmr32_address(pnode, offset)); |
|
} |
|
|
|
/* |
|
* Access Global MMR space using the MMR space located at the top of physical |
|
* memory. |
|
*/ |
|
static inline volatile void __iomem *uv_global_mmr64_address(int pnode, unsigned long offset) |
|
{ |
|
return __va(UV_GLOBAL_MMR64_BASE | |
|
UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset); |
|
} |
|
|
|
static inline void uv_write_global_mmr64(int pnode, unsigned long offset, unsigned long val) |
|
{ |
|
writeq(val, uv_global_mmr64_address(pnode, offset)); |
|
} |
|
|
|
static inline unsigned long uv_read_global_mmr64(int pnode, unsigned long offset) |
|
{ |
|
return readq(uv_global_mmr64_address(pnode, offset)); |
|
} |
|
|
|
static inline void uv_write_global_mmr8(int pnode, unsigned long offset, unsigned char val) |
|
{ |
|
writeb(val, uv_global_mmr64_address(pnode, offset)); |
|
} |
|
|
|
static inline unsigned char uv_read_global_mmr8(int pnode, unsigned long offset) |
|
{ |
|
return readb(uv_global_mmr64_address(pnode, offset)); |
|
} |
|
|
|
/* |
|
* Access hub local MMRs. Faster than using global space but only local MMRs |
|
* are accessible. |
|
*/ |
|
static inline unsigned long *uv_local_mmr_address(unsigned long offset) |
|
{ |
|
return __va(UV_LOCAL_MMR_BASE | offset); |
|
} |
|
|
|
static inline unsigned long uv_read_local_mmr(unsigned long offset) |
|
{ |
|
return readq(uv_local_mmr_address(offset)); |
|
} |
|
|
|
static inline void uv_write_local_mmr(unsigned long offset, unsigned long val) |
|
{ |
|
writeq(val, uv_local_mmr_address(offset)); |
|
} |
|
|
|
static inline unsigned char uv_read_local_mmr8(unsigned long offset) |
|
{ |
|
return readb(uv_local_mmr_address(offset)); |
|
} |
|
|
|
static inline void uv_write_local_mmr8(unsigned long offset, unsigned char val) |
|
{ |
|
writeb(val, uv_local_mmr_address(offset)); |
|
} |
|
|
|
/* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */ |
|
static inline int uv_blade_processor_id(void) |
|
{ |
|
return uv_cpu_info->blade_cpu_id; |
|
} |
|
|
|
/* Blade-local cpu number of cpu N. Numbered 0 .. <# cpus on the blade> */ |
|
static inline int uv_cpu_blade_processor_id(int cpu) |
|
{ |
|
return uv_cpu_info_per(cpu)->blade_cpu_id; |
|
} |
|
|
|
/* Blade number to Node number (UV2..UV4 is 1:1) */ |
|
static inline int uv_blade_to_node(int blade) |
|
{ |
|
return blade; |
|
} |
|
|
|
/* Blade number of current cpu. Numnbered 0 .. <#blades -1> */ |
|
static inline int uv_numa_blade_id(void) |
|
{ |
|
return uv_hub_info->numa_blade_id; |
|
} |
|
|
|
/* |
|
* Convert linux node number to the UV blade number. |
|
* .. Currently for UV2 thru UV4 the node and the blade are identical. |
|
* .. If this changes then you MUST check references to this function! |
|
*/ |
|
static inline int uv_node_to_blade_id(int nid) |
|
{ |
|
return nid; |
|
} |
|
|
|
/* Convert a CPU number to the UV blade number */ |
|
static inline int uv_cpu_to_blade_id(int cpu) |
|
{ |
|
return uv_node_to_blade_id(cpu_to_node(cpu)); |
|
} |
|
|
|
/* Convert a blade id to the PNODE of the blade */ |
|
static inline int uv_blade_to_pnode(int bid) |
|
{ |
|
return uv_hub_info_list(uv_blade_to_node(bid))->pnode; |
|
} |
|
|
|
/* Nid of memory node on blade. -1 if no blade-local memory */ |
|
static inline int uv_blade_to_memory_nid(int bid) |
|
{ |
|
return uv_hub_info_list(uv_blade_to_node(bid))->memory_nid; |
|
} |
|
|
|
/* Determine the number of possible cpus on a blade */ |
|
static inline int uv_blade_nr_possible_cpus(int bid) |
|
{ |
|
return uv_hub_info_list(uv_blade_to_node(bid))->nr_possible_cpus; |
|
} |
|
|
|
/* Determine the number of online cpus on a blade */ |
|
static inline int uv_blade_nr_online_cpus(int bid) |
|
{ |
|
return uv_hub_info_list(uv_blade_to_node(bid))->nr_online_cpus; |
|
} |
|
|
|
/* Convert a cpu id to the PNODE of the blade containing the cpu */ |
|
static inline int uv_cpu_to_pnode(int cpu) |
|
{ |
|
return uv_cpu_hub_info(cpu)->pnode; |
|
} |
|
|
|
/* Convert a linux node number to the PNODE of the blade */ |
|
static inline int uv_node_to_pnode(int nid) |
|
{ |
|
return uv_hub_info_list(nid)->pnode; |
|
} |
|
|
|
/* Maximum possible number of blades */ |
|
extern short uv_possible_blades; |
|
static inline int uv_num_possible_blades(void) |
|
{ |
|
return uv_possible_blades; |
|
} |
|
|
|
/* Per Hub NMI support */ |
|
extern void uv_nmi_setup(void); |
|
extern void uv_nmi_setup_hubless(void); |
|
|
|
/* BIOS/Kernel flags exchange MMR */ |
|
#define UVH_BIOS_KERNEL_MMR UVH_SCRATCH5 |
|
#define UVH_BIOS_KERNEL_MMR_ALIAS UVH_SCRATCH5_ALIAS |
|
#define UVH_BIOS_KERNEL_MMR_ALIAS_2 UVH_SCRATCH5_ALIAS_2 |
|
|
|
/* TSC sync valid, set by BIOS */ |
|
#define UVH_TSC_SYNC_MMR UVH_BIOS_KERNEL_MMR |
|
#define UVH_TSC_SYNC_SHIFT 10 |
|
#define UVH_TSC_SYNC_SHIFT_UV2K 16 /* UV2/3k have different bits */ |
|
#define UVH_TSC_SYNC_MASK 3 /* 0011 */ |
|
#define UVH_TSC_SYNC_VALID 3 /* 0011 */ |
|
#define UVH_TSC_SYNC_UNKNOWN 0 /* 0000 */ |
|
|
|
/* BMC sets a bit this MMR non-zero before sending an NMI */ |
|
#define UVH_NMI_MMR UVH_BIOS_KERNEL_MMR |
|
#define UVH_NMI_MMR_CLEAR UVH_BIOS_KERNEL_MMR_ALIAS |
|
#define UVH_NMI_MMR_SHIFT 63 |
|
#define UVH_NMI_MMR_TYPE "SCRATCH5" |
|
|
|
struct uv_hub_nmi_s { |
|
raw_spinlock_t nmi_lock; |
|
atomic_t in_nmi; /* flag this node in UV NMI IRQ */ |
|
atomic_t cpu_owner; /* last locker of this struct */ |
|
atomic_t read_mmr_count; /* count of MMR reads */ |
|
atomic_t nmi_count; /* count of true UV NMIs */ |
|
unsigned long nmi_value; /* last value read from NMI MMR */ |
|
bool hub_present; /* false means UV hubless system */ |
|
bool pch_owner; /* indicates this hub owns PCH */ |
|
}; |
|
|
|
struct uv_cpu_nmi_s { |
|
struct uv_hub_nmi_s *hub; |
|
int state; |
|
int pinging; |
|
int queries; |
|
int pings; |
|
}; |
|
|
|
DECLARE_PER_CPU(struct uv_cpu_nmi_s, uv_cpu_nmi); |
|
|
|
#define uv_hub_nmi this_cpu_read(uv_cpu_nmi.hub) |
|
#define uv_cpu_nmi_per(cpu) (per_cpu(uv_cpu_nmi, cpu)) |
|
#define uv_hub_nmi_per(cpu) (uv_cpu_nmi_per(cpu).hub) |
|
|
|
/* uv_cpu_nmi_states */ |
|
#define UV_NMI_STATE_OUT 0 |
|
#define UV_NMI_STATE_IN 1 |
|
#define UV_NMI_STATE_DUMP 2 |
|
#define UV_NMI_STATE_DUMP_DONE 3 |
|
|
|
/* |
|
* Get the minimum revision number of the hub chips within the partition. |
|
* (See UVx_HUB_REVISION_BASE above for specific values.) |
|
*/ |
|
static inline int uv_get_min_hub_revision_id(void) |
|
{ |
|
return uv_hub_info->hub_revision; |
|
} |
|
|
|
#endif /* CONFIG_X86_64 */ |
|
#endif /* _ASM_X86_UV_UV_HUB_H */
|
|
|