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522 lines
15 KiB
522 lines
15 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#ifndef _ASM_X86_PERF_EVENT_H |
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#define _ASM_X86_PERF_EVENT_H |
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/* |
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* Performance event hw details: |
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*/ |
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#define INTEL_PMC_MAX_GENERIC 32 |
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#define INTEL_PMC_MAX_FIXED 4 |
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#define INTEL_PMC_IDX_FIXED 32 |
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#define X86_PMC_IDX_MAX 64 |
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#define MSR_ARCH_PERFMON_PERFCTR0 0xc1 |
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#define MSR_ARCH_PERFMON_PERFCTR1 0xc2 |
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#define MSR_ARCH_PERFMON_EVENTSEL0 0x186 |
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#define MSR_ARCH_PERFMON_EVENTSEL1 0x187 |
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#define ARCH_PERFMON_EVENTSEL_EVENT 0x000000FFULL |
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#define ARCH_PERFMON_EVENTSEL_UMASK 0x0000FF00ULL |
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#define ARCH_PERFMON_EVENTSEL_USR (1ULL << 16) |
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#define ARCH_PERFMON_EVENTSEL_OS (1ULL << 17) |
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#define ARCH_PERFMON_EVENTSEL_EDGE (1ULL << 18) |
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#define ARCH_PERFMON_EVENTSEL_PIN_CONTROL (1ULL << 19) |
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#define ARCH_PERFMON_EVENTSEL_INT (1ULL << 20) |
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#define ARCH_PERFMON_EVENTSEL_ANY (1ULL << 21) |
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#define ARCH_PERFMON_EVENTSEL_ENABLE (1ULL << 22) |
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#define ARCH_PERFMON_EVENTSEL_INV (1ULL << 23) |
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#define ARCH_PERFMON_EVENTSEL_CMASK 0xFF000000ULL |
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#define HSW_IN_TX (1ULL << 32) |
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#define HSW_IN_TX_CHECKPOINTED (1ULL << 33) |
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#define ICL_EVENTSEL_ADAPTIVE (1ULL << 34) |
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#define ICL_FIXED_0_ADAPTIVE (1ULL << 32) |
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#define AMD64_EVENTSEL_INT_CORE_ENABLE (1ULL << 36) |
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#define AMD64_EVENTSEL_GUESTONLY (1ULL << 40) |
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#define AMD64_EVENTSEL_HOSTONLY (1ULL << 41) |
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#define AMD64_EVENTSEL_INT_CORE_SEL_SHIFT 37 |
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#define AMD64_EVENTSEL_INT_CORE_SEL_MASK \ |
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(0xFULL << AMD64_EVENTSEL_INT_CORE_SEL_SHIFT) |
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#define AMD64_EVENTSEL_EVENT \ |
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(ARCH_PERFMON_EVENTSEL_EVENT | (0x0FULL << 32)) |
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#define INTEL_ARCH_EVENT_MASK \ |
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(ARCH_PERFMON_EVENTSEL_UMASK | ARCH_PERFMON_EVENTSEL_EVENT) |
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#define AMD64_L3_SLICE_SHIFT 48 |
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#define AMD64_L3_SLICE_MASK \ |
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(0xFULL << AMD64_L3_SLICE_SHIFT) |
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#define AMD64_L3_SLICEID_MASK \ |
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(0x7ULL << AMD64_L3_SLICE_SHIFT) |
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#define AMD64_L3_THREAD_SHIFT 56 |
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#define AMD64_L3_THREAD_MASK \ |
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(0xFFULL << AMD64_L3_THREAD_SHIFT) |
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#define AMD64_L3_F19H_THREAD_MASK \ |
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(0x3ULL << AMD64_L3_THREAD_SHIFT) |
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#define AMD64_L3_EN_ALL_CORES BIT_ULL(47) |
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#define AMD64_L3_EN_ALL_SLICES BIT_ULL(46) |
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#define AMD64_L3_COREID_SHIFT 42 |
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#define AMD64_L3_COREID_MASK \ |
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(0x7ULL << AMD64_L3_COREID_SHIFT) |
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#define X86_RAW_EVENT_MASK \ |
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(ARCH_PERFMON_EVENTSEL_EVENT | \ |
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ARCH_PERFMON_EVENTSEL_UMASK | \ |
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ARCH_PERFMON_EVENTSEL_EDGE | \ |
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ARCH_PERFMON_EVENTSEL_INV | \ |
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ARCH_PERFMON_EVENTSEL_CMASK) |
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#define X86_ALL_EVENT_FLAGS \ |
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(ARCH_PERFMON_EVENTSEL_EDGE | \ |
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ARCH_PERFMON_EVENTSEL_INV | \ |
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ARCH_PERFMON_EVENTSEL_CMASK | \ |
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ARCH_PERFMON_EVENTSEL_ANY | \ |
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ARCH_PERFMON_EVENTSEL_PIN_CONTROL | \ |
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HSW_IN_TX | \ |
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HSW_IN_TX_CHECKPOINTED) |
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#define AMD64_RAW_EVENT_MASK \ |
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(X86_RAW_EVENT_MASK | \ |
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AMD64_EVENTSEL_EVENT) |
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#define AMD64_RAW_EVENT_MASK_NB \ |
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(AMD64_EVENTSEL_EVENT | \ |
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ARCH_PERFMON_EVENTSEL_UMASK) |
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#define AMD64_NUM_COUNTERS 4 |
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#define AMD64_NUM_COUNTERS_CORE 6 |
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#define AMD64_NUM_COUNTERS_NB 4 |
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#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL 0x3c |
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#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK (0x00 << 8) |
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#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX 0 |
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#define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \ |
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(1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX)) |
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#define ARCH_PERFMON_BRANCH_MISSES_RETIRED 6 |
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#define ARCH_PERFMON_EVENTS_COUNT 7 |
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#define PEBS_DATACFG_MEMINFO BIT_ULL(0) |
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#define PEBS_DATACFG_GP BIT_ULL(1) |
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#define PEBS_DATACFG_XMMS BIT_ULL(2) |
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#define PEBS_DATACFG_LBRS BIT_ULL(3) |
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#define PEBS_DATACFG_LBR_SHIFT 24 |
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/* |
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* Intel "Architectural Performance Monitoring" CPUID |
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* detection/enumeration details: |
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*/ |
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union cpuid10_eax { |
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struct { |
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unsigned int version_id:8; |
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unsigned int num_counters:8; |
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unsigned int bit_width:8; |
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unsigned int mask_length:8; |
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} split; |
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unsigned int full; |
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}; |
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union cpuid10_ebx { |
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struct { |
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unsigned int no_unhalted_core_cycles:1; |
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unsigned int no_instructions_retired:1; |
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unsigned int no_unhalted_reference_cycles:1; |
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unsigned int no_llc_reference:1; |
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unsigned int no_llc_misses:1; |
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unsigned int no_branch_instruction_retired:1; |
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unsigned int no_branch_misses_retired:1; |
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} split; |
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unsigned int full; |
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}; |
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union cpuid10_edx { |
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struct { |
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unsigned int num_counters_fixed:5; |
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unsigned int bit_width_fixed:8; |
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unsigned int reserved1:2; |
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unsigned int anythread_deprecated:1; |
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unsigned int reserved2:16; |
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} split; |
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unsigned int full; |
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}; |
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/* |
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* Intel Architectural LBR CPUID detection/enumeration details: |
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*/ |
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union cpuid28_eax { |
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struct { |
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/* Supported LBR depth values */ |
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unsigned int lbr_depth_mask:8; |
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unsigned int reserved:22; |
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/* Deep C-state Reset */ |
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unsigned int lbr_deep_c_reset:1; |
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/* IP values contain LIP */ |
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unsigned int lbr_lip:1; |
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} split; |
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unsigned int full; |
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}; |
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union cpuid28_ebx { |
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struct { |
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/* CPL Filtering Supported */ |
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unsigned int lbr_cpl:1; |
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/* Branch Filtering Supported */ |
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unsigned int lbr_filter:1; |
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/* Call-stack Mode Supported */ |
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unsigned int lbr_call_stack:1; |
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} split; |
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unsigned int full; |
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}; |
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union cpuid28_ecx { |
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struct { |
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/* Mispredict Bit Supported */ |
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unsigned int lbr_mispred:1; |
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/* Timed LBRs Supported */ |
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unsigned int lbr_timed_lbr:1; |
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/* Branch Type Field Supported */ |
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unsigned int lbr_br_type:1; |
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} split; |
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unsigned int full; |
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}; |
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struct x86_pmu_capability { |
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int version; |
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int num_counters_gp; |
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int num_counters_fixed; |
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int bit_width_gp; |
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int bit_width_fixed; |
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unsigned int events_mask; |
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int events_mask_len; |
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}; |
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/* |
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* Fixed-purpose performance events: |
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*/ |
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/* RDPMC offset for Fixed PMCs */ |
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#define INTEL_PMC_FIXED_RDPMC_BASE (1 << 30) |
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#define INTEL_PMC_FIXED_RDPMC_METRICS (1 << 29) |
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/* |
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* All the fixed-mode PMCs are configured via this single MSR: |
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*/ |
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#define MSR_ARCH_PERFMON_FIXED_CTR_CTRL 0x38d |
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/* |
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* There is no event-code assigned to the fixed-mode PMCs. |
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* |
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* For a fixed-mode PMC, which has an equivalent event on a general-purpose |
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* PMC, the event-code of the equivalent event is used for the fixed-mode PMC, |
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* e.g., Instr_Retired.Any and CPU_CLK_Unhalted.Core. |
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* |
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* For a fixed-mode PMC, which doesn't have an equivalent event, a |
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* pseudo-encoding is used, e.g., CPU_CLK_Unhalted.Ref and TOPDOWN.SLOTS. |
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* The pseudo event-code for a fixed-mode PMC must be 0x00. |
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* The pseudo umask-code is 0xX. The X equals the index of the fixed |
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* counter + 1, e.g., the fixed counter 2 has the pseudo-encoding 0x0300. |
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* |
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* The counts are available in separate MSRs: |
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*/ |
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/* Instr_Retired.Any: */ |
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#define MSR_ARCH_PERFMON_FIXED_CTR0 0x309 |
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#define INTEL_PMC_IDX_FIXED_INSTRUCTIONS (INTEL_PMC_IDX_FIXED + 0) |
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/* CPU_CLK_Unhalted.Core: */ |
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#define MSR_ARCH_PERFMON_FIXED_CTR1 0x30a |
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#define INTEL_PMC_IDX_FIXED_CPU_CYCLES (INTEL_PMC_IDX_FIXED + 1) |
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/* CPU_CLK_Unhalted.Ref: event=0x00,umask=0x3 (pseudo-encoding) */ |
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#define MSR_ARCH_PERFMON_FIXED_CTR2 0x30b |
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#define INTEL_PMC_IDX_FIXED_REF_CYCLES (INTEL_PMC_IDX_FIXED + 2) |
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#define INTEL_PMC_MSK_FIXED_REF_CYCLES (1ULL << INTEL_PMC_IDX_FIXED_REF_CYCLES) |
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/* TOPDOWN.SLOTS: event=0x00,umask=0x4 (pseudo-encoding) */ |
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#define MSR_ARCH_PERFMON_FIXED_CTR3 0x30c |
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#define INTEL_PMC_IDX_FIXED_SLOTS (INTEL_PMC_IDX_FIXED + 3) |
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#define INTEL_PMC_MSK_FIXED_SLOTS (1ULL << INTEL_PMC_IDX_FIXED_SLOTS) |
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/* |
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* We model BTS tracing as another fixed-mode PMC. |
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* |
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* We choose the value 47 for the fixed index of BTS, since lower |
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* values are used by actual fixed events and higher values are used |
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* to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr. |
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*/ |
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#define INTEL_PMC_IDX_FIXED_BTS (INTEL_PMC_IDX_FIXED + 15) |
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/* |
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* The PERF_METRICS MSR is modeled as several magic fixed-mode PMCs, one for |
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* each TopDown metric event. |
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* |
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* Internally the TopDown metric events are mapped to the FxCtr 3 (SLOTS). |
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*/ |
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#define INTEL_PMC_IDX_METRIC_BASE (INTEL_PMC_IDX_FIXED + 16) |
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#define INTEL_PMC_IDX_TD_RETIRING (INTEL_PMC_IDX_METRIC_BASE + 0) |
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#define INTEL_PMC_IDX_TD_BAD_SPEC (INTEL_PMC_IDX_METRIC_BASE + 1) |
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#define INTEL_PMC_IDX_TD_FE_BOUND (INTEL_PMC_IDX_METRIC_BASE + 2) |
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#define INTEL_PMC_IDX_TD_BE_BOUND (INTEL_PMC_IDX_METRIC_BASE + 3) |
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#define INTEL_PMC_IDX_TD_HEAVY_OPS (INTEL_PMC_IDX_METRIC_BASE + 4) |
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#define INTEL_PMC_IDX_TD_BR_MISPREDICT (INTEL_PMC_IDX_METRIC_BASE + 5) |
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#define INTEL_PMC_IDX_TD_FETCH_LAT (INTEL_PMC_IDX_METRIC_BASE + 6) |
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#define INTEL_PMC_IDX_TD_MEM_BOUND (INTEL_PMC_IDX_METRIC_BASE + 7) |
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#define INTEL_PMC_IDX_METRIC_END INTEL_PMC_IDX_TD_MEM_BOUND |
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#define INTEL_PMC_MSK_TOPDOWN ((0xffull << INTEL_PMC_IDX_METRIC_BASE) | \ |
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INTEL_PMC_MSK_FIXED_SLOTS) |
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/* |
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* There is no event-code assigned to the TopDown events. |
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* |
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* For the slots event, use the pseudo code of the fixed counter 3. |
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* |
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* For the metric events, the pseudo event-code is 0x00. |
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* The pseudo umask-code starts from the middle of the pseudo event |
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* space, 0x80. |
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*/ |
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#define INTEL_TD_SLOTS 0x0400 /* TOPDOWN.SLOTS */ |
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/* Level 1 metrics */ |
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#define INTEL_TD_METRIC_RETIRING 0x8000 /* Retiring metric */ |
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#define INTEL_TD_METRIC_BAD_SPEC 0x8100 /* Bad speculation metric */ |
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#define INTEL_TD_METRIC_FE_BOUND 0x8200 /* FE bound metric */ |
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#define INTEL_TD_METRIC_BE_BOUND 0x8300 /* BE bound metric */ |
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/* Level 2 metrics */ |
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#define INTEL_TD_METRIC_HEAVY_OPS 0x8400 /* Heavy Operations metric */ |
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#define INTEL_TD_METRIC_BR_MISPREDICT 0x8500 /* Branch Mispredict metric */ |
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#define INTEL_TD_METRIC_FETCH_LAT 0x8600 /* Fetch Latency metric */ |
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#define INTEL_TD_METRIC_MEM_BOUND 0x8700 /* Memory bound metric */ |
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#define INTEL_TD_METRIC_MAX INTEL_TD_METRIC_MEM_BOUND |
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#define INTEL_TD_METRIC_NUM 8 |
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static inline bool is_metric_idx(int idx) |
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{ |
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return (unsigned)(idx - INTEL_PMC_IDX_METRIC_BASE) < INTEL_TD_METRIC_NUM; |
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} |
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static inline bool is_topdown_idx(int idx) |
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{ |
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return is_metric_idx(idx) || idx == INTEL_PMC_IDX_FIXED_SLOTS; |
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} |
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#define INTEL_PMC_OTHER_TOPDOWN_BITS(bit) \ |
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(~(0x1ull << bit) & INTEL_PMC_MSK_TOPDOWN) |
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#define GLOBAL_STATUS_COND_CHG BIT_ULL(63) |
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#define GLOBAL_STATUS_BUFFER_OVF_BIT 62 |
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#define GLOBAL_STATUS_BUFFER_OVF BIT_ULL(GLOBAL_STATUS_BUFFER_OVF_BIT) |
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#define GLOBAL_STATUS_UNC_OVF BIT_ULL(61) |
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#define GLOBAL_STATUS_ASIF BIT_ULL(60) |
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#define GLOBAL_STATUS_COUNTERS_FROZEN BIT_ULL(59) |
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#define GLOBAL_STATUS_LBRS_FROZEN_BIT 58 |
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#define GLOBAL_STATUS_LBRS_FROZEN BIT_ULL(GLOBAL_STATUS_LBRS_FROZEN_BIT) |
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#define GLOBAL_STATUS_TRACE_TOPAPMI_BIT 55 |
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#define GLOBAL_STATUS_TRACE_TOPAPMI BIT_ULL(GLOBAL_STATUS_TRACE_TOPAPMI_BIT) |
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#define GLOBAL_STATUS_PERF_METRICS_OVF_BIT 48 |
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#define GLOBAL_CTRL_EN_PERF_METRICS 48 |
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/* |
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* We model guest LBR event tracing as another fixed-mode PMC like BTS. |
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* |
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* We choose bit 58 because it's used to indicate LBR stack frozen state |
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* for architectural perfmon v4, also we unconditionally mask that bit in |
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* the handle_pmi_common(), so it'll never be set in the overflow handling. |
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* |
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* With this fake counter assigned, the guest LBR event user (such as KVM), |
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* can program the LBR registers on its own, and we don't actually do anything |
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* with then in the host context. |
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*/ |
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#define INTEL_PMC_IDX_FIXED_VLBR (GLOBAL_STATUS_LBRS_FROZEN_BIT) |
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/* |
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* Pseudo-encoding the guest LBR event as event=0x00,umask=0x1b, |
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* since it would claim bit 58 which is effectively Fixed26. |
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*/ |
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#define INTEL_FIXED_VLBR_EVENT 0x1b00 |
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/* |
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* Adaptive PEBS v4 |
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*/ |
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struct pebs_basic { |
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u64 format_size; |
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u64 ip; |
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u64 applicable_counters; |
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u64 tsc; |
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}; |
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struct pebs_meminfo { |
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u64 address; |
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u64 aux; |
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u64 latency; |
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u64 tsx_tuning; |
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}; |
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struct pebs_gprs { |
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u64 flags, ip, ax, cx, dx, bx, sp, bp, si, di; |
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u64 r8, r9, r10, r11, r12, r13, r14, r15; |
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}; |
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struct pebs_xmm { |
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u64 xmm[16*2]; /* two entries for each register */ |
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}; |
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/* |
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* IBS cpuid feature detection |
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*/ |
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#define IBS_CPUID_FEATURES 0x8000001b |
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/* |
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* Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but |
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* bit 0 is used to indicate the existence of IBS. |
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*/ |
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#define IBS_CAPS_AVAIL (1U<<0) |
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#define IBS_CAPS_FETCHSAM (1U<<1) |
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#define IBS_CAPS_OPSAM (1U<<2) |
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#define IBS_CAPS_RDWROPCNT (1U<<3) |
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#define IBS_CAPS_OPCNT (1U<<4) |
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#define IBS_CAPS_BRNTRGT (1U<<5) |
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#define IBS_CAPS_OPCNTEXT (1U<<6) |
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#define IBS_CAPS_RIPINVALIDCHK (1U<<7) |
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#define IBS_CAPS_OPBRNFUSE (1U<<8) |
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#define IBS_CAPS_FETCHCTLEXTD (1U<<9) |
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#define IBS_CAPS_OPDATA4 (1U<<10) |
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#define IBS_CAPS_DEFAULT (IBS_CAPS_AVAIL \ |
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| IBS_CAPS_FETCHSAM \ |
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| IBS_CAPS_OPSAM) |
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/* |
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* IBS APIC setup |
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*/ |
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#define IBSCTL 0x1cc |
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#define IBSCTL_LVT_OFFSET_VALID (1ULL<<8) |
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#define IBSCTL_LVT_OFFSET_MASK 0x0F |
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/* IBS fetch bits/masks */ |
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#define IBS_FETCH_RAND_EN (1ULL<<57) |
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#define IBS_FETCH_VAL (1ULL<<49) |
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#define IBS_FETCH_ENABLE (1ULL<<48) |
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#define IBS_FETCH_CNT 0xFFFF0000ULL |
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#define IBS_FETCH_MAX_CNT 0x0000FFFFULL |
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/* |
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* IBS op bits/masks |
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* The lower 7 bits of the current count are random bits |
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* preloaded by hardware and ignored in software |
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*/ |
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#define IBS_OP_CUR_CNT (0xFFF80ULL<<32) |
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#define IBS_OP_CUR_CNT_RAND (0x0007FULL<<32) |
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#define IBS_OP_CNT_CTL (1ULL<<19) |
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#define IBS_OP_VAL (1ULL<<18) |
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#define IBS_OP_ENABLE (1ULL<<17) |
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#define IBS_OP_MAX_CNT 0x0000FFFFULL |
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#define IBS_OP_MAX_CNT_EXT 0x007FFFFFULL /* not a register bit mask */ |
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#define IBS_OP_MAX_CNT_EXT_MASK (0x7FULL<<20) /* separate upper 7 bits */ |
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#define IBS_RIP_INVALID (1ULL<<38) |
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#ifdef CONFIG_X86_LOCAL_APIC |
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extern u32 get_ibs_caps(void); |
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#else |
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static inline u32 get_ibs_caps(void) { return 0; } |
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#endif |
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#ifdef CONFIG_PERF_EVENTS |
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extern void perf_events_lapic_init(void); |
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/* |
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* Abuse bits {3,5} of the cpu eflags register. These flags are otherwise |
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* unused and ABI specified to be 0, so nobody should care what we do with |
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* them. |
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* |
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* EXACT - the IP points to the exact instruction that triggered the |
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* event (HW bugs exempt). |
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* VM - original X86_VM_MASK; see set_linear_ip(). |
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*/ |
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#define PERF_EFLAGS_EXACT (1UL << 3) |
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#define PERF_EFLAGS_VM (1UL << 5) |
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struct pt_regs; |
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struct x86_perf_regs { |
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struct pt_regs regs; |
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u64 *xmm_regs; |
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}; |
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extern unsigned long perf_instruction_pointer(struct pt_regs *regs); |
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extern unsigned long perf_misc_flags(struct pt_regs *regs); |
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#define perf_misc_flags(regs) perf_misc_flags(regs) |
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#include <asm/stacktrace.h> |
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/* |
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* We abuse bit 3 from flags to pass exact information, see perf_misc_flags |
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* and the comment with PERF_EFLAGS_EXACT. |
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*/ |
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#define perf_arch_fetch_caller_regs(regs, __ip) { \ |
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(regs)->ip = (__ip); \ |
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(regs)->sp = (unsigned long)__builtin_frame_address(0); \ |
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(regs)->cs = __KERNEL_CS; \ |
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regs->flags = 0; \ |
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} |
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struct perf_guest_switch_msr { |
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unsigned msr; |
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u64 host, guest; |
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}; |
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struct x86_pmu_lbr { |
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unsigned int nr; |
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unsigned int from; |
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unsigned int to; |
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unsigned int info; |
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}; |
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extern void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap); |
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extern void perf_check_microcode(void); |
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extern int x86_perf_rdpmc_index(struct perf_event *event); |
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#else |
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static inline void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap) |
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{ |
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memset(cap, 0, sizeof(*cap)); |
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} |
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static inline void perf_events_lapic_init(void) { } |
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static inline void perf_check_microcode(void) { } |
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#endif |
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#if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_INTEL) |
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extern struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr); |
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extern int x86_perf_get_lbr(struct x86_pmu_lbr *lbr); |
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#else |
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struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr); |
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static inline int x86_perf_get_lbr(struct x86_pmu_lbr *lbr) |
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{ |
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return -1; |
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} |
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#endif |
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|
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#ifdef CONFIG_CPU_SUP_INTEL |
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extern void intel_pt_handle_vmx(int on); |
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#else |
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static inline void intel_pt_handle_vmx(int on) |
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{ |
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|
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} |
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#endif |
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#if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD) |
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extern void amd_pmu_enable_virt(void); |
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extern void amd_pmu_disable_virt(void); |
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#else |
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static inline void amd_pmu_enable_virt(void) { } |
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static inline void amd_pmu_disable_virt(void) { } |
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#endif |
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#define arch_perf_out_copy_user copy_from_user_nmi |
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|
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#endif /* _ASM_X86_PERF_EVENT_H */
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