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143 lines
4.3 KiB
143 lines
4.3 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#ifndef _ASM_X86_MWAIT_H |
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#define _ASM_X86_MWAIT_H |
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#include <linux/sched.h> |
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#include <linux/sched/idle.h> |
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#include <asm/cpufeature.h> |
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#include <asm/nospec-branch.h> |
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#define MWAIT_SUBSTATE_MASK 0xf |
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#define MWAIT_CSTATE_MASK 0xf |
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#define MWAIT_SUBSTATE_SIZE 4 |
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#define MWAIT_HINT2CSTATE(hint) (((hint) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) |
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#define MWAIT_HINT2SUBSTATE(hint) ((hint) & MWAIT_CSTATE_MASK) |
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#define CPUID_MWAIT_LEAF 5 |
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#define CPUID5_ECX_EXTENSIONS_SUPPORTED 0x1 |
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#define CPUID5_ECX_INTERRUPT_BREAK 0x2 |
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#define MWAIT_ECX_INTERRUPT_BREAK 0x1 |
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#define MWAITX_ECX_TIMER_ENABLE BIT(1) |
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#define MWAITX_MAX_WAIT_CYCLES UINT_MAX |
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#define MWAITX_DISABLE_CSTATES 0xf0 |
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#define TPAUSE_C01_STATE 1 |
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#define TPAUSE_C02_STATE 0 |
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static inline void __monitor(const void *eax, unsigned long ecx, |
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unsigned long edx) |
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{ |
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/* "monitor %eax, %ecx, %edx;" */ |
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asm volatile(".byte 0x0f, 0x01, 0xc8;" |
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:: "a" (eax), "c" (ecx), "d"(edx)); |
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} |
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static inline void __monitorx(const void *eax, unsigned long ecx, |
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unsigned long edx) |
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{ |
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/* "monitorx %eax, %ecx, %edx;" */ |
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asm volatile(".byte 0x0f, 0x01, 0xfa;" |
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:: "a" (eax), "c" (ecx), "d"(edx)); |
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} |
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static inline void __mwait(unsigned long eax, unsigned long ecx) |
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{ |
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mds_idle_clear_cpu_buffers(); |
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/* "mwait %eax, %ecx;" */ |
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asm volatile(".byte 0x0f, 0x01, 0xc9;" |
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:: "a" (eax), "c" (ecx)); |
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} |
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/* |
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* MWAITX allows for a timer expiration to get the core out a wait state in |
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* addition to the default MWAIT exit condition of a store appearing at a |
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* monitored virtual address. |
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* |
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* Registers: |
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* |
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* MWAITX ECX[1]: enable timer if set |
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* MWAITX EBX[31:0]: max wait time expressed in SW P0 clocks. The software P0 |
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* frequency is the same as the TSC frequency. |
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* |
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* Below is a comparison between MWAIT and MWAITX on AMD processors: |
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* |
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* MWAIT MWAITX |
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* opcode 0f 01 c9 | 0f 01 fb |
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* ECX[0] value of RFLAGS.IF seen by instruction |
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* ECX[1] unused/#GP if set | enable timer if set |
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* ECX[31:2] unused/#GP if set |
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* EAX unused (reserve for hint) |
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* EBX[31:0] unused | max wait time (P0 clocks) |
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* |
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* MONITOR MONITORX |
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* opcode 0f 01 c8 | 0f 01 fa |
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* EAX (logical) address to monitor |
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* ECX #GP if not zero |
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*/ |
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static inline void __mwaitx(unsigned long eax, unsigned long ebx, |
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unsigned long ecx) |
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{ |
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/* No MDS buffer clear as this is AMD/HYGON only */ |
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/* "mwaitx %eax, %ebx, %ecx;" */ |
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asm volatile(".byte 0x0f, 0x01, 0xfb;" |
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:: "a" (eax), "b" (ebx), "c" (ecx)); |
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} |
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static inline void __sti_mwait(unsigned long eax, unsigned long ecx) |
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{ |
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mds_idle_clear_cpu_buffers(); |
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/* "mwait %eax, %ecx;" */ |
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asm volatile("sti; .byte 0x0f, 0x01, 0xc9;" |
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:: "a" (eax), "c" (ecx)); |
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} |
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/* |
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* This uses new MONITOR/MWAIT instructions on P4 processors with PNI, |
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* which can obviate IPI to trigger checking of need_resched. |
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* We execute MONITOR against need_resched and enter optimized wait state |
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* through MWAIT. Whenever someone changes need_resched, we would be woken |
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* up from MWAIT (without an IPI). |
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* |
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* New with Core Duo processors, MWAIT can take some hints based on CPU |
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* capability. |
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*/ |
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static inline void mwait_idle_with_hints(unsigned long eax, unsigned long ecx) |
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{ |
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if (static_cpu_has_bug(X86_BUG_MONITOR) || !current_set_polling_and_test()) { |
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if (static_cpu_has_bug(X86_BUG_CLFLUSH_MONITOR)) { |
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mb(); |
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clflush((void *)¤t_thread_info()->flags); |
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mb(); |
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} |
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__monitor((void *)¤t_thread_info()->flags, 0, 0); |
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if (!need_resched()) |
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__mwait(eax, ecx); |
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} |
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current_clr_polling(); |
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} |
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/* |
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* Caller can specify whether to enter C0.1 (low latency, less |
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* power saving) or C0.2 state (saves more power, but longer wakeup |
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* latency). This may be overridden by the IA32_UMWAIT_CONTROL MSR |
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* which can force requests for C0.2 to be downgraded to C0.1. |
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*/ |
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static inline void __tpause(u32 ecx, u32 edx, u32 eax) |
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{ |
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/* "tpause %ecx, %edx, %eax;" */ |
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#ifdef CONFIG_AS_TPAUSE |
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asm volatile("tpause %%ecx\n" |
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: |
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: "c"(ecx), "d"(edx), "a"(eax)); |
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#else |
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asm volatile(".byte 0x66, 0x0f, 0xae, 0xf1\t\n" |
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: |
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: "c"(ecx), "d"(edx), "a"(eax)); |
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#endif |
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} |
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#endif /* _ASM_X86_MWAIT_H */
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