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367 lines
13 KiB
367 lines
13 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#ifndef _ASM_X86_MCE_H |
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#define _ASM_X86_MCE_H |
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#include <uapi/asm/mce.h> |
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/* |
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* Machine Check support for x86 |
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*/ |
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/* MCG_CAP register defines */ |
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#define MCG_BANKCNT_MASK 0xff /* Number of Banks */ |
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#define MCG_CTL_P BIT_ULL(8) /* MCG_CTL register available */ |
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#define MCG_EXT_P BIT_ULL(9) /* Extended registers available */ |
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#define MCG_CMCI_P BIT_ULL(10) /* CMCI supported */ |
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#define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */ |
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#define MCG_EXT_CNT_SHIFT 16 |
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#define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT) |
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#define MCG_SER_P BIT_ULL(24) /* MCA recovery/new status bits */ |
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#define MCG_ELOG_P BIT_ULL(26) /* Extended error log supported */ |
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#define MCG_LMCE_P BIT_ULL(27) /* Local machine check supported */ |
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/* MCG_STATUS register defines */ |
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#define MCG_STATUS_RIPV BIT_ULL(0) /* restart ip valid */ |
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#define MCG_STATUS_EIPV BIT_ULL(1) /* ip points to correct instruction */ |
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#define MCG_STATUS_MCIP BIT_ULL(2) /* machine check in progress */ |
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#define MCG_STATUS_LMCES BIT_ULL(3) /* LMCE signaled */ |
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/* MCG_EXT_CTL register defines */ |
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#define MCG_EXT_CTL_LMCE_EN BIT_ULL(0) /* Enable LMCE */ |
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/* MCi_STATUS register defines */ |
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#define MCI_STATUS_VAL BIT_ULL(63) /* valid error */ |
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#define MCI_STATUS_OVER BIT_ULL(62) /* previous errors lost */ |
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#define MCI_STATUS_UC BIT_ULL(61) /* uncorrected error */ |
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#define MCI_STATUS_EN BIT_ULL(60) /* error enabled */ |
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#define MCI_STATUS_MISCV BIT_ULL(59) /* misc error reg. valid */ |
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#define MCI_STATUS_ADDRV BIT_ULL(58) /* addr reg. valid */ |
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#define MCI_STATUS_PCC BIT_ULL(57) /* processor context corrupt */ |
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#define MCI_STATUS_S BIT_ULL(56) /* Signaled machine check */ |
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#define MCI_STATUS_AR BIT_ULL(55) /* Action required */ |
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#define MCI_STATUS_CEC_SHIFT 38 /* Corrected Error Count */ |
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#define MCI_STATUS_CEC_MASK GENMASK_ULL(52,38) |
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#define MCI_STATUS_CEC(c) (((c) & MCI_STATUS_CEC_MASK) >> MCI_STATUS_CEC_SHIFT) |
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/* AMD-specific bits */ |
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#define MCI_STATUS_TCC BIT_ULL(55) /* Task context corrupt */ |
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#define MCI_STATUS_SYNDV BIT_ULL(53) /* synd reg. valid */ |
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#define MCI_STATUS_DEFERRED BIT_ULL(44) /* uncorrected error, deferred exception */ |
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#define MCI_STATUS_POISON BIT_ULL(43) /* access poisonous data */ |
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#define MCI_STATUS_SCRUB BIT_ULL(40) /* Error detected during scrub operation */ |
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/* |
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* McaX field if set indicates a given bank supports MCA extensions: |
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* - Deferred error interrupt type is specifiable by bank. |
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* - MCx_MISC0[BlkPtr] field indicates presence of extended MISC registers, |
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* But should not be used to determine MSR numbers. |
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* - TCC bit is present in MCx_STATUS. |
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*/ |
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#define MCI_CONFIG_MCAX 0x1 |
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#define MCI_IPID_MCATYPE 0xFFFF0000 |
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#define MCI_IPID_HWID 0xFFF |
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/* |
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* Note that the full MCACOD field of IA32_MCi_STATUS MSR is |
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* bits 15:0. But bit 12 is the 'F' bit, defined for corrected |
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* errors to indicate that errors are being filtered by hardware. |
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* We should mask out bit 12 when looking for specific signatures |
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* of uncorrected errors - so the F bit is deliberately skipped |
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* in this #define. |
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*/ |
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#define MCACOD 0xefff /* MCA Error Code */ |
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/* Architecturally defined codes from SDM Vol. 3B Chapter 15 */ |
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#define MCACOD_SCRUB 0x00C0 /* 0xC0-0xCF Memory Scrubbing */ |
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#define MCACOD_SCRUBMSK 0xeff0 /* Skip bit 12 ('F' bit) */ |
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#define MCACOD_L3WB 0x017A /* L3 Explicit Writeback */ |
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#define MCACOD_DATA 0x0134 /* Data Load */ |
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#define MCACOD_INSTR 0x0150 /* Instruction Fetch */ |
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/* MCi_MISC register defines */ |
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#define MCI_MISC_ADDR_LSB(m) ((m) & 0x3f) |
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#define MCI_MISC_ADDR_MODE(m) (((m) >> 6) & 7) |
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#define MCI_MISC_ADDR_SEGOFF 0 /* segment offset */ |
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#define MCI_MISC_ADDR_LINEAR 1 /* linear address */ |
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#define MCI_MISC_ADDR_PHYS 2 /* physical address */ |
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#define MCI_MISC_ADDR_MEM 3 /* memory address */ |
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#define MCI_MISC_ADDR_GENERIC 7 /* generic */ |
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/* CTL2 register defines */ |
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#define MCI_CTL2_CMCI_EN BIT_ULL(30) |
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#define MCI_CTL2_CMCI_THRESHOLD_MASK 0x7fffULL |
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#define MCJ_CTX_MASK 3 |
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#define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK) |
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#define MCJ_CTX_RANDOM 0 /* inject context: random */ |
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#define MCJ_CTX_PROCESS 0x1 /* inject context: process */ |
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#define MCJ_CTX_IRQ 0x2 /* inject context: IRQ */ |
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#define MCJ_NMI_BROADCAST 0x4 /* do NMI broadcasting */ |
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#define MCJ_EXCEPTION 0x8 /* raise as exception */ |
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#define MCJ_IRQ_BROADCAST 0x10 /* do IRQ broadcasting */ |
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#define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */ |
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#define MCE_LOG_MIN_LEN 32U |
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#define MCE_LOG_SIGNATURE "MACHINECHECK" |
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/* AMD Scalable MCA */ |
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#define MSR_AMD64_SMCA_MC0_CTL 0xc0002000 |
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#define MSR_AMD64_SMCA_MC0_STATUS 0xc0002001 |
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#define MSR_AMD64_SMCA_MC0_ADDR 0xc0002002 |
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#define MSR_AMD64_SMCA_MC0_MISC0 0xc0002003 |
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#define MSR_AMD64_SMCA_MC0_CONFIG 0xc0002004 |
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#define MSR_AMD64_SMCA_MC0_IPID 0xc0002005 |
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#define MSR_AMD64_SMCA_MC0_SYND 0xc0002006 |
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#define MSR_AMD64_SMCA_MC0_DESTAT 0xc0002008 |
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#define MSR_AMD64_SMCA_MC0_DEADDR 0xc0002009 |
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#define MSR_AMD64_SMCA_MC0_MISC1 0xc000200a |
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#define MSR_AMD64_SMCA_MCx_CTL(x) (MSR_AMD64_SMCA_MC0_CTL + 0x10*(x)) |
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#define MSR_AMD64_SMCA_MCx_STATUS(x) (MSR_AMD64_SMCA_MC0_STATUS + 0x10*(x)) |
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#define MSR_AMD64_SMCA_MCx_ADDR(x) (MSR_AMD64_SMCA_MC0_ADDR + 0x10*(x)) |
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#define MSR_AMD64_SMCA_MCx_MISC(x) (MSR_AMD64_SMCA_MC0_MISC0 + 0x10*(x)) |
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#define MSR_AMD64_SMCA_MCx_CONFIG(x) (MSR_AMD64_SMCA_MC0_CONFIG + 0x10*(x)) |
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#define MSR_AMD64_SMCA_MCx_IPID(x) (MSR_AMD64_SMCA_MC0_IPID + 0x10*(x)) |
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#define MSR_AMD64_SMCA_MCx_SYND(x) (MSR_AMD64_SMCA_MC0_SYND + 0x10*(x)) |
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#define MSR_AMD64_SMCA_MCx_DESTAT(x) (MSR_AMD64_SMCA_MC0_DESTAT + 0x10*(x)) |
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#define MSR_AMD64_SMCA_MCx_DEADDR(x) (MSR_AMD64_SMCA_MC0_DEADDR + 0x10*(x)) |
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#define MSR_AMD64_SMCA_MCx_MISCy(x, y) ((MSR_AMD64_SMCA_MC0_MISC1 + y) + (0x10*(x))) |
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#define XEC(x, mask) (((x) >> 16) & mask) |
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/* mce.kflags flag bits for logging etc. */ |
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#define MCE_HANDLED_CEC BIT_ULL(0) |
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#define MCE_HANDLED_UC BIT_ULL(1) |
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#define MCE_HANDLED_EXTLOG BIT_ULL(2) |
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#define MCE_HANDLED_NFIT BIT_ULL(3) |
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#define MCE_HANDLED_EDAC BIT_ULL(4) |
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#define MCE_HANDLED_MCELOG BIT_ULL(5) |
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/* |
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* Indicates an MCE which has happened in kernel space but from |
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* which the kernel can recover simply by executing fixup_exception() |
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* so that an error is returned to the caller of the function that |
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* hit the machine check. |
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*/ |
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#define MCE_IN_KERNEL_RECOV BIT_ULL(6) |
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/* |
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* Indicates an MCE that happened in kernel space while copying data |
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* from user. In this case fixup_exception() gets the kernel to the |
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* error exit for the copy function. Machine check handler can then |
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* treat it like a fault taken in user mode. |
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*/ |
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#define MCE_IN_KERNEL_COPYIN BIT_ULL(7) |
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/* |
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* This structure contains all data related to the MCE log. Also |
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* carries a signature to make it easier to find from external |
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* debugging tools. Each entry is only valid when its finished flag |
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* is set. |
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*/ |
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struct mce_log_buffer { |
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char signature[12]; /* "MACHINECHECK" */ |
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unsigned len; /* = elements in .mce_entry[] */ |
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unsigned next; |
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unsigned flags; |
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unsigned recordlen; /* length of struct mce */ |
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struct mce entry[]; |
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}; |
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/* Highest last */ |
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enum mce_notifier_prios { |
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MCE_PRIO_LOWEST, |
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MCE_PRIO_MCELOG, |
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MCE_PRIO_EDAC, |
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MCE_PRIO_NFIT, |
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MCE_PRIO_EXTLOG, |
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MCE_PRIO_UC, |
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MCE_PRIO_EARLY, |
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MCE_PRIO_CEC, |
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MCE_PRIO_HIGHEST = MCE_PRIO_CEC |
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}; |
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struct notifier_block; |
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extern void mce_register_decode_chain(struct notifier_block *nb); |
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extern void mce_unregister_decode_chain(struct notifier_block *nb); |
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#include <linux/percpu.h> |
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#include <linux/atomic.h> |
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extern int mce_p5_enabled; |
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#ifdef CONFIG_ARCH_HAS_COPY_MC |
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extern void enable_copy_mc_fragile(void); |
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unsigned long __must_check copy_mc_fragile(void *dst, const void *src, unsigned cnt); |
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#else |
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static inline void enable_copy_mc_fragile(void) |
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{ |
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} |
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#endif |
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struct cper_ia_proc_ctx; |
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#ifdef CONFIG_X86_MCE |
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int mcheck_init(void); |
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void mcheck_cpu_init(struct cpuinfo_x86 *c); |
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void mcheck_cpu_clear(struct cpuinfo_x86 *c); |
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void mcheck_vendor_init_severity(void); |
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int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info, |
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u64 lapic_id); |
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#else |
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static inline int mcheck_init(void) { return 0; } |
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static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {} |
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static inline void mcheck_cpu_clear(struct cpuinfo_x86 *c) {} |
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static inline void mcheck_vendor_init_severity(void) {} |
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static inline int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info, |
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u64 lapic_id) { return -EINVAL; } |
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#endif |
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#ifdef CONFIG_X86_ANCIENT_MCE |
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void intel_p5_mcheck_init(struct cpuinfo_x86 *c); |
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void winchip_mcheck_init(struct cpuinfo_x86 *c); |
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static inline void enable_p5_mce(void) { mce_p5_enabled = 1; } |
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#else |
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static inline void intel_p5_mcheck_init(struct cpuinfo_x86 *c) {} |
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static inline void winchip_mcheck_init(struct cpuinfo_x86 *c) {} |
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static inline void enable_p5_mce(void) {} |
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#endif |
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void mce_setup(struct mce *m); |
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void mce_log(struct mce *m); |
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DECLARE_PER_CPU(struct device *, mce_device); |
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/* Maximum number of MCA banks per CPU. */ |
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#define MAX_NR_BANKS 64 |
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#ifdef CONFIG_X86_MCE_INTEL |
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void mce_intel_feature_init(struct cpuinfo_x86 *c); |
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void mce_intel_feature_clear(struct cpuinfo_x86 *c); |
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void cmci_clear(void); |
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void cmci_reenable(void); |
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void cmci_rediscover(void); |
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void cmci_recheck(void); |
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#else |
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static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { } |
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static inline void mce_intel_feature_clear(struct cpuinfo_x86 *c) { } |
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static inline void cmci_clear(void) {} |
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static inline void cmci_reenable(void) {} |
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static inline void cmci_rediscover(void) {} |
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static inline void cmci_recheck(void) {} |
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#endif |
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int mce_available(struct cpuinfo_x86 *c); |
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bool mce_is_memory_error(struct mce *m); |
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bool mce_is_correctable(struct mce *m); |
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int mce_usable_address(struct mce *m); |
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DECLARE_PER_CPU(unsigned, mce_exception_count); |
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DECLARE_PER_CPU(unsigned, mce_poll_count); |
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typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS); |
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DECLARE_PER_CPU(mce_banks_t, mce_poll_banks); |
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enum mcp_flags { |
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MCP_TIMESTAMP = BIT(0), /* log time stamp */ |
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MCP_UC = BIT(1), /* log uncorrected errors */ |
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MCP_DONTLOG = BIT(2), /* only clear, don't log */ |
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}; |
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bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b); |
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int mce_notify_irq(void); |
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DECLARE_PER_CPU(struct mce, injectm); |
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/* Disable CMCI/polling for MCA bank claimed by firmware */ |
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extern void mce_disable_bank(int bank); |
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/* |
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* Exception handler |
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*/ |
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void do_machine_check(struct pt_regs *pt_regs); |
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/* |
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* Threshold handler |
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*/ |
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extern void (*mce_threshold_vector)(void); |
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/* Deferred error interrupt handler */ |
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extern void (*deferred_error_int_vector)(void); |
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/* |
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* Used by APEI to report memory error via /dev/mcelog |
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*/ |
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struct cper_sec_mem_err; |
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extern void apei_mce_report_mem_error(int corrected, |
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struct cper_sec_mem_err *mem_err); |
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/* |
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* Enumerate new IP types and HWID values in AMD processors which support |
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* Scalable MCA. |
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*/ |
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#ifdef CONFIG_X86_MCE_AMD |
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/* These may be used by multiple smca_hwid_mcatypes */ |
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enum smca_bank_types { |
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SMCA_LS = 0, /* Load Store */ |
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SMCA_LS_V2, /* Load Store */ |
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SMCA_IF, /* Instruction Fetch */ |
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SMCA_L2_CACHE, /* L2 Cache */ |
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SMCA_DE, /* Decoder Unit */ |
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SMCA_RESERVED, /* Reserved */ |
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SMCA_EX, /* Execution Unit */ |
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SMCA_FP, /* Floating Point */ |
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SMCA_L3_CACHE, /* L3 Cache */ |
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SMCA_CS, /* Coherent Slave */ |
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SMCA_CS_V2, /* Coherent Slave */ |
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SMCA_PIE, /* Power, Interrupts, etc. */ |
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SMCA_UMC, /* Unified Memory Controller */ |
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SMCA_PB, /* Parameter Block */ |
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SMCA_PSP, /* Platform Security Processor */ |
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SMCA_PSP_V2, /* Platform Security Processor */ |
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SMCA_SMU, /* System Management Unit */ |
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SMCA_SMU_V2, /* System Management Unit */ |
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SMCA_MP5, /* Microprocessor 5 Unit */ |
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SMCA_NBIO, /* Northbridge IO Unit */ |
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SMCA_PCIE, /* PCI Express Unit */ |
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N_SMCA_BANK_TYPES |
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}; |
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#define HWID_MCATYPE(hwid, mcatype) (((hwid) << 16) | (mcatype)) |
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struct smca_hwid { |
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unsigned int bank_type; /* Use with smca_bank_types for easy indexing. */ |
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u32 hwid_mcatype; /* (hwid,mcatype) tuple */ |
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u8 count; /* Number of instances. */ |
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}; |
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struct smca_bank { |
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struct smca_hwid *hwid; |
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u32 id; /* Value of MCA_IPID[InstanceId]. */ |
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u8 sysfs_id; /* Value used for sysfs name. */ |
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}; |
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extern struct smca_bank smca_banks[MAX_NR_BANKS]; |
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extern const char *smca_get_long_name(enum smca_bank_types t); |
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extern bool amd_mce_is_memory_error(struct mce *m); |
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extern int mce_threshold_create_device(unsigned int cpu); |
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extern int mce_threshold_remove_device(unsigned int cpu); |
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void mce_amd_feature_init(struct cpuinfo_x86 *c); |
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int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr); |
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#else |
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static inline int mce_threshold_create_device(unsigned int cpu) { return 0; }; |
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static inline int mce_threshold_remove_device(unsigned int cpu) { return 0; }; |
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static inline bool amd_mce_is_memory_error(struct mce *m) { return false; }; |
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static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { } |
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static inline int |
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umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) { return -EINVAL; }; |
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#endif |
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static inline void mce_hygon_feature_init(struct cpuinfo_x86 *c) { return mce_amd_feature_init(c); } |
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#endif /* _ASM_X86_MCE_H */
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