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137 lines
4.3 KiB
137 lines
4.3 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#ifndef _ASM_X86_INTEL_FAMILY_H |
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#define _ASM_X86_INTEL_FAMILY_H |
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/* |
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* "Big Core" Processors (Branded as Core, Xeon, etc...) |
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* |
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* While adding a new CPUID for a new microarchitecture, add a new |
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* group to keep logically sorted out in chronological order. Within |
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* that group keep the CPUID for the variants sorted by model number. |
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* |
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* The defined symbol names have the following form: |
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* INTEL_FAM6{OPTFAMILY}_{MICROARCH}{OPTDIFF} |
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* where: |
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* OPTFAMILY Describes the family of CPUs that this belongs to. Default |
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* is assumed to be "_CORE" (and should be omitted). Other values |
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* currently in use are _ATOM and _XEON_PHI |
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* MICROARCH Is the code name for the micro-architecture for this core. |
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* N.B. Not the platform name. |
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* OPTDIFF If needed, a short string to differentiate by market segment. |
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* |
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* Common OPTDIFFs: |
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* |
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* - regular client parts |
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* _L - regular mobile parts |
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* _G - parts with extra graphics on |
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* _X - regular server parts |
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* _D - micro server parts |
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* |
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* Historical OPTDIFFs: |
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* |
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* _EP - 2 socket server parts |
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* _EX - 4+ socket server parts |
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* |
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* The #define line may optionally include a comment including platform names. |
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*/ |
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/* Wildcard match for FAM6 so X86_MATCH_INTEL_FAM6_MODEL(ANY) works */ |
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#define INTEL_FAM6_ANY X86_MODEL_ANY |
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#define INTEL_FAM6_CORE_YONAH 0x0E |
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#define INTEL_FAM6_CORE2_MEROM 0x0F |
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#define INTEL_FAM6_CORE2_MEROM_L 0x16 |
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#define INTEL_FAM6_CORE2_PENRYN 0x17 |
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#define INTEL_FAM6_CORE2_DUNNINGTON 0x1D |
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#define INTEL_FAM6_NEHALEM 0x1E |
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#define INTEL_FAM6_NEHALEM_G 0x1F /* Auburndale / Havendale */ |
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#define INTEL_FAM6_NEHALEM_EP 0x1A |
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#define INTEL_FAM6_NEHALEM_EX 0x2E |
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#define INTEL_FAM6_WESTMERE 0x25 |
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#define INTEL_FAM6_WESTMERE_EP 0x2C |
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#define INTEL_FAM6_WESTMERE_EX 0x2F |
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#define INTEL_FAM6_SANDYBRIDGE 0x2A |
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#define INTEL_FAM6_SANDYBRIDGE_X 0x2D |
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#define INTEL_FAM6_IVYBRIDGE 0x3A |
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#define INTEL_FAM6_IVYBRIDGE_X 0x3E |
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#define INTEL_FAM6_HASWELL 0x3C |
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#define INTEL_FAM6_HASWELL_X 0x3F |
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#define INTEL_FAM6_HASWELL_L 0x45 |
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#define INTEL_FAM6_HASWELL_G 0x46 |
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#define INTEL_FAM6_BROADWELL 0x3D |
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#define INTEL_FAM6_BROADWELL_G 0x47 |
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#define INTEL_FAM6_BROADWELL_X 0x4F |
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#define INTEL_FAM6_BROADWELL_D 0x56 |
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#define INTEL_FAM6_SKYLAKE_L 0x4E |
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#define INTEL_FAM6_SKYLAKE 0x5E |
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#define INTEL_FAM6_SKYLAKE_X 0x55 |
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#define INTEL_FAM6_KABYLAKE_L 0x8E |
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#define INTEL_FAM6_KABYLAKE 0x9E |
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#define INTEL_FAM6_CANNONLAKE_L 0x66 |
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#define INTEL_FAM6_ICELAKE_X 0x6A |
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#define INTEL_FAM6_ICELAKE_D 0x6C |
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#define INTEL_FAM6_ICELAKE 0x7D |
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#define INTEL_FAM6_ICELAKE_L 0x7E |
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#define INTEL_FAM6_ICELAKE_NNPI 0x9D |
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#define INTEL_FAM6_TIGERLAKE_L 0x8C |
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#define INTEL_FAM6_TIGERLAKE 0x8D |
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#define INTEL_FAM6_COMETLAKE 0xA5 |
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#define INTEL_FAM6_COMETLAKE_L 0xA6 |
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#define INTEL_FAM6_ROCKETLAKE 0xA7 |
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#define INTEL_FAM6_SAPPHIRERAPIDS_X 0x8F |
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/* Hybrid Core/Atom Processors */ |
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#define INTEL_FAM6_LAKEFIELD 0x8A |
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#define INTEL_FAM6_ALDERLAKE 0x97 |
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#define INTEL_FAM6_ALDERLAKE_L 0x9A |
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/* "Small Core" Processors (Atom) */ |
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#define INTEL_FAM6_ATOM_BONNELL 0x1C /* Diamondville, Pineview */ |
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#define INTEL_FAM6_ATOM_BONNELL_MID 0x26 /* Silverthorne, Lincroft */ |
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#define INTEL_FAM6_ATOM_SALTWELL 0x36 /* Cedarview */ |
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#define INTEL_FAM6_ATOM_SALTWELL_MID 0x27 /* Penwell */ |
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#define INTEL_FAM6_ATOM_SALTWELL_TABLET 0x35 /* Cloverview */ |
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#define INTEL_FAM6_ATOM_SILVERMONT 0x37 /* Bay Trail, Valleyview */ |
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#define INTEL_FAM6_ATOM_SILVERMONT_D 0x4D /* Avaton, Rangely */ |
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#define INTEL_FAM6_ATOM_SILVERMONT_MID 0x4A /* Merriefield */ |
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#define INTEL_FAM6_ATOM_AIRMONT 0x4C /* Cherry Trail, Braswell */ |
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#define INTEL_FAM6_ATOM_AIRMONT_MID 0x5A /* Moorefield */ |
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#define INTEL_FAM6_ATOM_AIRMONT_NP 0x75 /* Lightning Mountain */ |
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#define INTEL_FAM6_ATOM_GOLDMONT 0x5C /* Apollo Lake */ |
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#define INTEL_FAM6_ATOM_GOLDMONT_D 0x5F /* Denverton */ |
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/* Note: the micro-architecture is "Goldmont Plus" */ |
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#define INTEL_FAM6_ATOM_GOLDMONT_PLUS 0x7A /* Gemini Lake */ |
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#define INTEL_FAM6_ATOM_TREMONT_D 0x86 /* Jacobsville */ |
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#define INTEL_FAM6_ATOM_TREMONT 0x96 /* Elkhart Lake */ |
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#define INTEL_FAM6_ATOM_TREMONT_L 0x9C /* Jasper Lake */ |
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/* Xeon Phi */ |
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#define INTEL_FAM6_XEON_PHI_KNL 0x57 /* Knights Landing */ |
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#define INTEL_FAM6_XEON_PHI_KNM 0x85 /* Knights Mill */ |
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/* Family 5 */ |
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#define INTEL_FAM5_QUARK_X1000 0x09 /* Quark X1000 SoC */ |
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#endif /* _ASM_X86_INTEL_FAMILY_H */
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