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56 lines
1.6 KiB
56 lines
1.6 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* imr.h: Isolated Memory Region API |
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* |
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* Copyright(c) 2013 Intel Corporation. |
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* Copyright(c) 2015 Bryan O'Donoghue <[email protected]> |
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*/ |
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#ifndef _IMR_H |
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#define _IMR_H |
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#include <linux/types.h> |
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/* |
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* IMR agent access mask bits |
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* See section 12.7.4.7 from quark-x1000-datasheet.pdf for register |
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* definitions. |
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*/ |
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#define IMR_ESRAM_FLUSH BIT(31) |
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#define IMR_CPU_SNOOP BIT(30) /* Applicable only to write */ |
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#define IMR_RMU BIT(29) |
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#define IMR_VC1_SAI_ID3 BIT(15) |
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#define IMR_VC1_SAI_ID2 BIT(14) |
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#define IMR_VC1_SAI_ID1 BIT(13) |
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#define IMR_VC1_SAI_ID0 BIT(12) |
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#define IMR_VC0_SAI_ID3 BIT(11) |
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#define IMR_VC0_SAI_ID2 BIT(10) |
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#define IMR_VC0_SAI_ID1 BIT(9) |
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#define IMR_VC0_SAI_ID0 BIT(8) |
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#define IMR_CPU_0 BIT(1) /* SMM mode */ |
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#define IMR_CPU BIT(0) /* Non SMM mode */ |
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#define IMR_ACCESS_NONE 0 |
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/* |
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* Read/Write access-all bits here include some reserved bits |
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* These are the values firmware uses and are accepted by hardware. |
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* The kernel defines read/write access-all in the same way as firmware |
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* in order to have a consistent and crisp definition across firmware, |
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* bootloader and kernel. |
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*/ |
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#define IMR_READ_ACCESS_ALL 0xBFFFFFFF |
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#define IMR_WRITE_ACCESS_ALL 0xFFFFFFFF |
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/* Number of IMRs provided by Quark X1000 SoC */ |
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#define QUARK_X1000_IMR_MAX 0x08 |
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#define QUARK_X1000_IMR_REGBASE 0x40 |
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/* IMR alignment bits - only bits 31:10 are checked for IMR validity */ |
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#define IMR_ALIGN 0x400 |
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#define IMR_MASK (IMR_ALIGN - 1) |
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int imr_add_range(phys_addr_t base, size_t size, |
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unsigned int rmask, unsigned int wmask); |
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int imr_remove_range(phys_addr_t base, size_t size); |
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#endif /* _IMR_H */
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