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115 lines
3.3 KiB
115 lines
3.3 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* Copyright (C) 1994 Linus Torvalds |
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* |
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* Pentium III FXSR, SSE support |
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* General FPU state handling cleanups |
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* Gareth Hughes <[email protected]>, May 2000 |
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* x86-64 work by Andi Kleen 2002 |
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*/ |
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#ifndef _ASM_X86_FPU_API_H |
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#define _ASM_X86_FPU_API_H |
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#include <linux/bottom_half.h> |
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/* |
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* Use kernel_fpu_begin/end() if you intend to use FPU in kernel context. It |
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* disables preemption so be careful if you intend to use it for long periods |
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* of time. |
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* If you intend to use the FPU in irq/softirq you need to check first with |
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* irq_fpu_usable() if it is possible. |
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*/ |
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/* Kernel FPU states to initialize in kernel_fpu_begin_mask() */ |
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#define KFPU_387 _BITUL(0) /* 387 state will be initialized */ |
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#define KFPU_MXCSR _BITUL(1) /* MXCSR will be initialized */ |
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extern void kernel_fpu_begin_mask(unsigned int kfpu_mask); |
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extern void kernel_fpu_end(void); |
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extern bool irq_fpu_usable(void); |
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extern void fpregs_mark_activate(void); |
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/* Code that is unaware of kernel_fpu_begin_mask() can use this */ |
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static inline void kernel_fpu_begin(void) |
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{ |
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#ifdef CONFIG_X86_64 |
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/* |
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* Any 64-bit code that uses 387 instructions must explicitly request |
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* KFPU_387. |
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*/ |
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kernel_fpu_begin_mask(KFPU_MXCSR); |
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#else |
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/* |
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* 32-bit kernel code may use 387 operations as well as SSE2, etc, |
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* as long as it checks that the CPU has the required capability. |
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*/ |
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kernel_fpu_begin_mask(KFPU_387 | KFPU_MXCSR); |
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#endif |
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} |
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/* |
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* Use fpregs_lock() while editing CPU's FPU registers or fpu->state. |
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* A context switch will (and softirq might) save CPU's FPU registers to |
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* fpu->state and set TIF_NEED_FPU_LOAD leaving CPU's FPU registers in |
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* a random state. |
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* |
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* local_bh_disable() protects against both preemption and soft interrupts |
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* on !RT kernels. |
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* |
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* On RT kernels local_bh_disable() is not sufficient because it only |
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* serializes soft interrupt related sections via a local lock, but stays |
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* preemptible. Disabling preemption is the right choice here as bottom |
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* half processing is always in thread context on RT kernels so it |
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* implicitly prevents bottom half processing as well. |
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* |
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* Disabling preemption also serializes against kernel_fpu_begin(). |
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*/ |
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static inline void fpregs_lock(void) |
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{ |
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if (!IS_ENABLED(CONFIG_PREEMPT_RT)) |
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local_bh_disable(); |
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else |
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preempt_disable(); |
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} |
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static inline void fpregs_unlock(void) |
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{ |
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if (!IS_ENABLED(CONFIG_PREEMPT_RT)) |
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local_bh_enable(); |
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else |
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preempt_enable(); |
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} |
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#ifdef CONFIG_X86_DEBUG_FPU |
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extern void fpregs_assert_state_consistent(void); |
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#else |
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static inline void fpregs_assert_state_consistent(void) { } |
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#endif |
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/* |
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* Load the task FPU state before returning to userspace. |
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*/ |
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extern void switch_fpu_return(void); |
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/* |
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* Query the presence of one or more xfeatures. Works on any legacy CPU as well. |
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* |
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* If 'feature_name' is set then put a human-readable description of |
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* the feature there as well - this can be used to print error (or success) |
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* messages. |
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*/ |
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extern int cpu_has_xfeatures(u64 xfeatures_mask, const char **feature_name); |
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/* |
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* Tasks that are not using SVA have mm->pasid set to zero to note that they |
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* will not have the valid bit set in MSR_IA32_PASID while they are running. |
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*/ |
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#define PASID_DISABLED 0 |
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#ifdef CONFIG_IOMMU_SUPPORT |
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/* Update current's PASID MSR/state by mm's PASID. */ |
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void update_pasid(void); |
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#else |
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static inline void update_pasid(void) { } |
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#endif |
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#endif /* _ASM_X86_FPU_API_H */
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