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432 lines
11 KiB
432 lines
11 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#ifndef _ASM_X86_DESC_H |
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#define _ASM_X86_DESC_H |
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#include <asm/desc_defs.h> |
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#include <asm/ldt.h> |
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#include <asm/mmu.h> |
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#include <asm/fixmap.h> |
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#include <asm/irq_vectors.h> |
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#include <asm/cpu_entry_area.h> |
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#include <linux/smp.h> |
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#include <linux/percpu.h> |
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static inline void fill_ldt(struct desc_struct *desc, const struct user_desc *info) |
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{ |
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desc->limit0 = info->limit & 0x0ffff; |
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desc->base0 = (info->base_addr & 0x0000ffff); |
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desc->base1 = (info->base_addr & 0x00ff0000) >> 16; |
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desc->type = (info->read_exec_only ^ 1) << 1; |
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desc->type |= info->contents << 2; |
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/* Set the ACCESS bit so it can be mapped RO */ |
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desc->type |= 1; |
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desc->s = 1; |
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desc->dpl = 0x3; |
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desc->p = info->seg_not_present ^ 1; |
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desc->limit1 = (info->limit & 0xf0000) >> 16; |
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desc->avl = info->useable; |
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desc->d = info->seg_32bit; |
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desc->g = info->limit_in_pages; |
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desc->base2 = (info->base_addr & 0xff000000) >> 24; |
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/* |
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* Don't allow setting of the lm bit. It would confuse |
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* user_64bit_mode and would get overridden by sysret anyway. |
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*/ |
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desc->l = 0; |
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} |
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struct gdt_page { |
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struct desc_struct gdt[GDT_ENTRIES]; |
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} __attribute__((aligned(PAGE_SIZE))); |
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DECLARE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page); |
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/* Provide the original GDT */ |
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static inline struct desc_struct *get_cpu_gdt_rw(unsigned int cpu) |
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{ |
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return per_cpu(gdt_page, cpu).gdt; |
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} |
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/* Provide the current original GDT */ |
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static inline struct desc_struct *get_current_gdt_rw(void) |
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{ |
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return this_cpu_ptr(&gdt_page)->gdt; |
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} |
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/* Provide the fixmap address of the remapped GDT */ |
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static inline struct desc_struct *get_cpu_gdt_ro(int cpu) |
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{ |
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return (struct desc_struct *)&get_cpu_entry_area(cpu)->gdt; |
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} |
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/* Provide the current read-only GDT */ |
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static inline struct desc_struct *get_current_gdt_ro(void) |
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{ |
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return get_cpu_gdt_ro(smp_processor_id()); |
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} |
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/* Provide the physical address of the GDT page. */ |
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static inline phys_addr_t get_cpu_gdt_paddr(unsigned int cpu) |
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{ |
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return per_cpu_ptr_to_phys(get_cpu_gdt_rw(cpu)); |
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} |
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static inline void pack_gate(gate_desc *gate, unsigned type, unsigned long func, |
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unsigned dpl, unsigned ist, unsigned seg) |
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{ |
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gate->offset_low = (u16) func; |
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gate->bits.p = 1; |
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gate->bits.dpl = dpl; |
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gate->bits.zero = 0; |
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gate->bits.type = type; |
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gate->offset_middle = (u16) (func >> 16); |
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#ifdef CONFIG_X86_64 |
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gate->segment = __KERNEL_CS; |
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gate->bits.ist = ist; |
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gate->reserved = 0; |
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gate->offset_high = (u32) (func >> 32); |
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#else |
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gate->segment = seg; |
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gate->bits.ist = 0; |
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#endif |
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} |
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static inline int desc_empty(const void *ptr) |
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{ |
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const u32 *desc = ptr; |
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return !(desc[0] | desc[1]); |
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} |
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#ifdef CONFIG_PARAVIRT_XXL |
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#include <asm/paravirt.h> |
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#else |
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#define load_TR_desc() native_load_tr_desc() |
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#define load_gdt(dtr) native_load_gdt(dtr) |
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#define load_idt(dtr) native_load_idt(dtr) |
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#define load_tr(tr) asm volatile("ltr %0"::"m" (tr)) |
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#define load_ldt(ldt) asm volatile("lldt %0"::"m" (ldt)) |
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#define store_gdt(dtr) native_store_gdt(dtr) |
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#define store_tr(tr) (tr = native_store_tr()) |
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#define load_TLS(t, cpu) native_load_tls(t, cpu) |
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#define set_ldt native_set_ldt |
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#define write_ldt_entry(dt, entry, desc) native_write_ldt_entry(dt, entry, desc) |
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#define write_gdt_entry(dt, entry, desc, type) native_write_gdt_entry(dt, entry, desc, type) |
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#define write_idt_entry(dt, entry, g) native_write_idt_entry(dt, entry, g) |
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static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries) |
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{ |
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} |
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static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries) |
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{ |
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} |
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#endif /* CONFIG_PARAVIRT_XXL */ |
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#define store_ldt(ldt) asm("sldt %0" : "=m"(ldt)) |
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static inline void native_write_idt_entry(gate_desc *idt, int entry, const gate_desc *gate) |
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{ |
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memcpy(&idt[entry], gate, sizeof(*gate)); |
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} |
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static inline void native_write_ldt_entry(struct desc_struct *ldt, int entry, const void *desc) |
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{ |
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memcpy(&ldt[entry], desc, 8); |
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} |
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static inline void |
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native_write_gdt_entry(struct desc_struct *gdt, int entry, const void *desc, int type) |
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{ |
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unsigned int size; |
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switch (type) { |
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case DESC_TSS: size = sizeof(tss_desc); break; |
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case DESC_LDT: size = sizeof(ldt_desc); break; |
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default: size = sizeof(*gdt); break; |
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} |
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memcpy(&gdt[entry], desc, size); |
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} |
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static inline void set_tssldt_descriptor(void *d, unsigned long addr, |
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unsigned type, unsigned size) |
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{ |
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struct ldttss_desc *desc = d; |
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memset(desc, 0, sizeof(*desc)); |
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desc->limit0 = (u16) size; |
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desc->base0 = (u16) addr; |
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desc->base1 = (addr >> 16) & 0xFF; |
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desc->type = type; |
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desc->p = 1; |
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desc->limit1 = (size >> 16) & 0xF; |
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desc->base2 = (addr >> 24) & 0xFF; |
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#ifdef CONFIG_X86_64 |
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desc->base3 = (u32) (addr >> 32); |
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#endif |
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} |
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static inline void __set_tss_desc(unsigned cpu, unsigned int entry, struct x86_hw_tss *addr) |
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{ |
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struct desc_struct *d = get_cpu_gdt_rw(cpu); |
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tss_desc tss; |
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set_tssldt_descriptor(&tss, (unsigned long)addr, DESC_TSS, |
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__KERNEL_TSS_LIMIT); |
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write_gdt_entry(d, entry, &tss, DESC_TSS); |
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} |
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#define set_tss_desc(cpu, addr) __set_tss_desc(cpu, GDT_ENTRY_TSS, addr) |
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static inline void native_set_ldt(const void *addr, unsigned int entries) |
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{ |
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if (likely(entries == 0)) |
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asm volatile("lldt %w0"::"q" (0)); |
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else { |
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unsigned cpu = smp_processor_id(); |
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ldt_desc ldt; |
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set_tssldt_descriptor(&ldt, (unsigned long)addr, DESC_LDT, |
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entries * LDT_ENTRY_SIZE - 1); |
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write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_LDT, |
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&ldt, DESC_LDT); |
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asm volatile("lldt %w0"::"q" (GDT_ENTRY_LDT*8)); |
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} |
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} |
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static inline void native_load_gdt(const struct desc_ptr *dtr) |
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{ |
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asm volatile("lgdt %0"::"m" (*dtr)); |
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} |
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static __always_inline void native_load_idt(const struct desc_ptr *dtr) |
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{ |
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asm volatile("lidt %0"::"m" (*dtr)); |
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} |
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static inline void native_store_gdt(struct desc_ptr *dtr) |
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{ |
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asm volatile("sgdt %0":"=m" (*dtr)); |
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} |
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static inline void store_idt(struct desc_ptr *dtr) |
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{ |
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asm volatile("sidt %0":"=m" (*dtr)); |
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} |
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/* |
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* The LTR instruction marks the TSS GDT entry as busy. On 64-bit, the GDT is |
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* a read-only remapping. To prevent a page fault, the GDT is switched to the |
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* original writeable version when needed. |
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*/ |
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#ifdef CONFIG_X86_64 |
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static inline void native_load_tr_desc(void) |
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{ |
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struct desc_ptr gdt; |
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int cpu = raw_smp_processor_id(); |
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bool restore = 0; |
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struct desc_struct *fixmap_gdt; |
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native_store_gdt(&gdt); |
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fixmap_gdt = get_cpu_gdt_ro(cpu); |
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/* |
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* If the current GDT is the read-only fixmap, swap to the original |
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* writeable version. Swap back at the end. |
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*/ |
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if (gdt.address == (unsigned long)fixmap_gdt) { |
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load_direct_gdt(cpu); |
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restore = 1; |
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} |
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asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8)); |
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if (restore) |
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load_fixmap_gdt(cpu); |
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} |
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#else |
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static inline void native_load_tr_desc(void) |
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{ |
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asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8)); |
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} |
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#endif |
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static inline unsigned long native_store_tr(void) |
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{ |
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unsigned long tr; |
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asm volatile("str %0":"=r" (tr)); |
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return tr; |
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} |
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static inline void native_load_tls(struct thread_struct *t, unsigned int cpu) |
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{ |
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struct desc_struct *gdt = get_cpu_gdt_rw(cpu); |
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unsigned int i; |
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for (i = 0; i < GDT_ENTRY_TLS_ENTRIES; i++) |
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gdt[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i]; |
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} |
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DECLARE_PER_CPU(bool, __tss_limit_invalid); |
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static inline void force_reload_TR(void) |
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{ |
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struct desc_struct *d = get_current_gdt_rw(); |
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tss_desc tss; |
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memcpy(&tss, &d[GDT_ENTRY_TSS], sizeof(tss_desc)); |
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/* |
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* LTR requires an available TSS, and the TSS is currently |
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* busy. Make it be available so that LTR will work. |
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*/ |
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tss.type = DESC_TSS; |
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write_gdt_entry(d, GDT_ENTRY_TSS, &tss, DESC_TSS); |
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load_TR_desc(); |
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this_cpu_write(__tss_limit_invalid, false); |
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} |
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/* |
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* Call this if you need the TSS limit to be correct, which should be the case |
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* if and only if you have TIF_IO_BITMAP set or you're switching to a task |
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* with TIF_IO_BITMAP set. |
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*/ |
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static inline void refresh_tss_limit(void) |
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{ |
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DEBUG_LOCKS_WARN_ON(preemptible()); |
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if (unlikely(this_cpu_read(__tss_limit_invalid))) |
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force_reload_TR(); |
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} |
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/* |
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* If you do something evil that corrupts the cached TSS limit (I'm looking |
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* at you, VMX exits), call this function. |
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* |
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* The optimization here is that the TSS limit only matters for Linux if the |
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* IO bitmap is in use. If the TSS limit gets forced to its minimum value, |
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* everything works except that IO bitmap will be ignored and all CPL 3 IO |
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* instructions will #GP, which is exactly what we want for normal tasks. |
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*/ |
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static inline void invalidate_tss_limit(void) |
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{ |
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DEBUG_LOCKS_WARN_ON(preemptible()); |
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if (unlikely(test_thread_flag(TIF_IO_BITMAP))) |
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force_reload_TR(); |
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else |
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this_cpu_write(__tss_limit_invalid, true); |
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} |
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/* This intentionally ignores lm, since 32-bit apps don't have that field. */ |
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#define LDT_empty(info) \ |
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((info)->base_addr == 0 && \ |
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(info)->limit == 0 && \ |
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(info)->contents == 0 && \ |
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(info)->read_exec_only == 1 && \ |
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(info)->seg_32bit == 0 && \ |
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(info)->limit_in_pages == 0 && \ |
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(info)->seg_not_present == 1 && \ |
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(info)->useable == 0) |
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/* Lots of programs expect an all-zero user_desc to mean "no segment at all". */ |
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static inline bool LDT_zero(const struct user_desc *info) |
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{ |
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return (info->base_addr == 0 && |
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info->limit == 0 && |
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info->contents == 0 && |
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info->read_exec_only == 0 && |
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info->seg_32bit == 0 && |
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info->limit_in_pages == 0 && |
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info->seg_not_present == 0 && |
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info->useable == 0); |
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} |
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static inline void clear_LDT(void) |
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{ |
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set_ldt(NULL, 0); |
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} |
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static inline unsigned long get_desc_base(const struct desc_struct *desc) |
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{ |
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return (unsigned)(desc->base0 | ((desc->base1) << 16) | ((desc->base2) << 24)); |
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} |
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static inline void set_desc_base(struct desc_struct *desc, unsigned long base) |
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{ |
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desc->base0 = base & 0xffff; |
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desc->base1 = (base >> 16) & 0xff; |
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desc->base2 = (base >> 24) & 0xff; |
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} |
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static inline unsigned long get_desc_limit(const struct desc_struct *desc) |
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{ |
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return desc->limit0 | (desc->limit1 << 16); |
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} |
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static inline void set_desc_limit(struct desc_struct *desc, unsigned long limit) |
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{ |
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desc->limit0 = limit & 0xffff; |
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desc->limit1 = (limit >> 16) & 0xf; |
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} |
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void alloc_intr_gate(unsigned int n, const void *addr); |
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static inline void init_idt_data(struct idt_data *data, unsigned int n, |
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const void *addr) |
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{ |
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BUG_ON(n > 0xFF); |
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memset(data, 0, sizeof(*data)); |
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data->vector = n; |
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data->addr = addr; |
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data->segment = __KERNEL_CS; |
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data->bits.type = GATE_INTERRUPT; |
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data->bits.p = 1; |
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} |
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static inline void idt_init_desc(gate_desc *gate, const struct idt_data *d) |
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{ |
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unsigned long addr = (unsigned long) d->addr; |
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gate->offset_low = (u16) addr; |
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gate->segment = (u16) d->segment; |
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gate->bits = d->bits; |
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gate->offset_middle = (u16) (addr >> 16); |
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#ifdef CONFIG_X86_64 |
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gate->offset_high = (u32) (addr >> 32); |
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gate->reserved = 0; |
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#endif |
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} |
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extern unsigned long system_vectors[]; |
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extern void load_current_idt(void); |
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extern void idt_setup_early_handler(void); |
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extern void idt_setup_early_traps(void); |
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extern void idt_setup_traps(void); |
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extern void idt_setup_apic_and_irq_gates(void); |
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extern bool idt_is_f00f_address(unsigned long address); |
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#ifdef CONFIG_X86_64 |
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extern void idt_setup_early_pf(void); |
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extern void idt_setup_ist_traps(void); |
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#else |
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static inline void idt_setup_early_pf(void) { } |
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static inline void idt_setup_ist_traps(void) { } |
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#endif |
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extern void idt_invalidate(void *addr); |
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#endif /* _ASM_X86_DESC_H */
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