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400 lines
9.9 KiB
400 lines
9.9 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#ifndef _ASM_X86_BITOPS_H |
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#define _ASM_X86_BITOPS_H |
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/* |
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* Copyright 1992, Linus Torvalds. |
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* |
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* Note: inlines with more than a single statement should be marked |
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* __always_inline to avoid problems with older gcc's inlining heuristics. |
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*/ |
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#ifndef _LINUX_BITOPS_H |
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#error only <linux/bitops.h> can be included directly |
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#endif |
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#include <linux/compiler.h> |
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#include <asm/alternative.h> |
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#include <asm/rmwcc.h> |
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#include <asm/barrier.h> |
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#if BITS_PER_LONG == 32 |
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# define _BITOPS_LONG_SHIFT 5 |
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#elif BITS_PER_LONG == 64 |
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# define _BITOPS_LONG_SHIFT 6 |
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#else |
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# error "Unexpected BITS_PER_LONG" |
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#endif |
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#define BIT_64(n) (U64_C(1) << (n)) |
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/* |
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* These have to be done with inline assembly: that way the bit-setting |
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* is guaranteed to be atomic. All bit operations return 0 if the bit |
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* was cleared before the operation and != 0 if it was not. |
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* |
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* bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1). |
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*/ |
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#define RLONG_ADDR(x) "m" (*(volatile long *) (x)) |
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#define WBYTE_ADDR(x) "+m" (*(volatile char *) (x)) |
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#define ADDR RLONG_ADDR(addr) |
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/* |
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* We do the locked ops that don't return the old value as |
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* a mask operation on a byte. |
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*/ |
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#define CONST_MASK_ADDR(nr, addr) WBYTE_ADDR((void *)(addr) + ((nr)>>3)) |
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#define CONST_MASK(nr) (1 << ((nr) & 7)) |
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static __always_inline void |
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arch_set_bit(long nr, volatile unsigned long *addr) |
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{ |
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if (__builtin_constant_p(nr)) { |
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asm volatile(LOCK_PREFIX "orb %b1,%0" |
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: CONST_MASK_ADDR(nr, addr) |
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: "iq" (CONST_MASK(nr)) |
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: "memory"); |
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} else { |
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asm volatile(LOCK_PREFIX __ASM_SIZE(bts) " %1,%0" |
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: : RLONG_ADDR(addr), "Ir" (nr) : "memory"); |
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} |
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} |
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static __always_inline void |
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arch___set_bit(long nr, volatile unsigned long *addr) |
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{ |
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asm volatile(__ASM_SIZE(bts) " %1,%0" : : ADDR, "Ir" (nr) : "memory"); |
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} |
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static __always_inline void |
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arch_clear_bit(long nr, volatile unsigned long *addr) |
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{ |
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if (__builtin_constant_p(nr)) { |
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asm volatile(LOCK_PREFIX "andb %b1,%0" |
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: CONST_MASK_ADDR(nr, addr) |
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: "iq" (~CONST_MASK(nr))); |
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} else { |
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asm volatile(LOCK_PREFIX __ASM_SIZE(btr) " %1,%0" |
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: : RLONG_ADDR(addr), "Ir" (nr) : "memory"); |
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} |
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} |
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static __always_inline void |
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arch_clear_bit_unlock(long nr, volatile unsigned long *addr) |
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{ |
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barrier(); |
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arch_clear_bit(nr, addr); |
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} |
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static __always_inline void |
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arch___clear_bit(long nr, volatile unsigned long *addr) |
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{ |
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asm volatile(__ASM_SIZE(btr) " %1,%0" : : ADDR, "Ir" (nr) : "memory"); |
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} |
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static __always_inline bool |
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arch_clear_bit_unlock_is_negative_byte(long nr, volatile unsigned long *addr) |
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{ |
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bool negative; |
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asm volatile(LOCK_PREFIX "andb %2,%1" |
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CC_SET(s) |
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: CC_OUT(s) (negative), WBYTE_ADDR(addr) |
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: "ir" ((char) ~(1 << nr)) : "memory"); |
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return negative; |
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} |
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#define arch_clear_bit_unlock_is_negative_byte \ |
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arch_clear_bit_unlock_is_negative_byte |
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static __always_inline void |
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arch___clear_bit_unlock(long nr, volatile unsigned long *addr) |
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{ |
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arch___clear_bit(nr, addr); |
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} |
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static __always_inline void |
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arch___change_bit(long nr, volatile unsigned long *addr) |
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{ |
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asm volatile(__ASM_SIZE(btc) " %1,%0" : : ADDR, "Ir" (nr) : "memory"); |
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} |
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static __always_inline void |
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arch_change_bit(long nr, volatile unsigned long *addr) |
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{ |
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if (__builtin_constant_p(nr)) { |
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asm volatile(LOCK_PREFIX "xorb %b1,%0" |
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: CONST_MASK_ADDR(nr, addr) |
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: "iq" (CONST_MASK(nr))); |
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} else { |
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asm volatile(LOCK_PREFIX __ASM_SIZE(btc) " %1,%0" |
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: : RLONG_ADDR(addr), "Ir" (nr) : "memory"); |
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} |
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} |
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static __always_inline bool |
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arch_test_and_set_bit(long nr, volatile unsigned long *addr) |
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{ |
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return GEN_BINARY_RMWcc(LOCK_PREFIX __ASM_SIZE(bts), *addr, c, "Ir", nr); |
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} |
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static __always_inline bool |
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arch_test_and_set_bit_lock(long nr, volatile unsigned long *addr) |
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{ |
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return arch_test_and_set_bit(nr, addr); |
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} |
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static __always_inline bool |
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arch___test_and_set_bit(long nr, volatile unsigned long *addr) |
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{ |
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bool oldbit; |
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asm(__ASM_SIZE(bts) " %2,%1" |
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CC_SET(c) |
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: CC_OUT(c) (oldbit) |
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: ADDR, "Ir" (nr) : "memory"); |
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return oldbit; |
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} |
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static __always_inline bool |
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arch_test_and_clear_bit(long nr, volatile unsigned long *addr) |
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{ |
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return GEN_BINARY_RMWcc(LOCK_PREFIX __ASM_SIZE(btr), *addr, c, "Ir", nr); |
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} |
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/* |
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* Note: the operation is performed atomically with respect to |
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* the local CPU, but not other CPUs. Portable code should not |
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* rely on this behaviour. |
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* KVM relies on this behaviour on x86 for modifying memory that is also |
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* accessed from a hypervisor on the same CPU if running in a VM: don't change |
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* this without also updating arch/x86/kernel/kvm.c |
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*/ |
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static __always_inline bool |
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arch___test_and_clear_bit(long nr, volatile unsigned long *addr) |
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{ |
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bool oldbit; |
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asm volatile(__ASM_SIZE(btr) " %2,%1" |
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CC_SET(c) |
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: CC_OUT(c) (oldbit) |
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: ADDR, "Ir" (nr) : "memory"); |
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return oldbit; |
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} |
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static __always_inline bool |
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arch___test_and_change_bit(long nr, volatile unsigned long *addr) |
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{ |
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bool oldbit; |
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asm volatile(__ASM_SIZE(btc) " %2,%1" |
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CC_SET(c) |
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: CC_OUT(c) (oldbit) |
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: ADDR, "Ir" (nr) : "memory"); |
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return oldbit; |
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} |
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static __always_inline bool |
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arch_test_and_change_bit(long nr, volatile unsigned long *addr) |
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{ |
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return GEN_BINARY_RMWcc(LOCK_PREFIX __ASM_SIZE(btc), *addr, c, "Ir", nr); |
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} |
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static __always_inline bool constant_test_bit(long nr, const volatile unsigned long *addr) |
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{ |
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return ((1UL << (nr & (BITS_PER_LONG-1))) & |
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(addr[nr >> _BITOPS_LONG_SHIFT])) != 0; |
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} |
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static __always_inline bool variable_test_bit(long nr, volatile const unsigned long *addr) |
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{ |
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bool oldbit; |
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asm volatile(__ASM_SIZE(bt) " %2,%1" |
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CC_SET(c) |
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: CC_OUT(c) (oldbit) |
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: "m" (*(unsigned long *)addr), "Ir" (nr) : "memory"); |
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return oldbit; |
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} |
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#define arch_test_bit(nr, addr) \ |
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(__builtin_constant_p((nr)) \ |
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? constant_test_bit((nr), (addr)) \ |
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: variable_test_bit((nr), (addr))) |
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/** |
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* __ffs - find first set bit in word |
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* @word: The word to search |
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* |
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* Undefined if no bit exists, so code should check against 0 first. |
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*/ |
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static __always_inline unsigned long __ffs(unsigned long word) |
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{ |
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asm("rep; bsf %1,%0" |
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: "=r" (word) |
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: "rm" (word)); |
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return word; |
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} |
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/** |
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* ffz - find first zero bit in word |
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* @word: The word to search |
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* |
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* Undefined if no zero exists, so code should check against ~0UL first. |
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*/ |
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static __always_inline unsigned long ffz(unsigned long word) |
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{ |
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asm("rep; bsf %1,%0" |
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: "=r" (word) |
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: "r" (~word)); |
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return word; |
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} |
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/* |
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* __fls: find last set bit in word |
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* @word: The word to search |
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* |
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* Undefined if no set bit exists, so code should check against 0 first. |
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*/ |
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static __always_inline unsigned long __fls(unsigned long word) |
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{ |
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asm("bsr %1,%0" |
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: "=r" (word) |
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: "rm" (word)); |
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return word; |
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} |
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#undef ADDR |
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#ifdef __KERNEL__ |
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/** |
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* ffs - find first set bit in word |
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* @x: the word to search |
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* |
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* This is defined the same way as the libc and compiler builtin ffs |
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* routines, therefore differs in spirit from the other bitops. |
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* |
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* ffs(value) returns 0 if value is 0 or the position of the first |
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* set bit if value is nonzero. The first (least significant) bit |
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* is at position 1. |
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*/ |
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static __always_inline int ffs(int x) |
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{ |
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int r; |
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#ifdef CONFIG_X86_64 |
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/* |
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* AMD64 says BSFL won't clobber the dest reg if x==0; Intel64 says the |
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* dest reg is undefined if x==0, but their CPU architect says its |
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* value is written to set it to the same as before, except that the |
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* top 32 bits will be cleared. |
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* |
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* We cannot do this on 32 bits because at the very least some |
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* 486 CPUs did not behave this way. |
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*/ |
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asm("bsfl %1,%0" |
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: "=r" (r) |
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: "rm" (x), "0" (-1)); |
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#elif defined(CONFIG_X86_CMOV) |
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asm("bsfl %1,%0\n\t" |
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"cmovzl %2,%0" |
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: "=&r" (r) : "rm" (x), "r" (-1)); |
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#else |
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asm("bsfl %1,%0\n\t" |
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"jnz 1f\n\t" |
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"movl $-1,%0\n" |
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"1:" : "=r" (r) : "rm" (x)); |
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#endif |
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return r + 1; |
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} |
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/** |
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* fls - find last set bit in word |
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* @x: the word to search |
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* |
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* This is defined in a similar way as the libc and compiler builtin |
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* ffs, but returns the position of the most significant set bit. |
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* |
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* fls(value) returns 0 if value is 0 or the position of the last |
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* set bit if value is nonzero. The last (most significant) bit is |
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* at position 32. |
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*/ |
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static __always_inline int fls(unsigned int x) |
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{ |
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int r; |
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#ifdef CONFIG_X86_64 |
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/* |
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* AMD64 says BSRL won't clobber the dest reg if x==0; Intel64 says the |
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* dest reg is undefined if x==0, but their CPU architect says its |
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* value is written to set it to the same as before, except that the |
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* top 32 bits will be cleared. |
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* |
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* We cannot do this on 32 bits because at the very least some |
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* 486 CPUs did not behave this way. |
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*/ |
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asm("bsrl %1,%0" |
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: "=r" (r) |
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: "rm" (x), "0" (-1)); |
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#elif defined(CONFIG_X86_CMOV) |
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asm("bsrl %1,%0\n\t" |
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"cmovzl %2,%0" |
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: "=&r" (r) : "rm" (x), "rm" (-1)); |
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#else |
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asm("bsrl %1,%0\n\t" |
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"jnz 1f\n\t" |
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"movl $-1,%0\n" |
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"1:" : "=r" (r) : "rm" (x)); |
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#endif |
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return r + 1; |
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} |
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/** |
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* fls64 - find last set bit in a 64-bit word |
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* @x: the word to search |
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* |
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* This is defined in a similar way as the libc and compiler builtin |
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* ffsll, but returns the position of the most significant set bit. |
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* |
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* fls64(value) returns 0 if value is 0 or the position of the last |
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* set bit if value is nonzero. The last (most significant) bit is |
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* at position 64. |
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*/ |
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#ifdef CONFIG_X86_64 |
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static __always_inline int fls64(__u64 x) |
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{ |
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int bitpos = -1; |
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/* |
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* AMD64 says BSRQ won't clobber the dest reg if x==0; Intel64 says the |
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* dest reg is undefined if x==0, but their CPU architect says its |
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* value is written to set it to the same as before. |
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*/ |
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asm("bsrq %1,%q0" |
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: "+r" (bitpos) |
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: "rm" (x)); |
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return bitpos + 1; |
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} |
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#else |
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#include <asm-generic/bitops/fls64.h> |
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#endif |
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#include <asm-generic/bitops/find.h> |
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#include <asm-generic/bitops/sched.h> |
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#include <asm/arch_hweight.h> |
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#include <asm-generic/bitops/const_hweight.h> |
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#include <asm-generic/bitops/instrumented-atomic.h> |
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#include <asm-generic/bitops/instrumented-non-atomic.h> |
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#include <asm-generic/bitops/instrumented-lock.h> |
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#include <asm-generic/bitops/le.h> |
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#include <asm-generic/bitops/ext2-atomic-setbit.h> |
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#endif /* __KERNEL__ */ |
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#endif /* _ASM_X86_BITOPS_H */
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