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132 lines
3.3 KiB
132 lines
3.3 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Intel(R) Processor Trace PMU driver for perf |
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* Copyright (c) 2013-2014, Intel Corporation. |
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* |
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* Intel PT is specified in the Intel Architecture Instruction Set Extensions |
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* Programming Reference: |
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* http://software.intel.com/en-us/intel-isa-extensions |
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*/ |
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#ifndef __INTEL_PT_H__ |
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#define __INTEL_PT_H__ |
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/* |
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* Single-entry ToPA: when this close to region boundary, switch |
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* buffers to avoid losing data. |
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*/ |
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#define TOPA_PMI_MARGIN 512 |
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#define TOPA_SHIFT 12 |
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static inline unsigned int sizes(unsigned int tsz) |
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{ |
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return 1 << (tsz + TOPA_SHIFT); |
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}; |
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struct topa_entry { |
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u64 end : 1; |
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u64 rsvd0 : 1; |
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u64 intr : 1; |
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u64 rsvd1 : 1; |
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u64 stop : 1; |
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u64 rsvd2 : 1; |
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u64 size : 4; |
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u64 rsvd3 : 2; |
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u64 base : 36; |
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u64 rsvd4 : 16; |
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}; |
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/* TSC to Core Crystal Clock Ratio */ |
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#define CPUID_TSC_LEAF 0x15 |
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struct pt_pmu { |
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struct pmu pmu; |
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u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES]; |
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bool vmx; |
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bool branch_en_always_on; |
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unsigned long max_nonturbo_ratio; |
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unsigned int tsc_art_num; |
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unsigned int tsc_art_den; |
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}; |
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/** |
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* struct pt_buffer - buffer configuration; one buffer per task_struct or |
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* cpu, depending on perf event configuration |
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* @tables: list of ToPA tables in this buffer |
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* @first: shorthand for first topa table |
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* @last: shorthand for last topa table |
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* @cur: current topa table |
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* @nr_pages: buffer size in pages |
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* @cur_idx: current output region's index within @cur table |
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* @output_off: offset within the current output region |
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* @data_size: running total of the amount of data in this buffer |
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* @lost: if data was lost/truncated |
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* @head: logical write offset inside the buffer |
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* @snapshot: if this is for a snapshot/overwrite counter |
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* @single: use Single Range Output instead of ToPA |
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* @stop_pos: STOP topa entry index |
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* @intr_pos: INT topa entry index |
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* @stop_te: STOP topa entry pointer |
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* @intr_te: INT topa entry pointer |
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* @data_pages: array of pages from perf |
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* @topa_index: table of topa entries indexed by page offset |
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*/ |
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struct pt_buffer { |
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struct list_head tables; |
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struct topa *first, *last, *cur; |
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unsigned int cur_idx; |
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size_t output_off; |
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unsigned long nr_pages; |
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local_t data_size; |
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local64_t head; |
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bool snapshot; |
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bool single; |
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long stop_pos, intr_pos; |
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struct topa_entry *stop_te, *intr_te; |
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void **data_pages; |
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}; |
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#define PT_FILTERS_NUM 4 |
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/** |
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* struct pt_filter - IP range filter configuration |
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* @msr_a: range start, goes to RTIT_ADDRn_A |
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* @msr_b: range end, goes to RTIT_ADDRn_B |
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* @config: 4-bit field in RTIT_CTL |
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*/ |
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struct pt_filter { |
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unsigned long msr_a; |
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unsigned long msr_b; |
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unsigned long config; |
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}; |
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/** |
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* struct pt_filters - IP range filtering context |
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* @filter: filters defined for this context |
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* @nr_filters: number of defined filters in the @filter array |
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*/ |
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struct pt_filters { |
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struct pt_filter filter[PT_FILTERS_NUM]; |
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unsigned int nr_filters; |
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}; |
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/** |
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* struct pt - per-cpu pt context |
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* @handle: perf output handle |
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* @filters: last configured filters |
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* @handle_nmi: do handle PT PMI on this cpu, there's an active event |
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* @vmx_on: 1 if VMX is ON on this cpu |
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* @output_base: cached RTIT_OUTPUT_BASE MSR value |
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* @output_mask: cached RTIT_OUTPUT_MASK MSR value |
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*/ |
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struct pt { |
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struct perf_output_handle handle; |
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struct pt_filters filters; |
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int handle_nmi; |
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int vmx_on; |
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u64 output_base; |
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u64 output_mask; |
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}; |
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#endif /* __INTEL_PT_H__ */
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