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250 lines
6.1 KiB
250 lines
6.1 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Using hardware provided CRC32 instruction to accelerate the CRC32 disposal. |
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* CRC32C polynomial:0x1EDC6F41(BE)/0x82F63B78(LE) |
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* CRC32 is a new instruction in Intel SSE4.2, the reference can be found at: |
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* http://www.intel.com/products/processor/manuals/ |
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* Intel(R) 64 and IA-32 Architectures Software Developer's Manual |
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* Volume 2A: Instruction Set Reference, A-M |
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* |
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* Copyright (C) 2008 Intel Corporation |
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* Authors: Austin Zhang <[email protected]> |
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* Kent Liu <[email protected]> |
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*/ |
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#include <linux/init.h> |
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#include <linux/module.h> |
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#include <linux/string.h> |
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#include <linux/kernel.h> |
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#include <crypto/internal/hash.h> |
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#include <crypto/internal/simd.h> |
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#include <asm/cpufeatures.h> |
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#include <asm/cpu_device_id.h> |
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#include <asm/simd.h> |
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#define CHKSUM_BLOCK_SIZE 1 |
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#define CHKSUM_DIGEST_SIZE 4 |
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#define SCALE_F sizeof(unsigned long) |
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#ifdef CONFIG_X86_64 |
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#define CRC32_INST "crc32q %1, %q0" |
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#else |
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#define CRC32_INST "crc32l %1, %0" |
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#endif |
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#ifdef CONFIG_X86_64 |
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/* |
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* use carryless multiply version of crc32c when buffer |
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* size is >= 512 to account |
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* for fpu state save/restore overhead. |
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*/ |
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#define CRC32C_PCL_BREAKEVEN 512 |
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asmlinkage unsigned int crc_pcl(const u8 *buffer, int len, |
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unsigned int crc_init); |
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#endif /* CONFIG_X86_64 */ |
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static u32 crc32c_intel_le_hw_byte(u32 crc, unsigned char const *data, size_t length) |
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{ |
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while (length--) { |
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asm("crc32b %1, %0" |
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: "+r" (crc) : "rm" (*data)); |
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data++; |
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} |
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return crc; |
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} |
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static u32 __pure crc32c_intel_le_hw(u32 crc, unsigned char const *p, size_t len) |
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{ |
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unsigned int iquotient = len / SCALE_F; |
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unsigned int iremainder = len % SCALE_F; |
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unsigned long *ptmp = (unsigned long *)p; |
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while (iquotient--) { |
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asm(CRC32_INST |
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: "+r" (crc) : "rm" (*ptmp)); |
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ptmp++; |
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} |
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if (iremainder) |
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crc = crc32c_intel_le_hw_byte(crc, (unsigned char *)ptmp, |
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iremainder); |
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return crc; |
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} |
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/* |
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* Setting the seed allows arbitrary accumulators and flexible XOR policy |
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* If your algorithm starts with ~0, then XOR with ~0 before you set |
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* the seed. |
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*/ |
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static int crc32c_intel_setkey(struct crypto_shash *hash, const u8 *key, |
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unsigned int keylen) |
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{ |
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u32 *mctx = crypto_shash_ctx(hash); |
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if (keylen != sizeof(u32)) |
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return -EINVAL; |
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*mctx = le32_to_cpup((__le32 *)key); |
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return 0; |
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} |
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static int crc32c_intel_init(struct shash_desc *desc) |
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{ |
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u32 *mctx = crypto_shash_ctx(desc->tfm); |
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u32 *crcp = shash_desc_ctx(desc); |
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*crcp = *mctx; |
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return 0; |
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} |
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static int crc32c_intel_update(struct shash_desc *desc, const u8 *data, |
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unsigned int len) |
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{ |
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u32 *crcp = shash_desc_ctx(desc); |
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*crcp = crc32c_intel_le_hw(*crcp, data, len); |
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return 0; |
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} |
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static int __crc32c_intel_finup(u32 *crcp, const u8 *data, unsigned int len, |
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u8 *out) |
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{ |
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*(__le32 *)out = ~cpu_to_le32(crc32c_intel_le_hw(*crcp, data, len)); |
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return 0; |
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} |
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static int crc32c_intel_finup(struct shash_desc *desc, const u8 *data, |
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unsigned int len, u8 *out) |
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{ |
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return __crc32c_intel_finup(shash_desc_ctx(desc), data, len, out); |
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} |
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static int crc32c_intel_final(struct shash_desc *desc, u8 *out) |
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{ |
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u32 *crcp = shash_desc_ctx(desc); |
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*(__le32 *)out = ~cpu_to_le32p(crcp); |
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return 0; |
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} |
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static int crc32c_intel_digest(struct shash_desc *desc, const u8 *data, |
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unsigned int len, u8 *out) |
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{ |
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return __crc32c_intel_finup(crypto_shash_ctx(desc->tfm), data, len, |
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out); |
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} |
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static int crc32c_intel_cra_init(struct crypto_tfm *tfm) |
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{ |
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u32 *key = crypto_tfm_ctx(tfm); |
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*key = ~0; |
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return 0; |
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} |
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#ifdef CONFIG_X86_64 |
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static int crc32c_pcl_intel_update(struct shash_desc *desc, const u8 *data, |
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unsigned int len) |
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{ |
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u32 *crcp = shash_desc_ctx(desc); |
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/* |
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* use faster PCL version if datasize is large enough to |
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* overcome kernel fpu state save/restore overhead |
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*/ |
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if (len >= CRC32C_PCL_BREAKEVEN && crypto_simd_usable()) { |
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kernel_fpu_begin(); |
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*crcp = crc_pcl(data, len, *crcp); |
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kernel_fpu_end(); |
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} else |
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*crcp = crc32c_intel_le_hw(*crcp, data, len); |
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return 0; |
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} |
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static int __crc32c_pcl_intel_finup(u32 *crcp, const u8 *data, unsigned int len, |
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u8 *out) |
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{ |
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if (len >= CRC32C_PCL_BREAKEVEN && crypto_simd_usable()) { |
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kernel_fpu_begin(); |
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*(__le32 *)out = ~cpu_to_le32(crc_pcl(data, len, *crcp)); |
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kernel_fpu_end(); |
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} else |
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*(__le32 *)out = |
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~cpu_to_le32(crc32c_intel_le_hw(*crcp, data, len)); |
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return 0; |
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} |
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static int crc32c_pcl_intel_finup(struct shash_desc *desc, const u8 *data, |
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unsigned int len, u8 *out) |
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{ |
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return __crc32c_pcl_intel_finup(shash_desc_ctx(desc), data, len, out); |
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} |
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static int crc32c_pcl_intel_digest(struct shash_desc *desc, const u8 *data, |
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unsigned int len, u8 *out) |
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{ |
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return __crc32c_pcl_intel_finup(crypto_shash_ctx(desc->tfm), data, len, |
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out); |
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} |
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#endif /* CONFIG_X86_64 */ |
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static struct shash_alg alg = { |
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.setkey = crc32c_intel_setkey, |
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.init = crc32c_intel_init, |
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.update = crc32c_intel_update, |
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.final = crc32c_intel_final, |
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.finup = crc32c_intel_finup, |
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.digest = crc32c_intel_digest, |
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.descsize = sizeof(u32), |
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.digestsize = CHKSUM_DIGEST_SIZE, |
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.base = { |
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.cra_name = "crc32c", |
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.cra_driver_name = "crc32c-intel", |
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.cra_priority = 200, |
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.cra_flags = CRYPTO_ALG_OPTIONAL_KEY, |
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.cra_blocksize = CHKSUM_BLOCK_SIZE, |
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.cra_ctxsize = sizeof(u32), |
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.cra_module = THIS_MODULE, |
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.cra_init = crc32c_intel_cra_init, |
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} |
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}; |
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static const struct x86_cpu_id crc32c_cpu_id[] = { |
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X86_MATCH_FEATURE(X86_FEATURE_XMM4_2, NULL), |
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{} |
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}; |
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MODULE_DEVICE_TABLE(x86cpu, crc32c_cpu_id); |
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static int __init crc32c_intel_mod_init(void) |
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{ |
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if (!x86_match_cpu(crc32c_cpu_id)) |
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return -ENODEV; |
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#ifdef CONFIG_X86_64 |
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if (boot_cpu_has(X86_FEATURE_PCLMULQDQ)) { |
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alg.update = crc32c_pcl_intel_update; |
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alg.finup = crc32c_pcl_intel_finup; |
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alg.digest = crc32c_pcl_intel_digest; |
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} |
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#endif |
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return crypto_register_shash(&alg); |
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} |
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static void __exit crc32c_intel_mod_fini(void) |
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{ |
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crypto_unregister_shash(&alg); |
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} |
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module_init(crc32c_intel_mod_init); |
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module_exit(crc32c_intel_mod_fini); |
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MODULE_AUTHOR("Austin Zhang <[email protected]>, Kent Liu <[email protected]>"); |
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MODULE_DESCRIPTION("CRC32c (Castagnoli) optimization using Intel Hardware."); |
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MODULE_LICENSE("GPL"); |
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MODULE_ALIAS_CRYPTO("crc32c"); |
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MODULE_ALIAS_CRYPTO("crc32c-intel");
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