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867 lines
22 KiB
867 lines
22 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* The file intends to implement PE based on the information from |
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* platforms. Basically, there have 3 types of PEs: PHB/Bus/Device. |
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* All the PEs should be organized as hierarchy tree. The first level |
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* of the tree will be associated to existing PHBs since the particular |
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* PE is only meaningful in one PHB domain. |
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* |
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* Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2012. |
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*/ |
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|
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#include <linux/delay.h> |
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#include <linux/export.h> |
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#include <linux/gfp.h> |
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#include <linux/kernel.h> |
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#include <linux/pci.h> |
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#include <linux/string.h> |
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|
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#include <asm/pci-bridge.h> |
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#include <asm/ppc-pci.h> |
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|
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static int eeh_pe_aux_size = 0; |
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static LIST_HEAD(eeh_phb_pe); |
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|
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/** |
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* eeh_set_pe_aux_size - Set PE auxillary data size |
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* @size: PE auxillary data size |
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* |
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* Set PE auxillary data size |
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*/ |
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void eeh_set_pe_aux_size(int size) |
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{ |
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if (size < 0) |
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return; |
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|
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eeh_pe_aux_size = size; |
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} |
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|
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/** |
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* eeh_pe_alloc - Allocate PE |
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* @phb: PCI controller |
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* @type: PE type |
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* |
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* Allocate PE instance dynamically. |
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*/ |
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static struct eeh_pe *eeh_pe_alloc(struct pci_controller *phb, int type) |
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{ |
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struct eeh_pe *pe; |
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size_t alloc_size; |
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|
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alloc_size = sizeof(struct eeh_pe); |
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if (eeh_pe_aux_size) { |
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alloc_size = ALIGN(alloc_size, cache_line_size()); |
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alloc_size += eeh_pe_aux_size; |
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} |
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|
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/* Allocate PHB PE */ |
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pe = kzalloc(alloc_size, GFP_KERNEL); |
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if (!pe) return NULL; |
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|
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/* Initialize PHB PE */ |
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pe->type = type; |
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pe->phb = phb; |
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INIT_LIST_HEAD(&pe->child_list); |
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INIT_LIST_HEAD(&pe->edevs); |
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|
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pe->data = (void *)pe + ALIGN(sizeof(struct eeh_pe), |
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cache_line_size()); |
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return pe; |
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} |
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|
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/** |
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* eeh_phb_pe_create - Create PHB PE |
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* @phb: PCI controller |
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* |
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* The function should be called while the PHB is detected during |
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* system boot or PCI hotplug in order to create PHB PE. |
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*/ |
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int eeh_phb_pe_create(struct pci_controller *phb) |
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{ |
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struct eeh_pe *pe; |
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|
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/* Allocate PHB PE */ |
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pe = eeh_pe_alloc(phb, EEH_PE_PHB); |
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if (!pe) { |
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pr_err("%s: out of memory!\n", __func__); |
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return -ENOMEM; |
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} |
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|
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/* Put it into the list */ |
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list_add_tail(&pe->child, &eeh_phb_pe); |
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|
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pr_debug("EEH: Add PE for PHB#%x\n", phb->global_number); |
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|
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return 0; |
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} |
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|
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/** |
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* eeh_wait_state - Wait for PE state |
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* @pe: EEH PE |
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* @max_wait: maximal period in millisecond |
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* |
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* Wait for the state of associated PE. It might take some time |
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* to retrieve the PE's state. |
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*/ |
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int eeh_wait_state(struct eeh_pe *pe, int max_wait) |
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{ |
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int ret; |
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int mwait; |
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|
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/* |
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* According to PAPR, the state of PE might be temporarily |
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* unavailable. Under the circumstance, we have to wait |
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* for indicated time determined by firmware. The maximal |
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* wait time is 5 minutes, which is acquired from the original |
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* EEH implementation. Also, the original implementation |
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* also defined the minimal wait time as 1 second. |
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*/ |
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#define EEH_STATE_MIN_WAIT_TIME (1000) |
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#define EEH_STATE_MAX_WAIT_TIME (300 * 1000) |
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|
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while (1) { |
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ret = eeh_ops->get_state(pe, &mwait); |
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|
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if (ret != EEH_STATE_UNAVAILABLE) |
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return ret; |
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|
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if (max_wait <= 0) { |
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pr_warn("%s: Timeout when getting PE's state (%d)\n", |
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__func__, max_wait); |
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return EEH_STATE_NOT_SUPPORT; |
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} |
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|
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if (mwait < EEH_STATE_MIN_WAIT_TIME) { |
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pr_warn("%s: Firmware returned bad wait value %d\n", |
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__func__, mwait); |
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mwait = EEH_STATE_MIN_WAIT_TIME; |
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} else if (mwait > EEH_STATE_MAX_WAIT_TIME) { |
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pr_warn("%s: Firmware returned too long wait value %d\n", |
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__func__, mwait); |
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mwait = EEH_STATE_MAX_WAIT_TIME; |
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} |
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|
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msleep(min(mwait, max_wait)); |
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max_wait -= mwait; |
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} |
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} |
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|
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/** |
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* eeh_phb_pe_get - Retrieve PHB PE based on the given PHB |
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* @phb: PCI controller |
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* |
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* The overall PEs form hierarchy tree. The first layer of the |
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* hierarchy tree is composed of PHB PEs. The function is used |
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* to retrieve the corresponding PHB PE according to the given PHB. |
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*/ |
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struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb) |
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{ |
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struct eeh_pe *pe; |
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|
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list_for_each_entry(pe, &eeh_phb_pe, child) { |
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/* |
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* Actually, we needn't check the type since |
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* the PE for PHB has been determined when that |
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* was created. |
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*/ |
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if ((pe->type & EEH_PE_PHB) && pe->phb == phb) |
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return pe; |
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} |
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|
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return NULL; |
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} |
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|
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/** |
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* eeh_pe_next - Retrieve the next PE in the tree |
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* @pe: current PE |
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* @root: root PE |
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* |
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* The function is used to retrieve the next PE in the |
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* hierarchy PE tree. |
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*/ |
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struct eeh_pe *eeh_pe_next(struct eeh_pe *pe, struct eeh_pe *root) |
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{ |
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struct list_head *next = pe->child_list.next; |
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|
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if (next == &pe->child_list) { |
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while (1) { |
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if (pe == root) |
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return NULL; |
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next = pe->child.next; |
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if (next != &pe->parent->child_list) |
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break; |
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pe = pe->parent; |
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} |
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} |
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|
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return list_entry(next, struct eeh_pe, child); |
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} |
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|
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/** |
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* eeh_pe_traverse - Traverse PEs in the specified PHB |
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* @root: root PE |
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* @fn: callback |
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* @flag: extra parameter to callback |
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* |
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* The function is used to traverse the specified PE and its |
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* child PEs. The traversing is to be terminated once the |
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* callback returns something other than NULL, or no more PEs |
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* to be traversed. |
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*/ |
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void *eeh_pe_traverse(struct eeh_pe *root, |
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eeh_pe_traverse_func fn, void *flag) |
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{ |
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struct eeh_pe *pe; |
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void *ret; |
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|
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eeh_for_each_pe(root, pe) { |
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ret = fn(pe, flag); |
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if (ret) return ret; |
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} |
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return NULL; |
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} |
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|
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/** |
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* eeh_pe_dev_traverse - Traverse the devices from the PE |
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* @root: EEH PE |
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* @fn: function callback |
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* @flag: extra parameter to callback |
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* |
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* The function is used to traverse the devices of the specified |
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* PE and its child PEs. |
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*/ |
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void eeh_pe_dev_traverse(struct eeh_pe *root, |
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eeh_edev_traverse_func fn, void *flag) |
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{ |
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struct eeh_pe *pe; |
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struct eeh_dev *edev, *tmp; |
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|
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if (!root) { |
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pr_warn("%s: Invalid PE %p\n", |
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__func__, root); |
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return; |
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} |
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|
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/* Traverse root PE */ |
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eeh_for_each_pe(root, pe) |
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eeh_pe_for_each_dev(pe, edev, tmp) |
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fn(edev, flag); |
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} |
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|
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/** |
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* __eeh_pe_get - Check the PE address |
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* |
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* For one particular PE, it can be identified by PE address |
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* or tranditional BDF address. BDF address is composed of |
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* Bus/Device/Function number. The extra data referred by flag |
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* indicates which type of address should be used. |
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*/ |
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static void *__eeh_pe_get(struct eeh_pe *pe, void *flag) |
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{ |
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int *target_pe = flag; |
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|
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/* PHB PEs are special and should be ignored */ |
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if (pe->type & EEH_PE_PHB) |
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return NULL; |
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|
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if (*target_pe == pe->addr) |
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return pe; |
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return NULL; |
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} |
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/** |
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* eeh_pe_get - Search PE based on the given address |
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* @phb: PCI controller |
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* @pe_no: PE number |
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* |
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* Search the corresponding PE based on the specified address which |
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* is included in the eeh device. The function is used to check if |
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* the associated PE has been created against the PE address. It's |
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* notable that the PE address has 2 format: traditional PE address |
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* which is composed of PCI bus/device/function number, or unified |
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* PE address. |
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*/ |
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struct eeh_pe *eeh_pe_get(struct pci_controller *phb, int pe_no) |
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{ |
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struct eeh_pe *root = eeh_phb_pe_get(phb); |
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return eeh_pe_traverse(root, __eeh_pe_get, &pe_no); |
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} |
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/** |
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* eeh_pe_tree_insert - Add EEH device to parent PE |
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* @edev: EEH device |
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* @new_pe_parent: PE to create additional PEs under |
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* |
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* Add EEH device to the PE in edev->pe_config_addr. If a PE already |
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* exists with that address then @edev is added to that PE. Otherwise |
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* a new PE is created and inserted into the PE tree as a child of |
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* @new_pe_parent. |
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* |
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* If @new_pe_parent is NULL then the new PE will be inserted under |
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* directly under the the PHB. |
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*/ |
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int eeh_pe_tree_insert(struct eeh_dev *edev, struct eeh_pe *new_pe_parent) |
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{ |
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struct pci_controller *hose = edev->controller; |
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struct eeh_pe *pe, *parent; |
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|
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/* |
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* Search the PE has been existing or not according |
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* to the PE address. If that has been existing, the |
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* PE should be composed of PCI bus and its subordinate |
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* components. |
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*/ |
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pe = eeh_pe_get(hose, edev->pe_config_addr); |
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if (pe) { |
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if (pe->type & EEH_PE_INVALID) { |
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list_add_tail(&edev->entry, &pe->edevs); |
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edev->pe = pe; |
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/* |
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* We're running to here because of PCI hotplug caused by |
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* EEH recovery. We need clear EEH_PE_INVALID until the top. |
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*/ |
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parent = pe; |
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while (parent) { |
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if (!(parent->type & EEH_PE_INVALID)) |
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break; |
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parent->type &= ~EEH_PE_INVALID; |
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parent = parent->parent; |
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} |
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eeh_edev_dbg(edev, "Added to existing PE (parent: PE#%x)\n", |
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pe->parent->addr); |
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} else { |
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/* Mark the PE as type of PCI bus */ |
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pe->type = EEH_PE_BUS; |
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edev->pe = pe; |
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|
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/* Put the edev to PE */ |
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list_add_tail(&edev->entry, &pe->edevs); |
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eeh_edev_dbg(edev, "Added to bus PE\n"); |
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} |
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return 0; |
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} |
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/* Create a new EEH PE */ |
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if (edev->physfn) |
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pe = eeh_pe_alloc(hose, EEH_PE_VF); |
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else |
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pe = eeh_pe_alloc(hose, EEH_PE_DEVICE); |
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if (!pe) { |
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pr_err("%s: out of memory!\n", __func__); |
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return -ENOMEM; |
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} |
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pe->addr = edev->pe_config_addr; |
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|
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/* |
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* Put the new EEH PE into hierarchy tree. If the parent |
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* can't be found, the newly created PE will be attached |
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* to PHB directly. Otherwise, we have to associate the |
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* PE with its parent. |
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*/ |
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if (!new_pe_parent) { |
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new_pe_parent = eeh_phb_pe_get(hose); |
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if (!new_pe_parent) { |
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pr_err("%s: No PHB PE is found (PHB Domain=%d)\n", |
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__func__, hose->global_number); |
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edev->pe = NULL; |
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kfree(pe); |
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return -EEXIST; |
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} |
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} |
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|
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/* link new PE into the tree */ |
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pe->parent = new_pe_parent; |
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list_add_tail(&pe->child, &new_pe_parent->child_list); |
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|
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/* |
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* Put the newly created PE into the child list and |
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* link the EEH device accordingly. |
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*/ |
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list_add_tail(&edev->entry, &pe->edevs); |
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edev->pe = pe; |
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eeh_edev_dbg(edev, "Added to new (parent: PE#%x)\n", |
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new_pe_parent->addr); |
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|
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return 0; |
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} |
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|
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/** |
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* eeh_pe_tree_remove - Remove one EEH device from the associated PE |
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* @edev: EEH device |
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* |
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* The PE hierarchy tree might be changed when doing PCI hotplug. |
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* Also, the PCI devices or buses could be removed from the system |
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* during EEH recovery. So we have to call the function remove the |
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* corresponding PE accordingly if necessary. |
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*/ |
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int eeh_pe_tree_remove(struct eeh_dev *edev) |
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{ |
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struct eeh_pe *pe, *parent, *child; |
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bool keep, recover; |
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int cnt; |
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|
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pe = eeh_dev_to_pe(edev); |
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if (!pe) { |
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eeh_edev_dbg(edev, "No PE found for device.\n"); |
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return -EEXIST; |
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} |
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|
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/* Remove the EEH device */ |
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edev->pe = NULL; |
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list_del(&edev->entry); |
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|
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/* |
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* Check if the parent PE includes any EEH devices. |
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* If not, we should delete that. Also, we should |
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* delete the parent PE if it doesn't have associated |
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* child PEs and EEH devices. |
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*/ |
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while (1) { |
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parent = pe->parent; |
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|
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/* PHB PEs should never be removed */ |
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if (pe->type & EEH_PE_PHB) |
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break; |
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|
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/* |
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* XXX: KEEP is set while resetting a PE. I don't think it's |
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* ever set without RECOVERING also being set. I could |
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* be wrong though so catch that with a WARN. |
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*/ |
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keep = !!(pe->state & EEH_PE_KEEP); |
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recover = !!(pe->state & EEH_PE_RECOVERING); |
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WARN_ON(keep && !recover); |
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|
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if (!keep && !recover) { |
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if (list_empty(&pe->edevs) && |
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list_empty(&pe->child_list)) { |
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list_del(&pe->child); |
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kfree(pe); |
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} else { |
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break; |
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} |
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} else { |
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/* |
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* Mark the PE as invalid. At the end of the recovery |
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* process any invalid PEs will be garbage collected. |
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* |
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* We need to delay the free()ing of them since we can |
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* remove edev's while traversing the PE tree which |
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* might trigger the removal of a PE and we can't |
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* deal with that (yet). |
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*/ |
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if (list_empty(&pe->edevs)) { |
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cnt = 0; |
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list_for_each_entry(child, &pe->child_list, child) { |
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if (!(child->type & EEH_PE_INVALID)) { |
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cnt++; |
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break; |
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} |
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} |
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|
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if (!cnt) |
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pe->type |= EEH_PE_INVALID; |
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else |
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break; |
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} |
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} |
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|
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pe = parent; |
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} |
|
|
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return 0; |
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} |
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|
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/** |
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* eeh_pe_update_time_stamp - Update PE's frozen time stamp |
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* @pe: EEH PE |
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* |
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* We have time stamp for each PE to trace its time of getting |
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* frozen in last hour. The function should be called to update |
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* the time stamp on first error of the specific PE. On the other |
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* handle, we needn't account for errors happened in last hour. |
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*/ |
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void eeh_pe_update_time_stamp(struct eeh_pe *pe) |
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{ |
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time64_t tstamp; |
|
|
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if (!pe) return; |
|
|
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if (pe->freeze_count <= 0) { |
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pe->freeze_count = 0; |
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pe->tstamp = ktime_get_seconds(); |
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} else { |
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tstamp = ktime_get_seconds(); |
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if (tstamp - pe->tstamp > 3600) { |
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pe->tstamp = tstamp; |
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pe->freeze_count = 0; |
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} |
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} |
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} |
|
|
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/** |
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* eeh_pe_state_mark - Mark specified state for PE and its associated device |
|
* @pe: EEH PE |
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* |
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* EEH error affects the current PE and its child PEs. The function |
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* is used to mark appropriate state for the affected PEs and the |
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* associated devices. |
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*/ |
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void eeh_pe_state_mark(struct eeh_pe *root, int state) |
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{ |
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struct eeh_pe *pe; |
|
|
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eeh_for_each_pe(root, pe) |
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if (!(pe->state & EEH_PE_REMOVED)) |
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pe->state |= state; |
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} |
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EXPORT_SYMBOL_GPL(eeh_pe_state_mark); |
|
|
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/** |
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* eeh_pe_mark_isolated |
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* @pe: EEH PE |
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* |
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* Record that a PE has been isolated by marking the PE and it's children as |
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* EEH_PE_ISOLATED (and EEH_PE_CFG_BLOCKED, if required) and their PCI devices |
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* as pci_channel_io_frozen. |
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*/ |
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void eeh_pe_mark_isolated(struct eeh_pe *root) |
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{ |
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struct eeh_pe *pe; |
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struct eeh_dev *edev; |
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struct pci_dev *pdev; |
|
|
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eeh_pe_state_mark(root, EEH_PE_ISOLATED); |
|
eeh_for_each_pe(root, pe) { |
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list_for_each_entry(edev, &pe->edevs, entry) { |
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pdev = eeh_dev_to_pci_dev(edev); |
|
if (pdev) |
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pdev->error_state = pci_channel_io_frozen; |
|
} |
|
/* Block PCI config access if required */ |
|
if (pe->state & EEH_PE_CFG_RESTRICTED) |
|
pe->state |= EEH_PE_CFG_BLOCKED; |
|
} |
|
} |
|
EXPORT_SYMBOL_GPL(eeh_pe_mark_isolated); |
|
|
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static void __eeh_pe_dev_mode_mark(struct eeh_dev *edev, void *flag) |
|
{ |
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int mode = *((int *)flag); |
|
|
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edev->mode |= mode; |
|
} |
|
|
|
/** |
|
* eeh_pe_dev_state_mark - Mark state for all device under the PE |
|
* @pe: EEH PE |
|
* |
|
* Mark specific state for all child devices of the PE. |
|
*/ |
|
void eeh_pe_dev_mode_mark(struct eeh_pe *pe, int mode) |
|
{ |
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eeh_pe_dev_traverse(pe, __eeh_pe_dev_mode_mark, &mode); |
|
} |
|
|
|
/** |
|
* eeh_pe_state_clear - Clear state for the PE |
|
* @data: EEH PE |
|
* @state: state |
|
* @include_passed: include passed-through devices? |
|
* |
|
* The function is used to clear the indicated state from the |
|
* given PE. Besides, we also clear the check count of the PE |
|
* as well. |
|
*/ |
|
void eeh_pe_state_clear(struct eeh_pe *root, int state, bool include_passed) |
|
{ |
|
struct eeh_pe *pe; |
|
struct eeh_dev *edev, *tmp; |
|
struct pci_dev *pdev; |
|
|
|
eeh_for_each_pe(root, pe) { |
|
/* Keep the state of permanently removed PE intact */ |
|
if (pe->state & EEH_PE_REMOVED) |
|
continue; |
|
|
|
if (!include_passed && eeh_pe_passed(pe)) |
|
continue; |
|
|
|
pe->state &= ~state; |
|
|
|
/* |
|
* Special treatment on clearing isolated state. Clear |
|
* check count since last isolation and put all affected |
|
* devices to normal state. |
|
*/ |
|
if (!(state & EEH_PE_ISOLATED)) |
|
continue; |
|
|
|
pe->check_count = 0; |
|
eeh_pe_for_each_dev(pe, edev, tmp) { |
|
pdev = eeh_dev_to_pci_dev(edev); |
|
if (!pdev) |
|
continue; |
|
|
|
pdev->error_state = pci_channel_io_normal; |
|
} |
|
|
|
/* Unblock PCI config access if required */ |
|
if (pe->state & EEH_PE_CFG_RESTRICTED) |
|
pe->state &= ~EEH_PE_CFG_BLOCKED; |
|
} |
|
} |
|
|
|
/* |
|
* Some PCI bridges (e.g. PLX bridges) have primary/secondary |
|
* buses assigned explicitly by firmware, and we probably have |
|
* lost that after reset. So we have to delay the check until |
|
* the PCI-CFG registers have been restored for the parent |
|
* bridge. |
|
* |
|
* Don't use normal PCI-CFG accessors, which probably has been |
|
* blocked on normal path during the stage. So we need utilize |
|
* eeh operations, which is always permitted. |
|
*/ |
|
static void eeh_bridge_check_link(struct eeh_dev *edev) |
|
{ |
|
int cap; |
|
uint32_t val; |
|
int timeout = 0; |
|
|
|
/* |
|
* We only check root port and downstream ports of |
|
* PCIe switches |
|
*/ |
|
if (!(edev->mode & (EEH_DEV_ROOT_PORT | EEH_DEV_DS_PORT))) |
|
return; |
|
|
|
eeh_edev_dbg(edev, "Checking PCIe link...\n"); |
|
|
|
/* Check slot status */ |
|
cap = edev->pcie_cap; |
|
eeh_ops->read_config(edev, cap + PCI_EXP_SLTSTA, 2, &val); |
|
if (!(val & PCI_EXP_SLTSTA_PDS)) { |
|
eeh_edev_dbg(edev, "No card in the slot (0x%04x) !\n", val); |
|
return; |
|
} |
|
|
|
/* Check power status if we have the capability */ |
|
eeh_ops->read_config(edev, cap + PCI_EXP_SLTCAP, 2, &val); |
|
if (val & PCI_EXP_SLTCAP_PCP) { |
|
eeh_ops->read_config(edev, cap + PCI_EXP_SLTCTL, 2, &val); |
|
if (val & PCI_EXP_SLTCTL_PCC) { |
|
eeh_edev_dbg(edev, "In power-off state, power it on ...\n"); |
|
val &= ~(PCI_EXP_SLTCTL_PCC | PCI_EXP_SLTCTL_PIC); |
|
val |= (0x0100 & PCI_EXP_SLTCTL_PIC); |
|
eeh_ops->write_config(edev, cap + PCI_EXP_SLTCTL, 2, val); |
|
msleep(2 * 1000); |
|
} |
|
} |
|
|
|
/* Enable link */ |
|
eeh_ops->read_config(edev, cap + PCI_EXP_LNKCTL, 2, &val); |
|
val &= ~PCI_EXP_LNKCTL_LD; |
|
eeh_ops->write_config(edev, cap + PCI_EXP_LNKCTL, 2, val); |
|
|
|
/* Check link */ |
|
eeh_ops->read_config(edev, cap + PCI_EXP_LNKCAP, 4, &val); |
|
if (!(val & PCI_EXP_LNKCAP_DLLLARC)) { |
|
eeh_edev_dbg(edev, "No link reporting capability (0x%08x) \n", val); |
|
msleep(1000); |
|
return; |
|
} |
|
|
|
/* Wait the link is up until timeout (5s) */ |
|
timeout = 0; |
|
while (timeout < 5000) { |
|
msleep(20); |
|
timeout += 20; |
|
|
|
eeh_ops->read_config(edev, cap + PCI_EXP_LNKSTA, 2, &val); |
|
if (val & PCI_EXP_LNKSTA_DLLLA) |
|
break; |
|
} |
|
|
|
if (val & PCI_EXP_LNKSTA_DLLLA) |
|
eeh_edev_dbg(edev, "Link up (%s)\n", |
|
(val & PCI_EXP_LNKSTA_CLS_2_5GB) ? "2.5GB" : "5GB"); |
|
else |
|
eeh_edev_dbg(edev, "Link not ready (0x%04x)\n", val); |
|
} |
|
|
|
#define BYTE_SWAP(OFF) (8*((OFF)/4)+3-(OFF)) |
|
#define SAVED_BYTE(OFF) (((u8 *)(edev->config_space))[BYTE_SWAP(OFF)]) |
|
|
|
static void eeh_restore_bridge_bars(struct eeh_dev *edev) |
|
{ |
|
int i; |
|
|
|
/* |
|
* Device BARs: 0x10 - 0x18 |
|
* Bus numbers and windows: 0x18 - 0x30 |
|
*/ |
|
for (i = 4; i < 13; i++) |
|
eeh_ops->write_config(edev, i*4, 4, edev->config_space[i]); |
|
/* Rom: 0x38 */ |
|
eeh_ops->write_config(edev, 14*4, 4, edev->config_space[14]); |
|
|
|
/* Cache line & Latency timer: 0xC 0xD */ |
|
eeh_ops->write_config(edev, PCI_CACHE_LINE_SIZE, 1, |
|
SAVED_BYTE(PCI_CACHE_LINE_SIZE)); |
|
eeh_ops->write_config(edev, PCI_LATENCY_TIMER, 1, |
|
SAVED_BYTE(PCI_LATENCY_TIMER)); |
|
/* Max latency, min grant, interrupt ping and line: 0x3C */ |
|
eeh_ops->write_config(edev, 15*4, 4, edev->config_space[15]); |
|
|
|
/* PCI Command: 0x4 */ |
|
eeh_ops->write_config(edev, PCI_COMMAND, 4, edev->config_space[1] | |
|
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); |
|
|
|
/* Check the PCIe link is ready */ |
|
eeh_bridge_check_link(edev); |
|
} |
|
|
|
static void eeh_restore_device_bars(struct eeh_dev *edev) |
|
{ |
|
int i; |
|
u32 cmd; |
|
|
|
for (i = 4; i < 10; i++) |
|
eeh_ops->write_config(edev, i*4, 4, edev->config_space[i]); |
|
/* 12 == Expansion ROM Address */ |
|
eeh_ops->write_config(edev, 12*4, 4, edev->config_space[12]); |
|
|
|
eeh_ops->write_config(edev, PCI_CACHE_LINE_SIZE, 1, |
|
SAVED_BYTE(PCI_CACHE_LINE_SIZE)); |
|
eeh_ops->write_config(edev, PCI_LATENCY_TIMER, 1, |
|
SAVED_BYTE(PCI_LATENCY_TIMER)); |
|
|
|
/* max latency, min grant, interrupt pin and line */ |
|
eeh_ops->write_config(edev, 15*4, 4, edev->config_space[15]); |
|
|
|
/* |
|
* Restore PERR & SERR bits, some devices require it, |
|
* don't touch the other command bits |
|
*/ |
|
eeh_ops->read_config(edev, PCI_COMMAND, 4, &cmd); |
|
if (edev->config_space[1] & PCI_COMMAND_PARITY) |
|
cmd |= PCI_COMMAND_PARITY; |
|
else |
|
cmd &= ~PCI_COMMAND_PARITY; |
|
if (edev->config_space[1] & PCI_COMMAND_SERR) |
|
cmd |= PCI_COMMAND_SERR; |
|
else |
|
cmd &= ~PCI_COMMAND_SERR; |
|
eeh_ops->write_config(edev, PCI_COMMAND, 4, cmd); |
|
} |
|
|
|
/** |
|
* eeh_restore_one_device_bars - Restore the Base Address Registers for one device |
|
* @data: EEH device |
|
* @flag: Unused |
|
* |
|
* Loads the PCI configuration space base address registers, |
|
* the expansion ROM base address, the latency timer, and etc. |
|
* from the saved values in the device node. |
|
*/ |
|
static void eeh_restore_one_device_bars(struct eeh_dev *edev, void *flag) |
|
{ |
|
/* Do special restore for bridges */ |
|
if (edev->mode & EEH_DEV_BRIDGE) |
|
eeh_restore_bridge_bars(edev); |
|
else |
|
eeh_restore_device_bars(edev); |
|
|
|
if (eeh_ops->restore_config) |
|
eeh_ops->restore_config(edev); |
|
} |
|
|
|
/** |
|
* eeh_pe_restore_bars - Restore the PCI config space info |
|
* @pe: EEH PE |
|
* |
|
* This routine performs a recursive walk to the children |
|
* of this device as well. |
|
*/ |
|
void eeh_pe_restore_bars(struct eeh_pe *pe) |
|
{ |
|
/* |
|
* We needn't take the EEH lock since eeh_pe_dev_traverse() |
|
* will take that. |
|
*/ |
|
eeh_pe_dev_traverse(pe, eeh_restore_one_device_bars, NULL); |
|
} |
|
|
|
/** |
|
* eeh_pe_loc_get - Retrieve location code binding to the given PE |
|
* @pe: EEH PE |
|
* |
|
* Retrieve the location code of the given PE. If the primary PE bus |
|
* is root bus, we will grab location code from PHB device tree node |
|
* or root port. Otherwise, the upstream bridge's device tree node |
|
* of the primary PE bus will be checked for the location code. |
|
*/ |
|
const char *eeh_pe_loc_get(struct eeh_pe *pe) |
|
{ |
|
struct pci_bus *bus = eeh_pe_bus_get(pe); |
|
struct device_node *dn; |
|
const char *loc = NULL; |
|
|
|
while (bus) { |
|
dn = pci_bus_to_OF_node(bus); |
|
if (!dn) { |
|
bus = bus->parent; |
|
continue; |
|
} |
|
|
|
if (pci_is_root_bus(bus)) |
|
loc = of_get_property(dn, "ibm,io-base-loc-code", NULL); |
|
else |
|
loc = of_get_property(dn, "ibm,slot-location-code", |
|
NULL); |
|
|
|
if (loc) |
|
return loc; |
|
|
|
bus = bus->parent; |
|
} |
|
|
|
return "N/A"; |
|
} |
|
|
|
/** |
|
* eeh_pe_bus_get - Retrieve PCI bus according to the given PE |
|
* @pe: EEH PE |
|
* |
|
* Retrieve the PCI bus according to the given PE. Basically, |
|
* there're 3 types of PEs: PHB/Bus/Device. For PHB PE, the |
|
* primary PCI bus will be retrieved. The parent bus will be |
|
* returned for BUS PE. However, we don't have associated PCI |
|
* bus for DEVICE PE. |
|
*/ |
|
struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe) |
|
{ |
|
struct eeh_dev *edev; |
|
struct pci_dev *pdev; |
|
|
|
if (pe->type & EEH_PE_PHB) |
|
return pe->phb->bus; |
|
|
|
/* The primary bus might be cached during probe time */ |
|
if (pe->state & EEH_PE_PRI_BUS) |
|
return pe->bus; |
|
|
|
/* Retrieve the parent PCI bus of first (top) PCI device */ |
|
edev = list_first_entry_or_null(&pe->edevs, struct eeh_dev, entry); |
|
pdev = eeh_dev_to_pci_dev(edev); |
|
if (pdev) |
|
return pdev->bus; |
|
|
|
return NULL; |
|
}
|
|
|