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513 lines
12 KiB
513 lines
12 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Based on arch/arm/mm/proc.S |
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* |
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* Copyright (C) 2001 Deep Blue Solutions Ltd. |
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* Copyright (C) 2012 ARM Ltd. |
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* Author: Catalin Marinas <catalin.marinas@arm.com> |
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*/ |
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#include <linux/init.h> |
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#include <linux/linkage.h> |
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#include <linux/pgtable.h> |
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#include <asm/assembler.h> |
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#include <asm/asm-offsets.h> |
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#include <asm/asm_pointer_auth.h> |
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#include <asm/hwcap.h> |
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#include <asm/pgtable-hwdef.h> |
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#include <asm/cpufeature.h> |
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#include <asm/alternative.h> |
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#include <asm/smp.h> |
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#include <asm/sysreg.h> |
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#ifdef CONFIG_ARM64_64K_PAGES |
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#define TCR_TG_FLAGS TCR_TG0_64K | TCR_TG1_64K |
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#elif defined(CONFIG_ARM64_16K_PAGES) |
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#define TCR_TG_FLAGS TCR_TG0_16K | TCR_TG1_16K |
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#else /* CONFIG_ARM64_4K_PAGES */ |
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#define TCR_TG_FLAGS TCR_TG0_4K | TCR_TG1_4K |
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#endif |
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#ifdef CONFIG_RANDOMIZE_BASE |
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#define TCR_KASLR_FLAGS TCR_NFD1 |
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#else |
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#define TCR_KASLR_FLAGS 0 |
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#endif |
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#define TCR_SMP_FLAGS TCR_SHARED |
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/* PTWs cacheable, inner/outer WBWA */ |
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#define TCR_CACHE_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA |
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#ifdef CONFIG_KASAN_SW_TAGS |
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#define TCR_KASAN_SW_FLAGS TCR_TBI1 | TCR_TBID1 |
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#else |
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#define TCR_KASAN_SW_FLAGS 0 |
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#endif |
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#ifdef CONFIG_KASAN_HW_TAGS |
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#define TCR_KASAN_HW_FLAGS SYS_TCR_EL1_TCMA1 | TCR_TBI1 | TCR_TBID1 |
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#else |
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#define TCR_KASAN_HW_FLAGS 0 |
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#endif |
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/* |
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* Default MAIR_EL1. MT_NORMAL_TAGGED is initially mapped as Normal memory and |
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* changed during __cpu_setup to Normal Tagged if the system supports MTE. |
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*/ |
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#define MAIR_EL1_SET \ |
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(MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRnE, MT_DEVICE_nGnRnE) | \ |
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MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRE, MT_DEVICE_nGnRE) | \ |
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MAIR_ATTRIDX(MAIR_ATTR_DEVICE_GRE, MT_DEVICE_GRE) | \ |
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MAIR_ATTRIDX(MAIR_ATTR_NORMAL_NC, MT_NORMAL_NC) | \ |
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MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL) | \ |
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MAIR_ATTRIDX(MAIR_ATTR_NORMAL_WT, MT_NORMAL_WT) | \ |
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MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL_TAGGED)) |
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#ifdef CONFIG_CPU_PM |
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/** |
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* cpu_do_suspend - save CPU registers context |
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* |
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* x0: virtual address of context pointer |
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* |
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* This must be kept in sync with struct cpu_suspend_ctx in <asm/suspend.h>. |
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*/ |
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SYM_FUNC_START(cpu_do_suspend) |
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mrs x2, tpidr_el0 |
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mrs x3, tpidrro_el0 |
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mrs x4, contextidr_el1 |
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mrs x5, osdlr_el1 |
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mrs x6, cpacr_el1 |
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mrs x7, tcr_el1 |
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mrs x8, vbar_el1 |
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mrs x9, mdscr_el1 |
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mrs x10, oslsr_el1 |
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mrs x11, sctlr_el1 |
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alternative_if_not ARM64_HAS_VIRT_HOST_EXTN |
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mrs x12, tpidr_el1 |
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alternative_else |
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mrs x12, tpidr_el2 |
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alternative_endif |
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mrs x13, sp_el0 |
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stp x2, x3, [x0] |
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stp x4, x5, [x0, #16] |
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stp x6, x7, [x0, #32] |
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stp x8, x9, [x0, #48] |
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stp x10, x11, [x0, #64] |
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stp x12, x13, [x0, #80] |
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/* |
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* Save x18 as it may be used as a platform register, e.g. by shadow |
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* call stack. |
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*/ |
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str x18, [x0, #96] |
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ret |
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SYM_FUNC_END(cpu_do_suspend) |
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/** |
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* cpu_do_resume - restore CPU register context |
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* |
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* x0: Address of context pointer |
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*/ |
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.pushsection ".idmap.text", "awx" |
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SYM_FUNC_START(cpu_do_resume) |
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ldp x2, x3, [x0] |
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ldp x4, x5, [x0, #16] |
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ldp x6, x8, [x0, #32] |
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ldp x9, x10, [x0, #48] |
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ldp x11, x12, [x0, #64] |
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ldp x13, x14, [x0, #80] |
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/* |
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* Restore x18, as it may be used as a platform register, and clear |
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* the buffer to minimize the risk of exposure when used for shadow |
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* call stack. |
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*/ |
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ldr x18, [x0, #96] |
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str xzr, [x0, #96] |
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msr tpidr_el0, x2 |
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msr tpidrro_el0, x3 |
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msr contextidr_el1, x4 |
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msr cpacr_el1, x6 |
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/* Don't change t0sz here, mask those bits when restoring */ |
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mrs x7, tcr_el1 |
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bfi x8, x7, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH |
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msr tcr_el1, x8 |
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msr vbar_el1, x9 |
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/* |
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* __cpu_setup() cleared MDSCR_EL1.MDE and friends, before unmasking |
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* debug exceptions. By restoring MDSCR_EL1 here, we may take a debug |
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* exception. Mask them until local_daif_restore() in cpu_suspend() |
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* resets them. |
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*/ |
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disable_daif |
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msr mdscr_el1, x10 |
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msr sctlr_el1, x12 |
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alternative_if_not ARM64_HAS_VIRT_HOST_EXTN |
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msr tpidr_el1, x13 |
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alternative_else |
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msr tpidr_el2, x13 |
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alternative_endif |
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msr sp_el0, x14 |
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/* |
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* Restore oslsr_el1 by writing oslar_el1 |
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*/ |
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msr osdlr_el1, x5 |
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ubfx x11, x11, #1, #1 |
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msr oslar_el1, x11 |
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reset_pmuserenr_el0 x0 // Disable PMU access from EL0 |
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reset_amuserenr_el0 x0 // Disable AMU access from EL0 |
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alternative_if ARM64_HAS_RAS_EXTN |
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msr_s SYS_DISR_EL1, xzr |
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alternative_else_nop_endif |
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ptrauth_keys_install_kernel_nosync x14, x1, x2, x3 |
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isb |
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ret |
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SYM_FUNC_END(cpu_do_resume) |
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.popsection |
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#endif |
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.pushsection ".idmap.text", "awx" |
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.macro __idmap_cpu_set_reserved_ttbr1, tmp1, tmp2 |
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adrp \tmp1, reserved_pg_dir |
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phys_to_ttbr \tmp2, \tmp1 |
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offset_ttbr1 \tmp2, \tmp1 |
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msr ttbr1_el1, \tmp2 |
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isb |
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tlbi vmalle1 |
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dsb nsh |
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isb |
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.endm |
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/* |
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* void idmap_cpu_replace_ttbr1(phys_addr_t ttbr1) |
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* |
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* This is the low-level counterpart to cpu_replace_ttbr1, and should not be |
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* called by anything else. It can only be executed from a TTBR0 mapping. |
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*/ |
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SYM_FUNC_START(idmap_cpu_replace_ttbr1) |
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save_and_disable_daif flags=x2 |
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__idmap_cpu_set_reserved_ttbr1 x1, x3 |
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offset_ttbr1 x0, x3 |
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msr ttbr1_el1, x0 |
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isb |
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restore_daif x2 |
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ret |
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SYM_FUNC_END(idmap_cpu_replace_ttbr1) |
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.popsection |
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#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 |
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.pushsection ".idmap.text", "awx" |
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.macro __idmap_kpti_get_pgtable_ent, type |
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dc cvac, cur_\()\type\()p // Ensure any existing dirty |
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dmb sy // lines are written back before |
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ldr \type, [cur_\()\type\()p] // loading the entry |
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tbz \type, #0, skip_\()\type // Skip invalid and |
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tbnz \type, #11, skip_\()\type // non-global entries |
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.endm |
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.macro __idmap_kpti_put_pgtable_ent_ng, type |
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orr \type, \type, #PTE_NG // Same bit for blocks and pages |
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str \type, [cur_\()\type\()p] // Update the entry and ensure |
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dmb sy // that it is visible to all |
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dc civac, cur_\()\type\()p // CPUs. |
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.endm |
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/* |
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* void __kpti_install_ng_mappings(int cpu, int num_cpus, phys_addr_t swapper) |
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* |
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* Called exactly once from stop_machine context by each CPU found during boot. |
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*/ |
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__idmap_kpti_flag: |
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.long 1 |
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SYM_FUNC_START(idmap_kpti_install_ng_mappings) |
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cpu .req w0 |
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num_cpus .req w1 |
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swapper_pa .req x2 |
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swapper_ttb .req x3 |
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flag_ptr .req x4 |
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cur_pgdp .req x5 |
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end_pgdp .req x6 |
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pgd .req x7 |
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cur_pudp .req x8 |
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end_pudp .req x9 |
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pud .req x10 |
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cur_pmdp .req x11 |
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end_pmdp .req x12 |
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pmd .req x13 |
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cur_ptep .req x14 |
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end_ptep .req x15 |
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pte .req x16 |
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mrs swapper_ttb, ttbr1_el1 |
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restore_ttbr1 swapper_ttb |
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adr flag_ptr, __idmap_kpti_flag |
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cbnz cpu, __idmap_kpti_secondary |
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/* We're the boot CPU. Wait for the others to catch up */ |
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sevl |
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1: wfe |
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ldaxr w17, [flag_ptr] |
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eor w17, w17, num_cpus |
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cbnz w17, 1b |
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/* We need to walk swapper, so turn off the MMU. */ |
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pre_disable_mmu_workaround |
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mrs x17, sctlr_el1 |
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bic x17, x17, #SCTLR_ELx_M |
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msr sctlr_el1, x17 |
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isb |
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/* Everybody is enjoying the idmap, so we can rewrite swapper. */ |
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/* PGD */ |
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mov cur_pgdp, swapper_pa |
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add end_pgdp, cur_pgdp, #(PTRS_PER_PGD * 8) |
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do_pgd: __idmap_kpti_get_pgtable_ent pgd |
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tbnz pgd, #1, walk_puds |
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next_pgd: |
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__idmap_kpti_put_pgtable_ent_ng pgd |
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skip_pgd: |
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add cur_pgdp, cur_pgdp, #8 |
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cmp cur_pgdp, end_pgdp |
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b.ne do_pgd |
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/* Publish the updated tables and nuke all the TLBs */ |
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dsb sy |
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tlbi vmalle1is |
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dsb ish |
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isb |
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/* We're done: fire up the MMU again */ |
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mrs x17, sctlr_el1 |
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orr x17, x17, #SCTLR_ELx_M |
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set_sctlr_el1 x17 |
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/* Set the flag to zero to indicate that we're all done */ |
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str wzr, [flag_ptr] |
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ret |
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/* PUD */ |
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walk_puds: |
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.if CONFIG_PGTABLE_LEVELS > 3 |
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pte_to_phys cur_pudp, pgd |
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add end_pudp, cur_pudp, #(PTRS_PER_PUD * 8) |
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do_pud: __idmap_kpti_get_pgtable_ent pud |
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tbnz pud, #1, walk_pmds |
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next_pud: |
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__idmap_kpti_put_pgtable_ent_ng pud |
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skip_pud: |
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add cur_pudp, cur_pudp, 8 |
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cmp cur_pudp, end_pudp |
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b.ne do_pud |
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b next_pgd |
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.else /* CONFIG_PGTABLE_LEVELS <= 3 */ |
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mov pud, pgd |
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b walk_pmds |
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next_pud: |
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b next_pgd |
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.endif |
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/* PMD */ |
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walk_pmds: |
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.if CONFIG_PGTABLE_LEVELS > 2 |
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pte_to_phys cur_pmdp, pud |
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add end_pmdp, cur_pmdp, #(PTRS_PER_PMD * 8) |
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do_pmd: __idmap_kpti_get_pgtable_ent pmd |
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tbnz pmd, #1, walk_ptes |
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next_pmd: |
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__idmap_kpti_put_pgtable_ent_ng pmd |
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skip_pmd: |
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add cur_pmdp, cur_pmdp, #8 |
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cmp cur_pmdp, end_pmdp |
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b.ne do_pmd |
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b next_pud |
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.else /* CONFIG_PGTABLE_LEVELS <= 2 */ |
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mov pmd, pud |
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b walk_ptes |
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next_pmd: |
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b next_pud |
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.endif |
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/* PTE */ |
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walk_ptes: |
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pte_to_phys cur_ptep, pmd |
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add end_ptep, cur_ptep, #(PTRS_PER_PTE * 8) |
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do_pte: __idmap_kpti_get_pgtable_ent pte |
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__idmap_kpti_put_pgtable_ent_ng pte |
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skip_pte: |
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add cur_ptep, cur_ptep, #8 |
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cmp cur_ptep, end_ptep |
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b.ne do_pte |
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b next_pmd |
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.unreq cpu |
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.unreq num_cpus |
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.unreq swapper_pa |
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.unreq cur_pgdp |
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.unreq end_pgdp |
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.unreq pgd |
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.unreq cur_pudp |
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.unreq end_pudp |
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.unreq pud |
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.unreq cur_pmdp |
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.unreq end_pmdp |
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.unreq pmd |
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.unreq cur_ptep |
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.unreq end_ptep |
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.unreq pte |
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/* Secondary CPUs end up here */ |
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__idmap_kpti_secondary: |
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/* Uninstall swapper before surgery begins */ |
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__idmap_cpu_set_reserved_ttbr1 x16, x17 |
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/* Increment the flag to let the boot CPU we're ready */ |
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1: ldxr w16, [flag_ptr] |
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add w16, w16, #1 |
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stxr w17, w16, [flag_ptr] |
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cbnz w17, 1b |
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/* Wait for the boot CPU to finish messing around with swapper */ |
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sevl |
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1: wfe |
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ldxr w16, [flag_ptr] |
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cbnz w16, 1b |
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/* All done, act like nothing happened */ |
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offset_ttbr1 swapper_ttb, x16 |
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msr ttbr1_el1, swapper_ttb |
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isb |
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ret |
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.unreq swapper_ttb |
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.unreq flag_ptr |
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SYM_FUNC_END(idmap_kpti_install_ng_mappings) |
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.popsection |
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#endif |
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/* |
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* __cpu_setup |
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* |
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* Initialise the processor for turning the MMU on. |
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* |
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* Output: |
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* Return in x0 the value of the SCTLR_EL1 register. |
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*/ |
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.pushsection ".idmap.text", "awx" |
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SYM_FUNC_START(__cpu_setup) |
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tlbi vmalle1 // Invalidate local TLB |
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dsb nsh |
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mov x1, #3 << 20 |
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msr cpacr_el1, x1 // Enable FP/ASIMD |
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mov x1, #1 << 12 // Reset mdscr_el1 and disable |
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msr mdscr_el1, x1 // access to the DCC from EL0 |
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isb // Unmask debug exceptions now, |
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enable_dbg // since this is per-cpu |
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reset_pmuserenr_el0 x1 // Disable PMU access from EL0 |
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reset_amuserenr_el0 x1 // Disable AMU access from EL0 |
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/* |
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* Memory region attributes |
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*/ |
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mov_q x5, MAIR_EL1_SET |
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#ifdef CONFIG_ARM64_MTE |
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mte_tcr .req x20 |
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mov mte_tcr, #0 |
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/* |
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* Update MAIR_EL1, GCR_EL1 and TFSR*_EL1 if MTE is supported |
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* (ID_AA64PFR1_EL1[11:8] > 1). |
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*/ |
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mrs x10, ID_AA64PFR1_EL1 |
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ubfx x10, x10, #ID_AA64PFR1_MTE_SHIFT, #4 |
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cmp x10, #ID_AA64PFR1_MTE |
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b.lt 1f |
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/* Normal Tagged memory type at the corresponding MAIR index */ |
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mov x10, #MAIR_ATTR_NORMAL_TAGGED |
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bfi x5, x10, #(8 * MT_NORMAL_TAGGED), #8 |
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/* initialize GCR_EL1: all non-zero tags excluded by default */ |
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mov x10, #(SYS_GCR_EL1_RRND | SYS_GCR_EL1_EXCL_MASK) |
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msr_s SYS_GCR_EL1, x10 |
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/* |
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* If GCR_EL1.RRND=1 is implemented the same way as RRND=0, then |
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* RGSR_EL1.SEED must be non-zero for IRG to produce |
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* pseudorandom numbers. As RGSR_EL1 is UNKNOWN out of reset, we |
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* must initialize it. |
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*/ |
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mrs x10, CNTVCT_EL0 |
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ands x10, x10, #SYS_RGSR_EL1_SEED_MASK |
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csinc x10, x10, xzr, ne |
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lsl x10, x10, #SYS_RGSR_EL1_SEED_SHIFT |
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msr_s SYS_RGSR_EL1, x10 |
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/* clear any pending tag check faults in TFSR*_EL1 */ |
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msr_s SYS_TFSR_EL1, xzr |
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msr_s SYS_TFSRE0_EL1, xzr |
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/* set the TCR_EL1 bits */ |
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mov_q mte_tcr, TCR_KASAN_HW_FLAGS |
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1: |
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#endif |
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msr mair_el1, x5 |
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/* |
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* Set/prepare TCR and TTBR. TCR_EL1.T1SZ gets further |
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* adjusted if the kernel is compiled with 52bit VA support. |
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*/ |
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mov_q x10, TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \ |
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TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \ |
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TCR_TBI0 | TCR_A1 | TCR_KASAN_SW_FLAGS |
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#ifdef CONFIG_ARM64_MTE |
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orr x10, x10, mte_tcr |
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.unreq mte_tcr |
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#endif |
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tcr_clear_errata_bits x10, x9, x5 |
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#ifdef CONFIG_ARM64_VA_BITS_52 |
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ldr_l x9, vabits_actual |
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sub x9, xzr, x9 |
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add x9, x9, #64 |
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tcr_set_t1sz x10, x9 |
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#else |
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ldr_l x9, idmap_t0sz |
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#endif |
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tcr_set_t0sz x10, x9 |
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/* |
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* Set the IPS bits in TCR_EL1. |
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*/ |
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tcr_compute_pa_size x10, #TCR_IPS_SHIFT, x5, x6 |
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#ifdef CONFIG_ARM64_HW_AFDBM |
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/* |
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* Enable hardware update of the Access Flags bit. |
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* Hardware dirty bit management is enabled later, |
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* via capabilities. |
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*/ |
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mrs x9, ID_AA64MMFR1_EL1 |
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and x9, x9, #0xf |
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cbz x9, 1f |
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orr x10, x10, #TCR_HA // hardware Access flag update |
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1: |
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#endif /* CONFIG_ARM64_HW_AFDBM */ |
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msr tcr_el1, x10 |
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/* |
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* Prepare SCTLR |
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*/ |
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mov_q x0, INIT_SCTLR_EL1_MMU_ON |
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ret // return to head.S |
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SYM_FUNC_END(__cpu_setup)
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