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227 lines
7.0 KiB
227 lines
7.0 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Copyright (C) 2015, 2016 ARM Ltd. |
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*/ |
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#ifndef __KVM_ARM_VGIC_MMIO_H__ |
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#define __KVM_ARM_VGIC_MMIO_H__ |
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struct vgic_register_region { |
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unsigned int reg_offset; |
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unsigned int len; |
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unsigned int bits_per_irq; |
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unsigned int access_flags; |
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union { |
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unsigned long (*read)(struct kvm_vcpu *vcpu, gpa_t addr, |
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unsigned int len); |
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unsigned long (*its_read)(struct kvm *kvm, struct vgic_its *its, |
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gpa_t addr, unsigned int len); |
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}; |
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union { |
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void (*write)(struct kvm_vcpu *vcpu, gpa_t addr, |
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unsigned int len, unsigned long val); |
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void (*its_write)(struct kvm *kvm, struct vgic_its *its, |
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gpa_t addr, unsigned int len, |
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unsigned long val); |
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}; |
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unsigned long (*uaccess_read)(struct kvm_vcpu *vcpu, gpa_t addr, |
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unsigned int len); |
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union { |
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int (*uaccess_write)(struct kvm_vcpu *vcpu, gpa_t addr, |
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unsigned int len, unsigned long val); |
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int (*uaccess_its_write)(struct kvm *kvm, struct vgic_its *its, |
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gpa_t addr, unsigned int len, |
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unsigned long val); |
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}; |
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}; |
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extern struct kvm_io_device_ops kvm_io_gic_ops; |
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#define VGIC_ACCESS_8bit 1 |
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#define VGIC_ACCESS_32bit 2 |
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#define VGIC_ACCESS_64bit 4 |
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/* |
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* Generate a mask that covers the number of bytes required to address |
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* up to 1024 interrupts, each represented by <bits> bits. This assumes |
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* that <bits> is a power of two. |
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*/ |
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#define VGIC_ADDR_IRQ_MASK(bits) (((bits) * 1024 / 8) - 1) |
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/* |
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* (addr & mask) gives us the _byte_ offset for the INT ID. |
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* We multiply this by 8 the get the _bit_ offset, then divide this by |
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* the number of bits to learn the actual INT ID. |
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* But instead of a division (which requires a "long long div" implementation), |
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* we shift by the binary logarithm of <bits>. |
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* This assumes that <bits> is a power of two. |
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*/ |
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#define VGIC_ADDR_TO_INTID(addr, bits) (((addr) & VGIC_ADDR_IRQ_MASK(bits)) * \ |
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8 >> ilog2(bits)) |
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/* |
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* Some VGIC registers store per-IRQ information, with a different number |
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* of bits per IRQ. For those registers this macro is used. |
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* The _WITH_LENGTH version instantiates registers with a fixed length |
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* and is mutually exclusive with the _PER_IRQ version. |
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*/ |
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#define REGISTER_DESC_WITH_BITS_PER_IRQ(off, rd, wr, ur, uw, bpi, acc) \ |
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{ \ |
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.reg_offset = off, \ |
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.bits_per_irq = bpi, \ |
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.len = bpi * 1024 / 8, \ |
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.access_flags = acc, \ |
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.read = rd, \ |
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.write = wr, \ |
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.uaccess_read = ur, \ |
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.uaccess_write = uw, \ |
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} |
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#define REGISTER_DESC_WITH_LENGTH(off, rd, wr, length, acc) \ |
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{ \ |
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.reg_offset = off, \ |
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.bits_per_irq = 0, \ |
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.len = length, \ |
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.access_flags = acc, \ |
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.read = rd, \ |
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.write = wr, \ |
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} |
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#define REGISTER_DESC_WITH_LENGTH_UACCESS(off, rd, wr, urd, uwr, length, acc) \ |
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{ \ |
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.reg_offset = off, \ |
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.bits_per_irq = 0, \ |
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.len = length, \ |
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.access_flags = acc, \ |
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.read = rd, \ |
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.write = wr, \ |
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.uaccess_read = urd, \ |
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.uaccess_write = uwr, \ |
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} |
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unsigned long vgic_data_mmio_bus_to_host(const void *val, unsigned int len); |
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void vgic_data_host_to_mmio_bus(void *buf, unsigned int len, |
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unsigned long data); |
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unsigned long extract_bytes(u64 data, unsigned int offset, |
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unsigned int num); |
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u64 update_64bit_reg(u64 reg, unsigned int offset, unsigned int len, |
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unsigned long val); |
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unsigned long vgic_mmio_read_raz(struct kvm_vcpu *vcpu, |
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gpa_t addr, unsigned int len); |
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unsigned long vgic_mmio_read_rao(struct kvm_vcpu *vcpu, |
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gpa_t addr, unsigned int len); |
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void vgic_mmio_write_wi(struct kvm_vcpu *vcpu, gpa_t addr, |
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unsigned int len, unsigned long val); |
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int vgic_mmio_uaccess_write_wi(struct kvm_vcpu *vcpu, gpa_t addr, |
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unsigned int len, unsigned long val); |
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unsigned long vgic_mmio_read_group(struct kvm_vcpu *vcpu, gpa_t addr, |
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unsigned int len); |
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void vgic_mmio_write_group(struct kvm_vcpu *vcpu, gpa_t addr, |
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unsigned int len, unsigned long val); |
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unsigned long vgic_mmio_read_enable(struct kvm_vcpu *vcpu, |
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gpa_t addr, unsigned int len); |
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void vgic_mmio_write_senable(struct kvm_vcpu *vcpu, |
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gpa_t addr, unsigned int len, |
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unsigned long val); |
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void vgic_mmio_write_cenable(struct kvm_vcpu *vcpu, |
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gpa_t addr, unsigned int len, |
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unsigned long val); |
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int vgic_uaccess_write_senable(struct kvm_vcpu *vcpu, |
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gpa_t addr, unsigned int len, |
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unsigned long val); |
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int vgic_uaccess_write_cenable(struct kvm_vcpu *vcpu, |
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gpa_t addr, unsigned int len, |
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unsigned long val); |
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unsigned long vgic_mmio_read_pending(struct kvm_vcpu *vcpu, |
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gpa_t addr, unsigned int len); |
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void vgic_mmio_write_spending(struct kvm_vcpu *vcpu, |
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gpa_t addr, unsigned int len, |
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unsigned long val); |
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void vgic_mmio_write_cpending(struct kvm_vcpu *vcpu, |
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gpa_t addr, unsigned int len, |
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unsigned long val); |
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int vgic_uaccess_write_spending(struct kvm_vcpu *vcpu, |
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gpa_t addr, unsigned int len, |
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unsigned long val); |
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int vgic_uaccess_write_cpending(struct kvm_vcpu *vcpu, |
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gpa_t addr, unsigned int len, |
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unsigned long val); |
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unsigned long vgic_mmio_read_active(struct kvm_vcpu *vcpu, |
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gpa_t addr, unsigned int len); |
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unsigned long vgic_uaccess_read_active(struct kvm_vcpu *vcpu, |
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gpa_t addr, unsigned int len); |
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void vgic_mmio_write_cactive(struct kvm_vcpu *vcpu, |
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gpa_t addr, unsigned int len, |
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unsigned long val); |
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void vgic_mmio_write_sactive(struct kvm_vcpu *vcpu, |
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gpa_t addr, unsigned int len, |
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unsigned long val); |
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int vgic_mmio_uaccess_write_cactive(struct kvm_vcpu *vcpu, |
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gpa_t addr, unsigned int len, |
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unsigned long val); |
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int vgic_mmio_uaccess_write_sactive(struct kvm_vcpu *vcpu, |
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gpa_t addr, unsigned int len, |
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unsigned long val); |
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unsigned long vgic_mmio_read_priority(struct kvm_vcpu *vcpu, |
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gpa_t addr, unsigned int len); |
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void vgic_mmio_write_priority(struct kvm_vcpu *vcpu, |
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gpa_t addr, unsigned int len, |
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unsigned long val); |
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unsigned long vgic_mmio_read_config(struct kvm_vcpu *vcpu, |
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gpa_t addr, unsigned int len); |
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void vgic_mmio_write_config(struct kvm_vcpu *vcpu, |
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gpa_t addr, unsigned int len, |
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unsigned long val); |
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int vgic_uaccess(struct kvm_vcpu *vcpu, struct vgic_io_device *dev, |
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bool is_write, int offset, u32 *val); |
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u64 vgic_read_irq_line_level_info(struct kvm_vcpu *vcpu, u32 intid); |
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void vgic_write_irq_line_level_info(struct kvm_vcpu *vcpu, u32 intid, |
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const u64 val); |
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unsigned int vgic_v2_init_dist_iodev(struct vgic_io_device *dev); |
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unsigned int vgic_v3_init_dist_iodev(struct vgic_io_device *dev); |
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u64 vgic_sanitise_outer_cacheability(u64 reg); |
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u64 vgic_sanitise_inner_cacheability(u64 reg); |
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u64 vgic_sanitise_shareability(u64 reg); |
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u64 vgic_sanitise_field(u64 reg, u64 field_mask, int field_shift, |
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u64 (*sanitise_fn)(u64)); |
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/* Find the proper register handler entry given a certain address offset */ |
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const struct vgic_register_region * |
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vgic_find_mmio_region(const struct vgic_register_region *regions, |
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int nr_regions, unsigned int offset); |
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#endif
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