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163 lines
3.9 KiB
163 lines
3.9 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (C) 2015 - ARM Ltd |
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* Author: Marc Zyngier <[email protected]> |
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*/ |
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#include <linux/irqflags.h> |
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#include <asm/kvm_hyp.h> |
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#include <asm/kvm_mmu.h> |
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#include <asm/tlbflush.h> |
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struct tlb_inv_context { |
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unsigned long flags; |
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u64 tcr; |
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u64 sctlr; |
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}; |
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static void __tlb_switch_to_guest(struct kvm_s2_mmu *mmu, |
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struct tlb_inv_context *cxt) |
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{ |
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u64 val; |
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local_irq_save(cxt->flags); |
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if (cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) { |
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/* |
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* For CPUs that are affected by ARM errata 1165522 or 1530923, |
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* we cannot trust stage-1 to be in a correct state at that |
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* point. Since we do not want to force a full load of the |
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* vcpu state, we prevent the EL1 page-table walker to |
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* allocate new TLBs. This is done by setting the EPD bits |
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* in the TCR_EL1 register. We also need to prevent it to |
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* allocate IPA->PA walks, so we enable the S1 MMU... |
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*/ |
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val = cxt->tcr = read_sysreg_el1(SYS_TCR); |
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val |= TCR_EPD1_MASK | TCR_EPD0_MASK; |
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write_sysreg_el1(val, SYS_TCR); |
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val = cxt->sctlr = read_sysreg_el1(SYS_SCTLR); |
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val |= SCTLR_ELx_M; |
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write_sysreg_el1(val, SYS_SCTLR); |
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} |
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/* |
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* With VHE enabled, we have HCR_EL2.{E2H,TGE} = {1,1}, and |
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* most TLB operations target EL2/EL0. In order to affect the |
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* guest TLBs (EL1/EL0), we need to change one of these two |
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* bits. Changing E2H is impossible (goodbye TTBR1_EL2), so |
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* let's flip TGE before executing the TLB operation. |
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* |
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* ARM erratum 1165522 requires some special handling (again), |
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* as we need to make sure both stages of translation are in |
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* place before clearing TGE. __load_guest_stage2() already |
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* has an ISB in order to deal with this. |
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*/ |
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__load_guest_stage2(mmu); |
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val = read_sysreg(hcr_el2); |
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val &= ~HCR_TGE; |
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write_sysreg(val, hcr_el2); |
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isb(); |
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} |
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static void __tlb_switch_to_host(struct tlb_inv_context *cxt) |
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{ |
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/* |
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* We're done with the TLB operation, let's restore the host's |
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* view of HCR_EL2. |
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*/ |
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write_sysreg(0, vttbr_el2); |
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write_sysreg(HCR_HOST_VHE_FLAGS, hcr_el2); |
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isb(); |
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if (cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) { |
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/* Restore the registers to what they were */ |
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write_sysreg_el1(cxt->tcr, SYS_TCR); |
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write_sysreg_el1(cxt->sctlr, SYS_SCTLR); |
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} |
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local_irq_restore(cxt->flags); |
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} |
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void __kvm_tlb_flush_vmid_ipa(struct kvm_s2_mmu *mmu, |
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phys_addr_t ipa, int level) |
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{ |
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struct tlb_inv_context cxt; |
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dsb(ishst); |
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/* Switch to requested VMID */ |
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__tlb_switch_to_guest(mmu, &cxt); |
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/* |
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* We could do so much better if we had the VA as well. |
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* Instead, we invalidate Stage-2 for this IPA, and the |
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* whole of Stage-1. Weep... |
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*/ |
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ipa >>= 12; |
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__tlbi_level(ipas2e1is, ipa, level); |
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/* |
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* We have to ensure completion of the invalidation at Stage-2, |
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* since a table walk on another CPU could refill a TLB with a |
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* complete (S1 + S2) walk based on the old Stage-2 mapping if |
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* the Stage-1 invalidation happened first. |
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*/ |
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dsb(ish); |
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__tlbi(vmalle1is); |
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dsb(ish); |
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isb(); |
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__tlb_switch_to_host(&cxt); |
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} |
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void __kvm_tlb_flush_vmid(struct kvm_s2_mmu *mmu) |
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{ |
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struct tlb_inv_context cxt; |
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dsb(ishst); |
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/* Switch to requested VMID */ |
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__tlb_switch_to_guest(mmu, &cxt); |
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__tlbi(vmalls12e1is); |
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dsb(ish); |
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isb(); |
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__tlb_switch_to_host(&cxt); |
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} |
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void __kvm_flush_cpu_context(struct kvm_s2_mmu *mmu) |
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{ |
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struct tlb_inv_context cxt; |
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/* Switch to requested VMID */ |
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__tlb_switch_to_guest(mmu, &cxt); |
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__tlbi(vmalle1); |
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asm volatile("ic iallu"); |
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dsb(nsh); |
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isb(); |
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__tlb_switch_to_host(&cxt); |
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} |
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void __kvm_flush_vm_context(void) |
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{ |
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dsb(ishst); |
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__tlbi(alle1is); |
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/* |
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* VIPT and PIPT caches are not affected by VMID, so no maintenance |
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* is necessary across a VMID rollover. |
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* |
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* VPIPT caches constrain lookup and maintenance to the active VMID, |
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* so we need to invalidate lines with a stale VMID to avoid an ABA |
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* race after multiple rollovers. |
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* |
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*/ |
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if (icache_is_vpipt()) |
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asm volatile("ic ialluis"); |
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dsb(ish); |
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}
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