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230 lines
5.7 KiB
230 lines
5.7 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (C) 2015 - ARM Ltd |
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* Author: Marc Zyngier <[email protected]> |
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*/ |
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#include <hyp/adjust_pc.h> |
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#include <hyp/switch.h> |
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#include <linux/arm-smccc.h> |
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#include <linux/kvm_host.h> |
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#include <linux/types.h> |
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#include <linux/jump_label.h> |
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#include <uapi/linux/psci.h> |
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#include <kvm/arm_psci.h> |
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#include <asm/barrier.h> |
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#include <asm/cpufeature.h> |
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#include <asm/kprobes.h> |
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#include <asm/kvm_asm.h> |
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#include <asm/kvm_emulate.h> |
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#include <asm/kvm_hyp.h> |
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#include <asm/kvm_mmu.h> |
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#include <asm/fpsimd.h> |
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#include <asm/debug-monitors.h> |
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#include <asm/processor.h> |
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#include <asm/thread_info.h> |
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const char __hyp_panic_string[] = "HYP panic:\nPS:%08llx PC:%016llx ESR:%08llx\nFAR:%016llx HPFAR:%016llx PAR:%016llx\nVCPU:%p\n"; |
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/* VHE specific context */ |
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DEFINE_PER_CPU(struct kvm_host_data, kvm_host_data); |
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DEFINE_PER_CPU(struct kvm_cpu_context, kvm_hyp_ctxt); |
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DEFINE_PER_CPU(unsigned long, kvm_hyp_vector); |
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static void __activate_traps(struct kvm_vcpu *vcpu) |
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{ |
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u64 val; |
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___activate_traps(vcpu); |
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val = read_sysreg(cpacr_el1); |
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val |= CPACR_EL1_TTA; |
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val &= ~CPACR_EL1_ZEN; |
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/* |
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* With VHE (HCR.E2H == 1), accesses to CPACR_EL1 are routed to |
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* CPTR_EL2. In general, CPACR_EL1 has the same layout as CPTR_EL2, |
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* except for some missing controls, such as TAM. |
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* In this case, CPTR_EL2.TAM has the same position with or without |
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* VHE (HCR.E2H == 1) which allows us to use here the CPTR_EL2.TAM |
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* shift value for trapping the AMU accesses. |
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*/ |
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val |= CPTR_EL2_TAM; |
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if (update_fp_enabled(vcpu)) { |
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if (vcpu_has_sve(vcpu)) |
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val |= CPACR_EL1_ZEN; |
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} else { |
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val &= ~CPACR_EL1_FPEN; |
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__activate_traps_fpsimd32(vcpu); |
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} |
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write_sysreg(val, cpacr_el1); |
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write_sysreg(__this_cpu_read(kvm_hyp_vector), vbar_el1); |
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} |
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NOKPROBE_SYMBOL(__activate_traps); |
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static void __deactivate_traps(struct kvm_vcpu *vcpu) |
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{ |
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extern char vectors[]; /* kernel exception vectors */ |
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___deactivate_traps(vcpu); |
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write_sysreg(HCR_HOST_VHE_FLAGS, hcr_el2); |
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/* |
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* ARM errata 1165522 and 1530923 require the actual execution of the |
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* above before we can switch to the EL2/EL0 translation regime used by |
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* the host. |
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*/ |
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asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_SPECULATIVE_AT)); |
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write_sysreg(CPACR_EL1_DEFAULT, cpacr_el1); |
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write_sysreg(vectors, vbar_el1); |
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} |
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NOKPROBE_SYMBOL(__deactivate_traps); |
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void activate_traps_vhe_load(struct kvm_vcpu *vcpu) |
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{ |
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__activate_traps_common(vcpu); |
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} |
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void deactivate_traps_vhe_put(void) |
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{ |
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u64 mdcr_el2 = read_sysreg(mdcr_el2); |
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mdcr_el2 &= MDCR_EL2_HPMN_MASK | |
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MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT | |
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MDCR_EL2_TPMS; |
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write_sysreg(mdcr_el2, mdcr_el2); |
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__deactivate_traps_common(); |
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} |
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/* Switch to the guest for VHE systems running in EL2 */ |
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static int __kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu) |
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{ |
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struct kvm_cpu_context *host_ctxt; |
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struct kvm_cpu_context *guest_ctxt; |
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u64 exit_code; |
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host_ctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt; |
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host_ctxt->__hyp_running_vcpu = vcpu; |
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guest_ctxt = &vcpu->arch.ctxt; |
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sysreg_save_host_state_vhe(host_ctxt); |
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/* |
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* ARM erratum 1165522 requires us to configure both stage 1 and |
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* stage 2 translation for the guest context before we clear |
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* HCR_EL2.TGE. |
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* |
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* We have already configured the guest's stage 1 translation in |
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* kvm_vcpu_load_sysregs_vhe above. We must now call |
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* __load_guest_stage2 before __activate_traps, because |
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* __load_guest_stage2 configures stage 2 translation, and |
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* __activate_traps clear HCR_EL2.TGE (among other things). |
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*/ |
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__load_guest_stage2(vcpu->arch.hw_mmu); |
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__activate_traps(vcpu); |
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__adjust_pc(vcpu); |
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sysreg_restore_guest_state_vhe(guest_ctxt); |
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__debug_switch_to_guest(vcpu); |
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do { |
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/* Jump in the fire! */ |
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exit_code = __guest_enter(vcpu); |
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/* And we're baaack! */ |
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} while (fixup_guest_exit(vcpu, &exit_code)); |
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sysreg_save_guest_state_vhe(guest_ctxt); |
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__deactivate_traps(vcpu); |
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sysreg_restore_host_state_vhe(host_ctxt); |
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if (vcpu->arch.flags & KVM_ARM64_FP_ENABLED) |
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__fpsimd_save_fpexc32(vcpu); |
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__debug_switch_to_host(vcpu); |
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return exit_code; |
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} |
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NOKPROBE_SYMBOL(__kvm_vcpu_run_vhe); |
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int __kvm_vcpu_run(struct kvm_vcpu *vcpu) |
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{ |
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int ret; |
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local_daif_mask(); |
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/* |
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* Having IRQs masked via PMR when entering the guest means the GIC |
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* will not signal the CPU of interrupts of lower priority, and the |
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* only way to get out will be via guest exceptions. |
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* Naturally, we want to avoid this. |
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* |
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* local_daif_mask() already sets GIC_PRIO_PSR_I_SET, we just need a |
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* dsb to ensure the redistributor is forwards EL2 IRQs to the CPU. |
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*/ |
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pmr_sync(); |
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ret = __kvm_vcpu_run_vhe(vcpu); |
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/* |
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* local_daif_restore() takes care to properly restore PSTATE.DAIF |
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* and the GIC PMR if the host is using IRQ priorities. |
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*/ |
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local_daif_restore(DAIF_PROCCTX_NOIRQ); |
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/* |
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* When we exit from the guest we change a number of CPU configuration |
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* parameters, such as traps. Make sure these changes take effect |
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* before running the host or additional guests. |
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*/ |
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isb(); |
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return ret; |
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} |
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static void __hyp_call_panic(u64 spsr, u64 elr, u64 par) |
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{ |
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struct kvm_cpu_context *host_ctxt; |
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struct kvm_vcpu *vcpu; |
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host_ctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt; |
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vcpu = host_ctxt->__hyp_running_vcpu; |
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__deactivate_traps(vcpu); |
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sysreg_restore_host_state_vhe(host_ctxt); |
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panic(__hyp_panic_string, |
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spsr, elr, |
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read_sysreg_el2(SYS_ESR), read_sysreg_el2(SYS_FAR), |
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read_sysreg(hpfar_el2), par, vcpu); |
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} |
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NOKPROBE_SYMBOL(__hyp_call_panic); |
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void __noreturn hyp_panic(void) |
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{ |
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u64 spsr = read_sysreg_el2(SYS_SPSR); |
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u64 elr = read_sysreg_el2(SYS_ELR); |
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u64 par = read_sysreg_par(); |
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__hyp_call_panic(spsr, elr, par); |
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unreachable(); |
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} |
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asmlinkage void kvm_unexpected_el2_exception(void) |
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{ |
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return __kvm_unexpected_el2_exception(); |
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}
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