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1031 lines
26 KiB
1031 lines
26 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* HW_breakpoint: a unified kernel/user-space hardware breakpoint facility, |
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* using the CPU's debug registers. |
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* |
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* Copyright (C) 2012 ARM Limited |
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* Author: Will Deacon <[email protected]> |
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*/ |
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|
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#define pr_fmt(fmt) "hw-breakpoint: " fmt |
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|
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#include <linux/compat.h> |
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#include <linux/cpu_pm.h> |
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#include <linux/errno.h> |
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#include <linux/hw_breakpoint.h> |
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#include <linux/kprobes.h> |
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#include <linux/perf_event.h> |
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#include <linux/ptrace.h> |
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#include <linux/smp.h> |
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#include <linux/uaccess.h> |
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|
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#include <asm/current.h> |
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#include <asm/debug-monitors.h> |
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#include <asm/hw_breakpoint.h> |
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#include <asm/traps.h> |
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#include <asm/cputype.h> |
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#include <asm/system_misc.h> |
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|
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/* Breakpoint currently in use for each BRP. */ |
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static DEFINE_PER_CPU(struct perf_event *, bp_on_reg[ARM_MAX_BRP]); |
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|
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/* Watchpoint currently in use for each WRP. */ |
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static DEFINE_PER_CPU(struct perf_event *, wp_on_reg[ARM_MAX_WRP]); |
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|
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/* Currently stepping a per-CPU kernel breakpoint. */ |
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static DEFINE_PER_CPU(int, stepping_kernel_bp); |
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|
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/* Number of BRP/WRP registers on this CPU. */ |
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static int core_num_brps; |
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static int core_num_wrps; |
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|
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int hw_breakpoint_slots(int type) |
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{ |
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/* |
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* We can be called early, so don't rely on |
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* our static variables being initialised. |
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*/ |
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switch (type) { |
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case TYPE_INST: |
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return get_num_brps(); |
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case TYPE_DATA: |
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return get_num_wrps(); |
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default: |
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pr_warn("unknown slot type: %d\n", type); |
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return 0; |
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} |
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} |
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#define READ_WB_REG_CASE(OFF, N, REG, VAL) \ |
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case (OFF + N): \ |
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AARCH64_DBG_READ(N, REG, VAL); \ |
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break |
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|
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#define WRITE_WB_REG_CASE(OFF, N, REG, VAL) \ |
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case (OFF + N): \ |
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AARCH64_DBG_WRITE(N, REG, VAL); \ |
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break |
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|
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#define GEN_READ_WB_REG_CASES(OFF, REG, VAL) \ |
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READ_WB_REG_CASE(OFF, 0, REG, VAL); \ |
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READ_WB_REG_CASE(OFF, 1, REG, VAL); \ |
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READ_WB_REG_CASE(OFF, 2, REG, VAL); \ |
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READ_WB_REG_CASE(OFF, 3, REG, VAL); \ |
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READ_WB_REG_CASE(OFF, 4, REG, VAL); \ |
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READ_WB_REG_CASE(OFF, 5, REG, VAL); \ |
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READ_WB_REG_CASE(OFF, 6, REG, VAL); \ |
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READ_WB_REG_CASE(OFF, 7, REG, VAL); \ |
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READ_WB_REG_CASE(OFF, 8, REG, VAL); \ |
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READ_WB_REG_CASE(OFF, 9, REG, VAL); \ |
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READ_WB_REG_CASE(OFF, 10, REG, VAL); \ |
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READ_WB_REG_CASE(OFF, 11, REG, VAL); \ |
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READ_WB_REG_CASE(OFF, 12, REG, VAL); \ |
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READ_WB_REG_CASE(OFF, 13, REG, VAL); \ |
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READ_WB_REG_CASE(OFF, 14, REG, VAL); \ |
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READ_WB_REG_CASE(OFF, 15, REG, VAL) |
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|
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#define GEN_WRITE_WB_REG_CASES(OFF, REG, VAL) \ |
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WRITE_WB_REG_CASE(OFF, 0, REG, VAL); \ |
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WRITE_WB_REG_CASE(OFF, 1, REG, VAL); \ |
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WRITE_WB_REG_CASE(OFF, 2, REG, VAL); \ |
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WRITE_WB_REG_CASE(OFF, 3, REG, VAL); \ |
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WRITE_WB_REG_CASE(OFF, 4, REG, VAL); \ |
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WRITE_WB_REG_CASE(OFF, 5, REG, VAL); \ |
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WRITE_WB_REG_CASE(OFF, 6, REG, VAL); \ |
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WRITE_WB_REG_CASE(OFF, 7, REG, VAL); \ |
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WRITE_WB_REG_CASE(OFF, 8, REG, VAL); \ |
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WRITE_WB_REG_CASE(OFF, 9, REG, VAL); \ |
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WRITE_WB_REG_CASE(OFF, 10, REG, VAL); \ |
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WRITE_WB_REG_CASE(OFF, 11, REG, VAL); \ |
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WRITE_WB_REG_CASE(OFF, 12, REG, VAL); \ |
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WRITE_WB_REG_CASE(OFF, 13, REG, VAL); \ |
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WRITE_WB_REG_CASE(OFF, 14, REG, VAL); \ |
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WRITE_WB_REG_CASE(OFF, 15, REG, VAL) |
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|
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static u64 read_wb_reg(int reg, int n) |
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{ |
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u64 val = 0; |
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|
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switch (reg + n) { |
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GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_BVR, AARCH64_DBG_REG_NAME_BVR, val); |
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GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_BCR, AARCH64_DBG_REG_NAME_BCR, val); |
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GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_WVR, AARCH64_DBG_REG_NAME_WVR, val); |
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GEN_READ_WB_REG_CASES(AARCH64_DBG_REG_WCR, AARCH64_DBG_REG_NAME_WCR, val); |
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default: |
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pr_warn("attempt to read from unknown breakpoint register %d\n", n); |
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} |
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|
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return val; |
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} |
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NOKPROBE_SYMBOL(read_wb_reg); |
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|
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static void write_wb_reg(int reg, int n, u64 val) |
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{ |
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switch (reg + n) { |
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GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_BVR, AARCH64_DBG_REG_NAME_BVR, val); |
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GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_BCR, AARCH64_DBG_REG_NAME_BCR, val); |
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GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_WVR, AARCH64_DBG_REG_NAME_WVR, val); |
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GEN_WRITE_WB_REG_CASES(AARCH64_DBG_REG_WCR, AARCH64_DBG_REG_NAME_WCR, val); |
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default: |
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pr_warn("attempt to write to unknown breakpoint register %d\n", n); |
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} |
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isb(); |
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} |
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NOKPROBE_SYMBOL(write_wb_reg); |
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|
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/* |
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* Convert a breakpoint privilege level to the corresponding exception |
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* level. |
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*/ |
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static enum dbg_active_el debug_exception_level(int privilege) |
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{ |
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switch (privilege) { |
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case AARCH64_BREAKPOINT_EL0: |
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return DBG_ACTIVE_EL0; |
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case AARCH64_BREAKPOINT_EL1: |
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return DBG_ACTIVE_EL1; |
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default: |
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pr_warn("invalid breakpoint privilege level %d\n", privilege); |
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return -EINVAL; |
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} |
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} |
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NOKPROBE_SYMBOL(debug_exception_level); |
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|
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enum hw_breakpoint_ops { |
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HW_BREAKPOINT_INSTALL, |
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HW_BREAKPOINT_UNINSTALL, |
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HW_BREAKPOINT_RESTORE |
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}; |
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|
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static int is_compat_bp(struct perf_event *bp) |
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{ |
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struct task_struct *tsk = bp->hw.target; |
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|
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/* |
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* tsk can be NULL for per-cpu (non-ptrace) breakpoints. |
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* In this case, use the native interface, since we don't have |
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* the notion of a "compat CPU" and could end up relying on |
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* deprecated behaviour if we use unaligned watchpoints in |
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* AArch64 state. |
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*/ |
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return tsk && is_compat_thread(task_thread_info(tsk)); |
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} |
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|
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/** |
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* hw_breakpoint_slot_setup - Find and setup a perf slot according to |
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* operations |
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* |
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* @slots: pointer to array of slots |
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* @max_slots: max number of slots |
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* @bp: perf_event to setup |
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* @ops: operation to be carried out on the slot |
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* |
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* Return: |
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* slot index on success |
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* -ENOSPC if no slot is available/matches |
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* -EINVAL on wrong operations parameter |
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*/ |
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static int hw_breakpoint_slot_setup(struct perf_event **slots, int max_slots, |
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struct perf_event *bp, |
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enum hw_breakpoint_ops ops) |
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{ |
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int i; |
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struct perf_event **slot; |
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|
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for (i = 0; i < max_slots; ++i) { |
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slot = &slots[i]; |
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switch (ops) { |
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case HW_BREAKPOINT_INSTALL: |
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if (!*slot) { |
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*slot = bp; |
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return i; |
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} |
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break; |
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case HW_BREAKPOINT_UNINSTALL: |
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if (*slot == bp) { |
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*slot = NULL; |
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return i; |
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} |
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break; |
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case HW_BREAKPOINT_RESTORE: |
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if (*slot == bp) |
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return i; |
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break; |
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default: |
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pr_warn_once("Unhandled hw breakpoint ops %d\n", ops); |
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return -EINVAL; |
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} |
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} |
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return -ENOSPC; |
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} |
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|
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static int hw_breakpoint_control(struct perf_event *bp, |
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enum hw_breakpoint_ops ops) |
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{ |
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struct arch_hw_breakpoint *info = counter_arch_bp(bp); |
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struct perf_event **slots; |
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struct debug_info *debug_info = ¤t->thread.debug; |
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int i, max_slots, ctrl_reg, val_reg, reg_enable; |
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enum dbg_active_el dbg_el = debug_exception_level(info->ctrl.privilege); |
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u32 ctrl; |
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|
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if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) { |
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/* Breakpoint */ |
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ctrl_reg = AARCH64_DBG_REG_BCR; |
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val_reg = AARCH64_DBG_REG_BVR; |
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slots = this_cpu_ptr(bp_on_reg); |
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max_slots = core_num_brps; |
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reg_enable = !debug_info->bps_disabled; |
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} else { |
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/* Watchpoint */ |
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ctrl_reg = AARCH64_DBG_REG_WCR; |
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val_reg = AARCH64_DBG_REG_WVR; |
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slots = this_cpu_ptr(wp_on_reg); |
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max_slots = core_num_wrps; |
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reg_enable = !debug_info->wps_disabled; |
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} |
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|
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i = hw_breakpoint_slot_setup(slots, max_slots, bp, ops); |
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|
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if (WARN_ONCE(i < 0, "Can't find any breakpoint slot")) |
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return i; |
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|
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switch (ops) { |
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case HW_BREAKPOINT_INSTALL: |
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/* |
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* Ensure debug monitors are enabled at the correct exception |
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* level. |
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*/ |
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enable_debug_monitors(dbg_el); |
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fallthrough; |
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case HW_BREAKPOINT_RESTORE: |
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/* Setup the address register. */ |
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write_wb_reg(val_reg, i, info->address); |
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|
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/* Setup the control register. */ |
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ctrl = encode_ctrl_reg(info->ctrl); |
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write_wb_reg(ctrl_reg, i, |
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reg_enable ? ctrl | 0x1 : ctrl & ~0x1); |
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break; |
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case HW_BREAKPOINT_UNINSTALL: |
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/* Reset the control register. */ |
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write_wb_reg(ctrl_reg, i, 0); |
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|
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/* |
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* Release the debug monitors for the correct exception |
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* level. |
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*/ |
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disable_debug_monitors(dbg_el); |
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break; |
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} |
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return 0; |
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} |
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/* |
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* Install a perf counter breakpoint. |
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*/ |
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int arch_install_hw_breakpoint(struct perf_event *bp) |
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{ |
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return hw_breakpoint_control(bp, HW_BREAKPOINT_INSTALL); |
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} |
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void arch_uninstall_hw_breakpoint(struct perf_event *bp) |
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{ |
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hw_breakpoint_control(bp, HW_BREAKPOINT_UNINSTALL); |
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} |
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static int get_hbp_len(u8 hbp_len) |
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{ |
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unsigned int len_in_bytes = 0; |
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|
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switch (hbp_len) { |
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case ARM_BREAKPOINT_LEN_1: |
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len_in_bytes = 1; |
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break; |
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case ARM_BREAKPOINT_LEN_2: |
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len_in_bytes = 2; |
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break; |
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case ARM_BREAKPOINT_LEN_3: |
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len_in_bytes = 3; |
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break; |
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case ARM_BREAKPOINT_LEN_4: |
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len_in_bytes = 4; |
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break; |
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case ARM_BREAKPOINT_LEN_5: |
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len_in_bytes = 5; |
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break; |
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case ARM_BREAKPOINT_LEN_6: |
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len_in_bytes = 6; |
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break; |
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case ARM_BREAKPOINT_LEN_7: |
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len_in_bytes = 7; |
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break; |
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case ARM_BREAKPOINT_LEN_8: |
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len_in_bytes = 8; |
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break; |
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} |
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return len_in_bytes; |
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} |
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|
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/* |
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* Check whether bp virtual address is in kernel space. |
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*/ |
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int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw) |
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{ |
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unsigned int len; |
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unsigned long va; |
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|
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va = hw->address; |
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len = get_hbp_len(hw->ctrl.len); |
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|
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return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE); |
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} |
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|
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/* |
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* Extract generic type and length encodings from an arch_hw_breakpoint_ctrl. |
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* Hopefully this will disappear when ptrace can bypass the conversion |
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* to generic breakpoint descriptions. |
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*/ |
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int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl, |
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int *gen_len, int *gen_type, int *offset) |
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{ |
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/* Type */ |
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switch (ctrl.type) { |
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case ARM_BREAKPOINT_EXECUTE: |
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*gen_type = HW_BREAKPOINT_X; |
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break; |
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case ARM_BREAKPOINT_LOAD: |
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*gen_type = HW_BREAKPOINT_R; |
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break; |
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case ARM_BREAKPOINT_STORE: |
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*gen_type = HW_BREAKPOINT_W; |
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break; |
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case ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE: |
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*gen_type = HW_BREAKPOINT_RW; |
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break; |
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default: |
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return -EINVAL; |
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} |
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|
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if (!ctrl.len) |
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return -EINVAL; |
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*offset = __ffs(ctrl.len); |
|
|
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/* Len */ |
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switch (ctrl.len >> *offset) { |
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case ARM_BREAKPOINT_LEN_1: |
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*gen_len = HW_BREAKPOINT_LEN_1; |
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break; |
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case ARM_BREAKPOINT_LEN_2: |
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*gen_len = HW_BREAKPOINT_LEN_2; |
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break; |
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case ARM_BREAKPOINT_LEN_3: |
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*gen_len = HW_BREAKPOINT_LEN_3; |
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break; |
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case ARM_BREAKPOINT_LEN_4: |
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*gen_len = HW_BREAKPOINT_LEN_4; |
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break; |
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case ARM_BREAKPOINT_LEN_5: |
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*gen_len = HW_BREAKPOINT_LEN_5; |
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break; |
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case ARM_BREAKPOINT_LEN_6: |
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*gen_len = HW_BREAKPOINT_LEN_6; |
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break; |
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case ARM_BREAKPOINT_LEN_7: |
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*gen_len = HW_BREAKPOINT_LEN_7; |
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break; |
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case ARM_BREAKPOINT_LEN_8: |
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*gen_len = HW_BREAKPOINT_LEN_8; |
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break; |
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default: |
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return -EINVAL; |
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} |
|
|
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return 0; |
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} |
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|
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/* |
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* Construct an arch_hw_breakpoint from a perf_event. |
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*/ |
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static int arch_build_bp_info(struct perf_event *bp, |
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const struct perf_event_attr *attr, |
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struct arch_hw_breakpoint *hw) |
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{ |
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/* Type */ |
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switch (attr->bp_type) { |
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case HW_BREAKPOINT_X: |
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hw->ctrl.type = ARM_BREAKPOINT_EXECUTE; |
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break; |
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case HW_BREAKPOINT_R: |
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hw->ctrl.type = ARM_BREAKPOINT_LOAD; |
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break; |
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case HW_BREAKPOINT_W: |
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hw->ctrl.type = ARM_BREAKPOINT_STORE; |
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break; |
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case HW_BREAKPOINT_RW: |
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hw->ctrl.type = ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE; |
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break; |
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default: |
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return -EINVAL; |
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} |
|
|
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/* Len */ |
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switch (attr->bp_len) { |
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case HW_BREAKPOINT_LEN_1: |
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hw->ctrl.len = ARM_BREAKPOINT_LEN_1; |
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break; |
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case HW_BREAKPOINT_LEN_2: |
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hw->ctrl.len = ARM_BREAKPOINT_LEN_2; |
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break; |
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case HW_BREAKPOINT_LEN_3: |
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hw->ctrl.len = ARM_BREAKPOINT_LEN_3; |
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break; |
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case HW_BREAKPOINT_LEN_4: |
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hw->ctrl.len = ARM_BREAKPOINT_LEN_4; |
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break; |
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case HW_BREAKPOINT_LEN_5: |
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hw->ctrl.len = ARM_BREAKPOINT_LEN_5; |
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break; |
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case HW_BREAKPOINT_LEN_6: |
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hw->ctrl.len = ARM_BREAKPOINT_LEN_6; |
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break; |
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case HW_BREAKPOINT_LEN_7: |
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hw->ctrl.len = ARM_BREAKPOINT_LEN_7; |
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break; |
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case HW_BREAKPOINT_LEN_8: |
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hw->ctrl.len = ARM_BREAKPOINT_LEN_8; |
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break; |
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default: |
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return -EINVAL; |
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} |
|
|
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/* |
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* On AArch64, we only permit breakpoints of length 4, whereas |
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* AArch32 also requires breakpoints of length 2 for Thumb. |
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* Watchpoints can be of length 1, 2, 4 or 8 bytes. |
|
*/ |
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if (hw->ctrl.type == ARM_BREAKPOINT_EXECUTE) { |
|
if (is_compat_bp(bp)) { |
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if (hw->ctrl.len != ARM_BREAKPOINT_LEN_2 && |
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hw->ctrl.len != ARM_BREAKPOINT_LEN_4) |
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return -EINVAL; |
|
} else if (hw->ctrl.len != ARM_BREAKPOINT_LEN_4) { |
|
/* |
|
* FIXME: Some tools (I'm looking at you perf) assume |
|
* that breakpoints should be sizeof(long). This |
|
* is nonsense. For now, we fix up the parameter |
|
* but we should probably return -EINVAL instead. |
|
*/ |
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hw->ctrl.len = ARM_BREAKPOINT_LEN_4; |
|
} |
|
} |
|
|
|
/* Address */ |
|
hw->address = attr->bp_addr; |
|
|
|
/* |
|
* Privilege |
|
* Note that we disallow combined EL0/EL1 breakpoints because |
|
* that would complicate the stepping code. |
|
*/ |
|
if (arch_check_bp_in_kernelspace(hw)) |
|
hw->ctrl.privilege = AARCH64_BREAKPOINT_EL1; |
|
else |
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hw->ctrl.privilege = AARCH64_BREAKPOINT_EL0; |
|
|
|
/* Enabled? */ |
|
hw->ctrl.enabled = !attr->disabled; |
|
|
|
return 0; |
|
} |
|
|
|
/* |
|
* Validate the arch-specific HW Breakpoint register settings. |
|
*/ |
|
int hw_breakpoint_arch_parse(struct perf_event *bp, |
|
const struct perf_event_attr *attr, |
|
struct arch_hw_breakpoint *hw) |
|
{ |
|
int ret; |
|
u64 alignment_mask, offset; |
|
|
|
/* Build the arch_hw_breakpoint. */ |
|
ret = arch_build_bp_info(bp, attr, hw); |
|
if (ret) |
|
return ret; |
|
|
|
/* |
|
* Check address alignment. |
|
* We don't do any clever alignment correction for watchpoints |
|
* because using 64-bit unaligned addresses is deprecated for |
|
* AArch64. |
|
* |
|
* AArch32 tasks expect some simple alignment fixups, so emulate |
|
* that here. |
|
*/ |
|
if (is_compat_bp(bp)) { |
|
if (hw->ctrl.len == ARM_BREAKPOINT_LEN_8) |
|
alignment_mask = 0x7; |
|
else |
|
alignment_mask = 0x3; |
|
offset = hw->address & alignment_mask; |
|
switch (offset) { |
|
case 0: |
|
/* Aligned */ |
|
break; |
|
case 1: |
|
case 2: |
|
/* Allow halfword watchpoints and breakpoints. */ |
|
if (hw->ctrl.len == ARM_BREAKPOINT_LEN_2) |
|
break; |
|
|
|
fallthrough; |
|
case 3: |
|
/* Allow single byte watchpoint. */ |
|
if (hw->ctrl.len == ARM_BREAKPOINT_LEN_1) |
|
break; |
|
|
|
fallthrough; |
|
default: |
|
return -EINVAL; |
|
} |
|
} else { |
|
if (hw->ctrl.type == ARM_BREAKPOINT_EXECUTE) |
|
alignment_mask = 0x3; |
|
else |
|
alignment_mask = 0x7; |
|
offset = hw->address & alignment_mask; |
|
} |
|
|
|
hw->address &= ~alignment_mask; |
|
hw->ctrl.len <<= offset; |
|
|
|
/* |
|
* Disallow per-task kernel breakpoints since these would |
|
* complicate the stepping code. |
|
*/ |
|
if (hw->ctrl.privilege == AARCH64_BREAKPOINT_EL1 && bp->hw.target) |
|
return -EINVAL; |
|
|
|
return 0; |
|
} |
|
|
|
/* |
|
* Enable/disable all of the breakpoints active at the specified |
|
* exception level at the register level. |
|
* This is used when single-stepping after a breakpoint exception. |
|
*/ |
|
static void toggle_bp_registers(int reg, enum dbg_active_el el, int enable) |
|
{ |
|
int i, max_slots, privilege; |
|
u32 ctrl; |
|
struct perf_event **slots; |
|
|
|
switch (reg) { |
|
case AARCH64_DBG_REG_BCR: |
|
slots = this_cpu_ptr(bp_on_reg); |
|
max_slots = core_num_brps; |
|
break; |
|
case AARCH64_DBG_REG_WCR: |
|
slots = this_cpu_ptr(wp_on_reg); |
|
max_slots = core_num_wrps; |
|
break; |
|
default: |
|
return; |
|
} |
|
|
|
for (i = 0; i < max_slots; ++i) { |
|
if (!slots[i]) |
|
continue; |
|
|
|
privilege = counter_arch_bp(slots[i])->ctrl.privilege; |
|
if (debug_exception_level(privilege) != el) |
|
continue; |
|
|
|
ctrl = read_wb_reg(reg, i); |
|
if (enable) |
|
ctrl |= 0x1; |
|
else |
|
ctrl &= ~0x1; |
|
write_wb_reg(reg, i, ctrl); |
|
} |
|
} |
|
NOKPROBE_SYMBOL(toggle_bp_registers); |
|
|
|
/* |
|
* Debug exception handlers. |
|
*/ |
|
static int breakpoint_handler(unsigned long unused, unsigned int esr, |
|
struct pt_regs *regs) |
|
{ |
|
int i, step = 0, *kernel_step; |
|
u32 ctrl_reg; |
|
u64 addr, val; |
|
struct perf_event *bp, **slots; |
|
struct debug_info *debug_info; |
|
struct arch_hw_breakpoint_ctrl ctrl; |
|
|
|
slots = this_cpu_ptr(bp_on_reg); |
|
addr = instruction_pointer(regs); |
|
debug_info = ¤t->thread.debug; |
|
|
|
for (i = 0; i < core_num_brps; ++i) { |
|
rcu_read_lock(); |
|
|
|
bp = slots[i]; |
|
|
|
if (bp == NULL) |
|
goto unlock; |
|
|
|
/* Check if the breakpoint value matches. */ |
|
val = read_wb_reg(AARCH64_DBG_REG_BVR, i); |
|
if (val != (addr & ~0x3)) |
|
goto unlock; |
|
|
|
/* Possible match, check the byte address select to confirm. */ |
|
ctrl_reg = read_wb_reg(AARCH64_DBG_REG_BCR, i); |
|
decode_ctrl_reg(ctrl_reg, &ctrl); |
|
if (!((1 << (addr & 0x3)) & ctrl.len)) |
|
goto unlock; |
|
|
|
counter_arch_bp(bp)->trigger = addr; |
|
perf_bp_event(bp, regs); |
|
|
|
/* Do we need to handle the stepping? */ |
|
if (is_default_overflow_handler(bp)) |
|
step = 1; |
|
unlock: |
|
rcu_read_unlock(); |
|
} |
|
|
|
if (!step) |
|
return 0; |
|
|
|
if (user_mode(regs)) { |
|
debug_info->bps_disabled = 1; |
|
toggle_bp_registers(AARCH64_DBG_REG_BCR, DBG_ACTIVE_EL0, 0); |
|
|
|
/* If we're already stepping a watchpoint, just return. */ |
|
if (debug_info->wps_disabled) |
|
return 0; |
|
|
|
if (test_thread_flag(TIF_SINGLESTEP)) |
|
debug_info->suspended_step = 1; |
|
else |
|
user_enable_single_step(current); |
|
} else { |
|
toggle_bp_registers(AARCH64_DBG_REG_BCR, DBG_ACTIVE_EL1, 0); |
|
kernel_step = this_cpu_ptr(&stepping_kernel_bp); |
|
|
|
if (*kernel_step != ARM_KERNEL_STEP_NONE) |
|
return 0; |
|
|
|
if (kernel_active_single_step()) { |
|
*kernel_step = ARM_KERNEL_STEP_SUSPEND; |
|
} else { |
|
*kernel_step = ARM_KERNEL_STEP_ACTIVE; |
|
kernel_enable_single_step(regs); |
|
} |
|
} |
|
|
|
return 0; |
|
} |
|
NOKPROBE_SYMBOL(breakpoint_handler); |
|
|
|
/* |
|
* Arm64 hardware does not always report a watchpoint hit address that matches |
|
* one of the watchpoints set. It can also report an address "near" the |
|
* watchpoint if a single instruction access both watched and unwatched |
|
* addresses. There is no straight-forward way, short of disassembling the |
|
* offending instruction, to map that address back to the watchpoint. This |
|
* function computes the distance of the memory access from the watchpoint as a |
|
* heuristic for the likelyhood that a given access triggered the watchpoint. |
|
* |
|
* See Section D2.10.5 "Determining the memory location that caused a Watchpoint |
|
* exception" of ARMv8 Architecture Reference Manual for details. |
|
* |
|
* The function returns the distance of the address from the bytes watched by |
|
* the watchpoint. In case of an exact match, it returns 0. |
|
*/ |
|
static u64 get_distance_from_watchpoint(unsigned long addr, u64 val, |
|
struct arch_hw_breakpoint_ctrl *ctrl) |
|
{ |
|
u64 wp_low, wp_high; |
|
u32 lens, lene; |
|
|
|
addr = untagged_addr(addr); |
|
|
|
lens = __ffs(ctrl->len); |
|
lene = __fls(ctrl->len); |
|
|
|
wp_low = val + lens; |
|
wp_high = val + lene; |
|
if (addr < wp_low) |
|
return wp_low - addr; |
|
else if (addr > wp_high) |
|
return addr - wp_high; |
|
else |
|
return 0; |
|
} |
|
|
|
static int watchpoint_report(struct perf_event *wp, unsigned long addr, |
|
struct pt_regs *regs) |
|
{ |
|
int step = is_default_overflow_handler(wp); |
|
struct arch_hw_breakpoint *info = counter_arch_bp(wp); |
|
|
|
info->trigger = addr; |
|
|
|
/* |
|
* If we triggered a user watchpoint from a uaccess routine, then |
|
* handle the stepping ourselves since userspace really can't help |
|
* us with this. |
|
*/ |
|
if (!user_mode(regs) && info->ctrl.privilege == AARCH64_BREAKPOINT_EL0) |
|
step = 1; |
|
else |
|
perf_bp_event(wp, regs); |
|
|
|
return step; |
|
} |
|
|
|
static int watchpoint_handler(unsigned long addr, unsigned int esr, |
|
struct pt_regs *regs) |
|
{ |
|
int i, step = 0, *kernel_step, access, closest_match = 0; |
|
u64 min_dist = -1, dist; |
|
u32 ctrl_reg; |
|
u64 val; |
|
struct perf_event *wp, **slots; |
|
struct debug_info *debug_info; |
|
struct arch_hw_breakpoint_ctrl ctrl; |
|
|
|
slots = this_cpu_ptr(wp_on_reg); |
|
debug_info = ¤t->thread.debug; |
|
|
|
/* |
|
* Find all watchpoints that match the reported address. If no exact |
|
* match is found. Attribute the hit to the closest watchpoint. |
|
*/ |
|
rcu_read_lock(); |
|
for (i = 0; i < core_num_wrps; ++i) { |
|
wp = slots[i]; |
|
if (wp == NULL) |
|
continue; |
|
|
|
/* |
|
* Check that the access type matches. |
|
* 0 => load, otherwise => store |
|
*/ |
|
access = (esr & AARCH64_ESR_ACCESS_MASK) ? HW_BREAKPOINT_W : |
|
HW_BREAKPOINT_R; |
|
if (!(access & hw_breakpoint_type(wp))) |
|
continue; |
|
|
|
/* Check if the watchpoint value and byte select match. */ |
|
val = read_wb_reg(AARCH64_DBG_REG_WVR, i); |
|
ctrl_reg = read_wb_reg(AARCH64_DBG_REG_WCR, i); |
|
decode_ctrl_reg(ctrl_reg, &ctrl); |
|
dist = get_distance_from_watchpoint(addr, val, &ctrl); |
|
if (dist < min_dist) { |
|
min_dist = dist; |
|
closest_match = i; |
|
} |
|
/* Is this an exact match? */ |
|
if (dist != 0) |
|
continue; |
|
|
|
step = watchpoint_report(wp, addr, regs); |
|
} |
|
|
|
/* No exact match found? */ |
|
if (min_dist > 0 && min_dist != -1) |
|
step = watchpoint_report(slots[closest_match], addr, regs); |
|
|
|
rcu_read_unlock(); |
|
|
|
if (!step) |
|
return 0; |
|
|
|
/* |
|
* We always disable EL0 watchpoints because the kernel can |
|
* cause these to fire via an unprivileged access. |
|
*/ |
|
toggle_bp_registers(AARCH64_DBG_REG_WCR, DBG_ACTIVE_EL0, 0); |
|
|
|
if (user_mode(regs)) { |
|
debug_info->wps_disabled = 1; |
|
|
|
/* If we're already stepping a breakpoint, just return. */ |
|
if (debug_info->bps_disabled) |
|
return 0; |
|
|
|
if (test_thread_flag(TIF_SINGLESTEP)) |
|
debug_info->suspended_step = 1; |
|
else |
|
user_enable_single_step(current); |
|
} else { |
|
toggle_bp_registers(AARCH64_DBG_REG_WCR, DBG_ACTIVE_EL1, 0); |
|
kernel_step = this_cpu_ptr(&stepping_kernel_bp); |
|
|
|
if (*kernel_step != ARM_KERNEL_STEP_NONE) |
|
return 0; |
|
|
|
if (kernel_active_single_step()) { |
|
*kernel_step = ARM_KERNEL_STEP_SUSPEND; |
|
} else { |
|
*kernel_step = ARM_KERNEL_STEP_ACTIVE; |
|
kernel_enable_single_step(regs); |
|
} |
|
} |
|
|
|
return 0; |
|
} |
|
NOKPROBE_SYMBOL(watchpoint_handler); |
|
|
|
/* |
|
* Handle single-step exception. |
|
*/ |
|
int reinstall_suspended_bps(struct pt_regs *regs) |
|
{ |
|
struct debug_info *debug_info = ¤t->thread.debug; |
|
int handled_exception = 0, *kernel_step; |
|
|
|
kernel_step = this_cpu_ptr(&stepping_kernel_bp); |
|
|
|
/* |
|
* Called from single-step exception handler. |
|
* Return 0 if execution can resume, 1 if a SIGTRAP should be |
|
* reported. |
|
*/ |
|
if (user_mode(regs)) { |
|
if (debug_info->bps_disabled) { |
|
debug_info->bps_disabled = 0; |
|
toggle_bp_registers(AARCH64_DBG_REG_BCR, DBG_ACTIVE_EL0, 1); |
|
handled_exception = 1; |
|
} |
|
|
|
if (debug_info->wps_disabled) { |
|
debug_info->wps_disabled = 0; |
|
toggle_bp_registers(AARCH64_DBG_REG_WCR, DBG_ACTIVE_EL0, 1); |
|
handled_exception = 1; |
|
} |
|
|
|
if (handled_exception) { |
|
if (debug_info->suspended_step) { |
|
debug_info->suspended_step = 0; |
|
/* Allow exception handling to fall-through. */ |
|
handled_exception = 0; |
|
} else { |
|
user_disable_single_step(current); |
|
} |
|
} |
|
} else if (*kernel_step != ARM_KERNEL_STEP_NONE) { |
|
toggle_bp_registers(AARCH64_DBG_REG_BCR, DBG_ACTIVE_EL1, 1); |
|
toggle_bp_registers(AARCH64_DBG_REG_WCR, DBG_ACTIVE_EL1, 1); |
|
|
|
if (!debug_info->wps_disabled) |
|
toggle_bp_registers(AARCH64_DBG_REG_WCR, DBG_ACTIVE_EL0, 1); |
|
|
|
if (*kernel_step != ARM_KERNEL_STEP_SUSPEND) { |
|
kernel_disable_single_step(); |
|
handled_exception = 1; |
|
} else { |
|
handled_exception = 0; |
|
} |
|
|
|
*kernel_step = ARM_KERNEL_STEP_NONE; |
|
} |
|
|
|
return !handled_exception; |
|
} |
|
NOKPROBE_SYMBOL(reinstall_suspended_bps); |
|
|
|
/* |
|
* Context-switcher for restoring suspended breakpoints. |
|
*/ |
|
void hw_breakpoint_thread_switch(struct task_struct *next) |
|
{ |
|
/* |
|
* current next |
|
* disabled: 0 0 => The usual case, NOTIFY_DONE |
|
* 0 1 => Disable the registers |
|
* 1 0 => Enable the registers |
|
* 1 1 => NOTIFY_DONE. per-task bps will |
|
* get taken care of by perf. |
|
*/ |
|
|
|
struct debug_info *current_debug_info, *next_debug_info; |
|
|
|
current_debug_info = ¤t->thread.debug; |
|
next_debug_info = &next->thread.debug; |
|
|
|
/* Update breakpoints. */ |
|
if (current_debug_info->bps_disabled != next_debug_info->bps_disabled) |
|
toggle_bp_registers(AARCH64_DBG_REG_BCR, |
|
DBG_ACTIVE_EL0, |
|
!next_debug_info->bps_disabled); |
|
|
|
/* Update watchpoints. */ |
|
if (current_debug_info->wps_disabled != next_debug_info->wps_disabled) |
|
toggle_bp_registers(AARCH64_DBG_REG_WCR, |
|
DBG_ACTIVE_EL0, |
|
!next_debug_info->wps_disabled); |
|
} |
|
|
|
/* |
|
* CPU initialisation. |
|
*/ |
|
static int hw_breakpoint_reset(unsigned int cpu) |
|
{ |
|
int i; |
|
struct perf_event **slots; |
|
/* |
|
* When a CPU goes through cold-boot, it does not have any installed |
|
* slot, so it is safe to share the same function for restoring and |
|
* resetting breakpoints; when a CPU is hotplugged in, it goes |
|
* through the slots, which are all empty, hence it just resets control |
|
* and value for debug registers. |
|
* When this function is triggered on warm-boot through a CPU PM |
|
* notifier some slots might be initialized; if so they are |
|
* reprogrammed according to the debug slots content. |
|
*/ |
|
for (slots = this_cpu_ptr(bp_on_reg), i = 0; i < core_num_brps; ++i) { |
|
if (slots[i]) { |
|
hw_breakpoint_control(slots[i], HW_BREAKPOINT_RESTORE); |
|
} else { |
|
write_wb_reg(AARCH64_DBG_REG_BCR, i, 0UL); |
|
write_wb_reg(AARCH64_DBG_REG_BVR, i, 0UL); |
|
} |
|
} |
|
|
|
for (slots = this_cpu_ptr(wp_on_reg), i = 0; i < core_num_wrps; ++i) { |
|
if (slots[i]) { |
|
hw_breakpoint_control(slots[i], HW_BREAKPOINT_RESTORE); |
|
} else { |
|
write_wb_reg(AARCH64_DBG_REG_WCR, i, 0UL); |
|
write_wb_reg(AARCH64_DBG_REG_WVR, i, 0UL); |
|
} |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
#ifdef CONFIG_CPU_PM |
|
extern void cpu_suspend_set_dbg_restorer(int (*hw_bp_restore)(unsigned int)); |
|
#else |
|
static inline void cpu_suspend_set_dbg_restorer(int (*hw_bp_restore)(unsigned int)) |
|
{ |
|
} |
|
#endif |
|
|
|
/* |
|
* One-time initialisation. |
|
*/ |
|
static int __init arch_hw_breakpoint_init(void) |
|
{ |
|
int ret; |
|
|
|
core_num_brps = get_num_brps(); |
|
core_num_wrps = get_num_wrps(); |
|
|
|
pr_info("found %d breakpoint and %d watchpoint registers.\n", |
|
core_num_brps, core_num_wrps); |
|
|
|
/* Register debug fault handlers. */ |
|
hook_debug_fault_code(DBG_ESR_EVT_HWBP, breakpoint_handler, SIGTRAP, |
|
TRAP_HWBKPT, "hw-breakpoint handler"); |
|
hook_debug_fault_code(DBG_ESR_EVT_HWWP, watchpoint_handler, SIGTRAP, |
|
TRAP_HWBKPT, "hw-watchpoint handler"); |
|
|
|
/* |
|
* Reset the breakpoint resources. We assume that a halting |
|
* debugger will leave the world in a nice state for us. |
|
*/ |
|
ret = cpuhp_setup_state(CPUHP_AP_PERF_ARM_HW_BREAKPOINT_STARTING, |
|
"perf/arm64/hw_breakpoint:starting", |
|
hw_breakpoint_reset, NULL); |
|
if (ret) |
|
pr_err("failed to register CPU hotplug notifier: %d\n", ret); |
|
|
|
/* Register cpu_suspend hw breakpoint restore hook */ |
|
cpu_suspend_set_dbg_restorer(hw_breakpoint_reset); |
|
|
|
return ret; |
|
} |
|
arch_initcall(arch_hw_breakpoint_init); |
|
|
|
void hw_breakpoint_pmu_read(struct perf_event *bp) |
|
{ |
|
} |
|
|
|
/* |
|
* Dummy function to register with die_notifier. |
|
*/ |
|
int hw_breakpoint_exceptions_notify(struct notifier_block *unused, |
|
unsigned long val, void *data) |
|
{ |
|
return NOTIFY_DONE; |
|
}
|
|
|