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383 lines
10 KiB
383 lines
10 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Based on arch/arm/include/asm/ptrace.h |
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* |
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* Copyright (C) 1996-2003 Russell King |
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* Copyright (C) 2012 ARM Ltd. |
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*/ |
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#ifndef __ASM_PTRACE_H |
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#define __ASM_PTRACE_H |
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#include <asm/cpufeature.h> |
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#include <uapi/asm/ptrace.h> |
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/* Current Exception Level values, as contained in CurrentEL */ |
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#define CurrentEL_EL1 (1 << 2) |
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#define CurrentEL_EL2 (2 << 2) |
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#define INIT_PSTATE_EL1 \ |
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(PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT | PSR_MODE_EL1h) |
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#define INIT_PSTATE_EL2 \ |
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(PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT | PSR_MODE_EL2h) |
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/* |
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* PMR values used to mask/unmask interrupts. |
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* |
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* GIC priority masking works as follows: if an IRQ's priority is a higher value |
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* than the value held in PMR, that IRQ is masked. Lowering the value of PMR |
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* means masking more IRQs (or at least that the same IRQs remain masked). |
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* |
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* To mask interrupts, we clear the most significant bit of PMR. |
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* |
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* Some code sections either automatically switch back to PSR.I or explicitly |
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* require to not use priority masking. If bit GIC_PRIO_PSR_I_SET is included |
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* in the priority mask, it indicates that PSR.I should be set and |
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* interrupt disabling temporarily does not rely on IRQ priorities. |
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*/ |
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#define GIC_PRIO_IRQON 0xe0 |
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#define __GIC_PRIO_IRQOFF (GIC_PRIO_IRQON & ~0x80) |
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#define __GIC_PRIO_IRQOFF_NS 0xa0 |
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#define GIC_PRIO_PSR_I_SET (1 << 4) |
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#define GIC_PRIO_IRQOFF \ |
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({ \ |
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extern struct static_key_false gic_nonsecure_priorities;\ |
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u8 __prio = __GIC_PRIO_IRQOFF; \ |
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\ |
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if (static_branch_unlikely(&gic_nonsecure_priorities)) \ |
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__prio = __GIC_PRIO_IRQOFF_NS; \ |
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\ |
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__prio; \ |
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}) |
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/* Additional SPSR bits not exposed in the UABI */ |
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#define PSR_MODE_THREAD_BIT (1 << 0) |
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#define PSR_IL_BIT (1 << 20) |
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/* AArch32-specific ptrace requests */ |
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#define COMPAT_PTRACE_GETREGS 12 |
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#define COMPAT_PTRACE_SETREGS 13 |
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#define COMPAT_PTRACE_GET_THREAD_AREA 22 |
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#define COMPAT_PTRACE_SET_SYSCALL 23 |
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#define COMPAT_PTRACE_GETVFPREGS 27 |
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#define COMPAT_PTRACE_SETVFPREGS 28 |
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#define COMPAT_PTRACE_GETHBPREGS 29 |
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#define COMPAT_PTRACE_SETHBPREGS 30 |
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/* SPSR_ELx bits for exceptions taken from AArch32 */ |
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#define PSR_AA32_MODE_MASK 0x0000001f |
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#define PSR_AA32_MODE_USR 0x00000010 |
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#define PSR_AA32_MODE_FIQ 0x00000011 |
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#define PSR_AA32_MODE_IRQ 0x00000012 |
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#define PSR_AA32_MODE_SVC 0x00000013 |
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#define PSR_AA32_MODE_ABT 0x00000017 |
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#define PSR_AA32_MODE_HYP 0x0000001a |
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#define PSR_AA32_MODE_UND 0x0000001b |
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#define PSR_AA32_MODE_SYS 0x0000001f |
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#define PSR_AA32_T_BIT 0x00000020 |
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#define PSR_AA32_F_BIT 0x00000040 |
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#define PSR_AA32_I_BIT 0x00000080 |
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#define PSR_AA32_A_BIT 0x00000100 |
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#define PSR_AA32_E_BIT 0x00000200 |
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#define PSR_AA32_PAN_BIT 0x00400000 |
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#define PSR_AA32_SSBS_BIT 0x00800000 |
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#define PSR_AA32_DIT_BIT 0x01000000 |
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#define PSR_AA32_Q_BIT 0x08000000 |
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#define PSR_AA32_V_BIT 0x10000000 |
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#define PSR_AA32_C_BIT 0x20000000 |
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#define PSR_AA32_Z_BIT 0x40000000 |
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#define PSR_AA32_N_BIT 0x80000000 |
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#define PSR_AA32_IT_MASK 0x0600fc00 /* If-Then execution state mask */ |
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#define PSR_AA32_GE_MASK 0x000f0000 |
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#ifdef CONFIG_CPU_BIG_ENDIAN |
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#define PSR_AA32_ENDSTATE PSR_AA32_E_BIT |
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#else |
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#define PSR_AA32_ENDSTATE 0 |
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#endif |
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/* AArch32 CPSR bits, as seen in AArch32 */ |
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#define COMPAT_PSR_DIT_BIT 0x00200000 |
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/* |
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* These are 'magic' values for PTRACE_PEEKUSR that return info about where a |
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* process is located in memory. |
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*/ |
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#define COMPAT_PT_TEXT_ADDR 0x10000 |
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#define COMPAT_PT_DATA_ADDR 0x10004 |
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#define COMPAT_PT_TEXT_END_ADDR 0x10008 |
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/* |
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* If pt_regs.syscallno == NO_SYSCALL, then the thread is not executing |
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* a syscall -- i.e., its most recent entry into the kernel from |
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* userspace was not via SVC, or otherwise a tracer cancelled the syscall. |
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* |
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* This must have the value -1, for ABI compatibility with ptrace etc. |
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*/ |
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#define NO_SYSCALL (-1) |
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#ifndef __ASSEMBLY__ |
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#include <linux/bug.h> |
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#include <linux/types.h> |
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/* sizeof(struct user) for AArch32 */ |
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#define COMPAT_USER_SZ 296 |
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/* Architecturally defined mapping between AArch32 and AArch64 registers */ |
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#define compat_usr(x) regs[(x)] |
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#define compat_fp regs[11] |
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#define compat_sp regs[13] |
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#define compat_lr regs[14] |
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#define compat_sp_hyp regs[15] |
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#define compat_lr_irq regs[16] |
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#define compat_sp_irq regs[17] |
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#define compat_lr_svc regs[18] |
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#define compat_sp_svc regs[19] |
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#define compat_lr_abt regs[20] |
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#define compat_sp_abt regs[21] |
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#define compat_lr_und regs[22] |
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#define compat_sp_und regs[23] |
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#define compat_r8_fiq regs[24] |
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#define compat_r9_fiq regs[25] |
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#define compat_r10_fiq regs[26] |
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#define compat_r11_fiq regs[27] |
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#define compat_r12_fiq regs[28] |
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#define compat_sp_fiq regs[29] |
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#define compat_lr_fiq regs[30] |
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static inline unsigned long compat_psr_to_pstate(const unsigned long psr) |
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{ |
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unsigned long pstate; |
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pstate = psr & ~COMPAT_PSR_DIT_BIT; |
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if (psr & COMPAT_PSR_DIT_BIT) |
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pstate |= PSR_AA32_DIT_BIT; |
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return pstate; |
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} |
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static inline unsigned long pstate_to_compat_psr(const unsigned long pstate) |
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{ |
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unsigned long psr; |
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psr = pstate & ~PSR_AA32_DIT_BIT; |
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if (pstate & PSR_AA32_DIT_BIT) |
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psr |= COMPAT_PSR_DIT_BIT; |
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return psr; |
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} |
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/* |
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* This struct defines the way the registers are stored on the stack during an |
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* exception. Note that sizeof(struct pt_regs) has to be a multiple of 16 (for |
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* stack alignment). struct user_pt_regs must form a prefix of struct pt_regs. |
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*/ |
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struct pt_regs { |
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union { |
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struct user_pt_regs user_regs; |
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struct { |
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u64 regs[31]; |
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u64 sp; |
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u64 pc; |
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u64 pstate; |
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}; |
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}; |
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u64 orig_x0; |
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#ifdef __AARCH64EB__ |
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u32 unused2; |
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s32 syscallno; |
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#else |
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s32 syscallno; |
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u32 unused2; |
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#endif |
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u64 sdei_ttbr1; |
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/* Only valid when ARM64_HAS_IRQ_PRIO_MASKING is enabled. */ |
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u64 pmr_save; |
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u64 stackframe[2]; |
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/* Only valid for some EL1 exceptions. */ |
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u64 lockdep_hardirqs; |
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u64 exit_rcu; |
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}; |
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static inline bool in_syscall(struct pt_regs const *regs) |
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{ |
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return regs->syscallno != NO_SYSCALL; |
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} |
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static inline void forget_syscall(struct pt_regs *regs) |
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{ |
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regs->syscallno = NO_SYSCALL; |
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} |
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#define MAX_REG_OFFSET offsetof(struct pt_regs, pstate) |
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#define arch_has_single_step() (1) |
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#ifdef CONFIG_COMPAT |
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#define compat_thumb_mode(regs) \ |
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(((regs)->pstate & PSR_AA32_T_BIT)) |
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#else |
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#define compat_thumb_mode(regs) (0) |
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#endif |
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#define user_mode(regs) \ |
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(((regs)->pstate & PSR_MODE_MASK) == PSR_MODE_EL0t) |
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#define compat_user_mode(regs) \ |
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(((regs)->pstate & (PSR_MODE32_BIT | PSR_MODE_MASK)) == \ |
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(PSR_MODE32_BIT | PSR_MODE_EL0t)) |
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#define processor_mode(regs) \ |
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((regs)->pstate & PSR_MODE_MASK) |
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#define irqs_priority_unmasked(regs) \ |
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(system_uses_irq_prio_masking() ? \ |
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(regs)->pmr_save == GIC_PRIO_IRQON : \ |
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true) |
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#define interrupts_enabled(regs) \ |
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(!((regs)->pstate & PSR_I_BIT) && irqs_priority_unmasked(regs)) |
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#define fast_interrupts_enabled(regs) \ |
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(!((regs)->pstate & PSR_F_BIT)) |
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static inline unsigned long user_stack_pointer(struct pt_regs *regs) |
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{ |
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if (compat_user_mode(regs)) |
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return regs->compat_sp; |
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return regs->sp; |
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} |
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extern int regs_query_register_offset(const char *name); |
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extern unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, |
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unsigned int n); |
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/** |
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* regs_get_register() - get register value from its offset |
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* @regs: pt_regs from which register value is gotten |
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* @offset: offset of the register. |
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* |
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* regs_get_register returns the value of a register whose offset from @regs. |
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* The @offset is the offset of the register in struct pt_regs. |
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* If @offset is bigger than MAX_REG_OFFSET, this returns 0. |
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*/ |
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static inline u64 regs_get_register(struct pt_regs *regs, unsigned int offset) |
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{ |
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u64 val = 0; |
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WARN_ON(offset & 7); |
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offset >>= 3; |
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switch (offset) { |
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case 0 ... 30: |
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val = regs->regs[offset]; |
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break; |
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case offsetof(struct pt_regs, sp) >> 3: |
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val = regs->sp; |
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break; |
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case offsetof(struct pt_regs, pc) >> 3: |
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val = regs->pc; |
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break; |
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case offsetof(struct pt_regs, pstate) >> 3: |
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val = regs->pstate; |
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break; |
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default: |
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val = 0; |
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} |
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return val; |
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} |
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/* |
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* Read a register given an architectural register index r. |
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* This handles the common case where 31 means XZR, not SP. |
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*/ |
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static inline unsigned long pt_regs_read_reg(const struct pt_regs *regs, int r) |
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{ |
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return (r == 31) ? 0 : regs->regs[r]; |
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} |
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/* |
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* Write a register given an architectural register index r. |
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* This handles the common case where 31 means XZR, not SP. |
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*/ |
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static inline void pt_regs_write_reg(struct pt_regs *regs, int r, |
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unsigned long val) |
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{ |
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if (r != 31) |
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regs->regs[r] = val; |
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} |
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/* Valid only for Kernel mode traps. */ |
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static inline unsigned long kernel_stack_pointer(struct pt_regs *regs) |
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{ |
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return regs->sp; |
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} |
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static inline unsigned long regs_return_value(struct pt_regs *regs) |
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{ |
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return regs->regs[0]; |
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} |
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static inline void regs_set_return_value(struct pt_regs *regs, unsigned long rc) |
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{ |
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regs->regs[0] = rc; |
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} |
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/** |
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* regs_get_kernel_argument() - get Nth function argument in kernel |
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* @regs: pt_regs of that context |
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* @n: function argument number (start from 0) |
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* |
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* regs_get_argument() returns @n th argument of the function call. |
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* |
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* Note that this chooses the most likely register mapping. In very rare |
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* cases this may not return correct data, for example, if one of the |
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* function parameters is 16 bytes or bigger. In such cases, we cannot |
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* get access the parameter correctly and the register assignment of |
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* subsequent parameters will be shifted. |
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*/ |
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static inline unsigned long regs_get_kernel_argument(struct pt_regs *regs, |
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unsigned int n) |
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{ |
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#define NR_REG_ARGUMENTS 8 |
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if (n < NR_REG_ARGUMENTS) |
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return pt_regs_read_reg(regs, n); |
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return 0; |
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} |
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/* We must avoid circular header include via sched.h */ |
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struct task_struct; |
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int valid_user_regs(struct user_pt_regs *regs, struct task_struct *task); |
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static inline unsigned long instruction_pointer(struct pt_regs *regs) |
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{ |
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return regs->pc; |
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} |
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static inline void instruction_pointer_set(struct pt_regs *regs, |
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unsigned long val) |
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{ |
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regs->pc = val; |
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} |
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static inline unsigned long frame_pointer(struct pt_regs *regs) |
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{ |
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return regs->regs[29]; |
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} |
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#define procedure_link_pointer(regs) ((regs)->regs[30]) |
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static inline void procedure_link_pointer_set(struct pt_regs *regs, |
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unsigned long val) |
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{ |
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procedure_link_pointer(regs) = val; |
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} |
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extern unsigned long profile_pc(struct pt_regs *regs); |
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#endif /* __ASSEMBLY__ */ |
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#endif
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