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68 lines
1.8 KiB
68 lines
1.8 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Copyright (C) 2012 ARM Ltd. |
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*/ |
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#ifndef __ASM_MODULE_H |
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#define __ASM_MODULE_H |
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#include <asm-generic/module.h> |
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#ifdef CONFIG_ARM64_MODULE_PLTS |
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struct mod_plt_sec { |
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int plt_shndx; |
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int plt_num_entries; |
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int plt_max_entries; |
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}; |
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struct mod_arch_specific { |
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struct mod_plt_sec core; |
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struct mod_plt_sec init; |
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/* for CONFIG_DYNAMIC_FTRACE */ |
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struct plt_entry *ftrace_trampolines; |
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}; |
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#endif |
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u64 module_emit_plt_entry(struct module *mod, Elf64_Shdr *sechdrs, |
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void *loc, const Elf64_Rela *rela, |
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Elf64_Sym *sym); |
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u64 module_emit_veneer_for_adrp(struct module *mod, Elf64_Shdr *sechdrs, |
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void *loc, u64 val); |
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#ifdef CONFIG_RANDOMIZE_BASE |
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extern u64 module_alloc_base; |
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#else |
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#define module_alloc_base ((u64)_etext - MODULES_VSIZE) |
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#endif |
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struct plt_entry { |
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/* |
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* A program that conforms to the AArch64 Procedure Call Standard |
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* (AAPCS64) must assume that a veneer that alters IP0 (x16) and/or |
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* IP1 (x17) may be inserted at any branch instruction that is |
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* exposed to a relocation that supports long branches. Since that |
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* is exactly what we are dealing with here, we are free to use x16 |
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* as a scratch register in the PLT veneers. |
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*/ |
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__le32 adrp; /* adrp x16, .... */ |
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__le32 add; /* add x16, x16, #0x.... */ |
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__le32 br; /* br x16 */ |
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}; |
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static inline bool is_forbidden_offset_for_adrp(void *place) |
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{ |
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return IS_ENABLED(CONFIG_ARM64_ERRATUM_843419) && |
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cpus_have_const_cap(ARM64_WORKAROUND_843419) && |
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((u64)place & 0xfff) >= 0xff8; |
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} |
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struct plt_entry get_plt_entry(u64 dst, void *pc); |
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bool plt_entries_equal(const struct plt_entry *a, const struct plt_entry *b); |
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static inline bool plt_entry_is_initialized(const struct plt_entry *e) |
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{ |
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return e->adrp || e->add || e->br; |
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} |
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#endif /* __ASM_MODULE_H */
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