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776 lines
24 KiB
776 lines
24 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Copyright (C) 2012,2013 - ARM Ltd |
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* Author: Marc Zyngier <[email protected]> |
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* |
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* Derived from arch/arm/include/asm/kvm_host.h: |
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* Copyright (C) 2012 - Virtual Open Systems and Columbia University |
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* Author: Christoffer Dall <[email protected]> |
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*/ |
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#ifndef __ARM64_KVM_HOST_H__ |
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#define __ARM64_KVM_HOST_H__ |
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#include <linux/arm-smccc.h> |
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#include <linux/bitmap.h> |
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#include <linux/types.h> |
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#include <linux/jump_label.h> |
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#include <linux/kvm_types.h> |
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#include <linux/percpu.h> |
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#include <linux/psci.h> |
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#include <asm/arch_gicv3.h> |
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#include <asm/barrier.h> |
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#include <asm/cpufeature.h> |
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#include <asm/cputype.h> |
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#include <asm/daifflags.h> |
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#include <asm/fpsimd.h> |
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#include <asm/kvm.h> |
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#include <asm/kvm_asm.h> |
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#include <asm/thread_info.h> |
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#define __KVM_HAVE_ARCH_INTC_INITIALIZED |
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#define KVM_HALT_POLL_NS_DEFAULT 500000 |
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#include <kvm/arm_vgic.h> |
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#include <kvm/arm_arch_timer.h> |
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#include <kvm/arm_pmu.h> |
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#define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS |
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#define KVM_VCPU_MAX_FEATURES 7 |
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#define KVM_REQ_SLEEP \ |
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KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) |
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#define KVM_REQ_IRQ_PENDING KVM_ARCH_REQ(1) |
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#define KVM_REQ_VCPU_RESET KVM_ARCH_REQ(2) |
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#define KVM_REQ_RECORD_STEAL KVM_ARCH_REQ(3) |
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#define KVM_REQ_RELOAD_GICv4 KVM_ARCH_REQ(4) |
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#define KVM_DIRTY_LOG_MANUAL_CAPS (KVM_DIRTY_LOG_MANUAL_PROTECT_ENABLE | \ |
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KVM_DIRTY_LOG_INITIALLY_SET) |
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/* |
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* Mode of operation configurable with kvm-arm.mode early param. |
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* See Documentation/admin-guide/kernel-parameters.txt for more information. |
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*/ |
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enum kvm_mode { |
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KVM_MODE_DEFAULT, |
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KVM_MODE_PROTECTED, |
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}; |
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enum kvm_mode kvm_get_mode(void); |
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DECLARE_STATIC_KEY_FALSE(userspace_irqchip_in_use); |
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extern unsigned int kvm_sve_max_vl; |
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int kvm_arm_init_sve(void); |
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int __attribute_const__ kvm_target_cpu(void); |
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int kvm_reset_vcpu(struct kvm_vcpu *vcpu); |
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void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu); |
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struct kvm_vmid { |
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/* The VMID generation used for the virt. memory system */ |
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u64 vmid_gen; |
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u32 vmid; |
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}; |
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struct kvm_s2_mmu { |
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struct kvm_vmid vmid; |
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/* |
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* stage2 entry level table |
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* |
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* Two kvm_s2_mmu structures in the same VM can point to the same |
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* pgd here. This happens when running a guest using a |
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* translation regime that isn't affected by its own stage-2 |
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* translation, such as a non-VHE hypervisor running at vEL2, or |
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* for vEL1/EL0 with vHCR_EL2.VM == 0. In that case, we use the |
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* canonical stage-2 page tables. |
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*/ |
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phys_addr_t pgd_phys; |
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struct kvm_pgtable *pgt; |
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/* The last vcpu id that ran on each physical CPU */ |
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int __percpu *last_vcpu_ran; |
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struct kvm *kvm; |
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}; |
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struct kvm_arch_memory_slot { |
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}; |
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struct kvm_arch { |
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struct kvm_s2_mmu mmu; |
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/* VTCR_EL2 value for this VM */ |
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u64 vtcr; |
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/* The maximum number of vCPUs depends on the used GIC model */ |
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int max_vcpus; |
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/* Interrupt controller */ |
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struct vgic_dist vgic; |
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/* Mandated version of PSCI */ |
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u32 psci_version; |
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/* |
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* If we encounter a data abort without valid instruction syndrome |
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* information, report this to user space. User space can (and |
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* should) opt in to this feature if KVM_CAP_ARM_NISV_TO_USER is |
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* supported. |
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*/ |
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bool return_nisv_io_abort_to_user; |
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/* |
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* VM-wide PMU filter, implemented as a bitmap and big enough for |
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* up to 2^10 events (ARMv8.0) or 2^16 events (ARMv8.1+). |
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*/ |
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unsigned long *pmu_filter; |
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unsigned int pmuver; |
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u8 pfr0_csv2; |
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u8 pfr0_csv3; |
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}; |
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struct kvm_vcpu_fault_info { |
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u32 esr_el2; /* Hyp Syndrom Register */ |
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u64 far_el2; /* Hyp Fault Address Register */ |
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u64 hpfar_el2; /* Hyp IPA Fault Address Register */ |
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u64 disr_el1; /* Deferred [SError] Status Register */ |
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}; |
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enum vcpu_sysreg { |
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__INVALID_SYSREG__, /* 0 is reserved as an invalid value */ |
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MPIDR_EL1, /* MultiProcessor Affinity Register */ |
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CSSELR_EL1, /* Cache Size Selection Register */ |
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SCTLR_EL1, /* System Control Register */ |
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ACTLR_EL1, /* Auxiliary Control Register */ |
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CPACR_EL1, /* Coprocessor Access Control */ |
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ZCR_EL1, /* SVE Control */ |
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TTBR0_EL1, /* Translation Table Base Register 0 */ |
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TTBR1_EL1, /* Translation Table Base Register 1 */ |
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TCR_EL1, /* Translation Control Register */ |
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ESR_EL1, /* Exception Syndrome Register */ |
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AFSR0_EL1, /* Auxiliary Fault Status Register 0 */ |
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AFSR1_EL1, /* Auxiliary Fault Status Register 1 */ |
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FAR_EL1, /* Fault Address Register */ |
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MAIR_EL1, /* Memory Attribute Indirection Register */ |
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VBAR_EL1, /* Vector Base Address Register */ |
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CONTEXTIDR_EL1, /* Context ID Register */ |
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TPIDR_EL0, /* Thread ID, User R/W */ |
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TPIDRRO_EL0, /* Thread ID, User R/O */ |
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TPIDR_EL1, /* Thread ID, Privileged */ |
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AMAIR_EL1, /* Aux Memory Attribute Indirection Register */ |
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CNTKCTL_EL1, /* Timer Control Register (EL1) */ |
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PAR_EL1, /* Physical Address Register */ |
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MDSCR_EL1, /* Monitor Debug System Control Register */ |
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MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */ |
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DISR_EL1, /* Deferred Interrupt Status Register */ |
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/* Performance Monitors Registers */ |
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PMCR_EL0, /* Control Register */ |
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PMSELR_EL0, /* Event Counter Selection Register */ |
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PMEVCNTR0_EL0, /* Event Counter Register (0-30) */ |
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PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30, |
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PMCCNTR_EL0, /* Cycle Counter Register */ |
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PMEVTYPER0_EL0, /* Event Type Register (0-30) */ |
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PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30, |
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PMCCFILTR_EL0, /* Cycle Count Filter Register */ |
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PMCNTENSET_EL0, /* Count Enable Set Register */ |
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PMINTENSET_EL1, /* Interrupt Enable Set Register */ |
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PMOVSSET_EL0, /* Overflow Flag Status Set Register */ |
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PMSWINC_EL0, /* Software Increment Register */ |
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PMUSERENR_EL0, /* User Enable Register */ |
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/* Pointer Authentication Registers in a strict increasing order. */ |
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APIAKEYLO_EL1, |
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APIAKEYHI_EL1, |
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APIBKEYLO_EL1, |
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APIBKEYHI_EL1, |
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APDAKEYLO_EL1, |
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APDAKEYHI_EL1, |
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APDBKEYLO_EL1, |
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APDBKEYHI_EL1, |
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APGAKEYLO_EL1, |
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APGAKEYHI_EL1, |
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ELR_EL1, |
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SP_EL1, |
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SPSR_EL1, |
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CNTVOFF_EL2, |
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CNTV_CVAL_EL0, |
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CNTV_CTL_EL0, |
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CNTP_CVAL_EL0, |
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CNTP_CTL_EL0, |
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/* 32bit specific registers. Keep them at the end of the range */ |
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DACR32_EL2, /* Domain Access Control Register */ |
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IFSR32_EL2, /* Instruction Fault Status Register */ |
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FPEXC32_EL2, /* Floating-Point Exception Control Register */ |
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DBGVCR32_EL2, /* Debug Vector Catch Register */ |
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NR_SYS_REGS /* Nothing after this line! */ |
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}; |
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struct kvm_cpu_context { |
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struct user_pt_regs regs; /* sp = sp_el0 */ |
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u64 spsr_abt; |
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u64 spsr_und; |
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u64 spsr_irq; |
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u64 spsr_fiq; |
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struct user_fpsimd_state fp_regs; |
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u64 sys_regs[NR_SYS_REGS]; |
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struct kvm_vcpu *__hyp_running_vcpu; |
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}; |
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struct kvm_pmu_events { |
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u32 events_host; |
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u32 events_guest; |
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}; |
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struct kvm_host_data { |
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struct kvm_cpu_context host_ctxt; |
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struct kvm_pmu_events pmu_events; |
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}; |
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struct kvm_host_psci_config { |
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/* PSCI version used by host. */ |
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u32 version; |
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/* Function IDs used by host if version is v0.1. */ |
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struct psci_0_1_function_ids function_ids_0_1; |
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bool psci_0_1_cpu_suspend_implemented; |
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bool psci_0_1_cpu_on_implemented; |
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bool psci_0_1_cpu_off_implemented; |
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bool psci_0_1_migrate_implemented; |
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}; |
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extern struct kvm_host_psci_config kvm_nvhe_sym(kvm_host_psci_config); |
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#define kvm_host_psci_config CHOOSE_NVHE_SYM(kvm_host_psci_config) |
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extern s64 kvm_nvhe_sym(hyp_physvirt_offset); |
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#define hyp_physvirt_offset CHOOSE_NVHE_SYM(hyp_physvirt_offset) |
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extern u64 kvm_nvhe_sym(hyp_cpu_logical_map)[NR_CPUS]; |
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#define hyp_cpu_logical_map CHOOSE_NVHE_SYM(hyp_cpu_logical_map) |
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struct vcpu_reset_state { |
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unsigned long pc; |
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unsigned long r0; |
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bool be; |
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bool reset; |
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}; |
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struct kvm_vcpu_arch { |
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struct kvm_cpu_context ctxt; |
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void *sve_state; |
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unsigned int sve_max_vl; |
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/* Stage 2 paging state used by the hardware on next switch */ |
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struct kvm_s2_mmu *hw_mmu; |
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/* HYP configuration */ |
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u64 hcr_el2; |
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u32 mdcr_el2; |
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/* Exception Information */ |
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struct kvm_vcpu_fault_info fault; |
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/* State of various workarounds, see kvm_asm.h for bit assignment */ |
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u64 workaround_flags; |
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/* Miscellaneous vcpu state flags */ |
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u64 flags; |
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/* |
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* We maintain more than a single set of debug registers to support |
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* debugging the guest from the host and to maintain separate host and |
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* guest state during world switches. vcpu_debug_state are the debug |
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* registers of the vcpu as the guest sees them. host_debug_state are |
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* the host registers which are saved and restored during |
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* world switches. external_debug_state contains the debug |
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* values we want to debug the guest. This is set via the |
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* KVM_SET_GUEST_DEBUG ioctl. |
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* |
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* debug_ptr points to the set of debug registers that should be loaded |
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* onto the hardware when running the guest. |
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*/ |
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struct kvm_guest_debug_arch *debug_ptr; |
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struct kvm_guest_debug_arch vcpu_debug_state; |
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struct kvm_guest_debug_arch external_debug_state; |
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struct thread_info *host_thread_info; /* hyp VA */ |
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struct user_fpsimd_state *host_fpsimd_state; /* hyp VA */ |
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struct { |
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/* {Break,watch}point registers */ |
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struct kvm_guest_debug_arch regs; |
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/* Statistical profiling extension */ |
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u64 pmscr_el1; |
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} host_debug_state; |
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/* VGIC state */ |
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struct vgic_cpu vgic_cpu; |
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struct arch_timer_cpu timer_cpu; |
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struct kvm_pmu pmu; |
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/* |
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* Anything that is not used directly from assembly code goes |
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* here. |
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*/ |
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/* |
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* Guest registers we preserve during guest debugging. |
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* |
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* These shadow registers are updated by the kvm_handle_sys_reg |
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* trap handler if the guest accesses or updates them while we |
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* are using guest debug. |
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*/ |
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struct { |
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u32 mdscr_el1; |
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} guest_debug_preserved; |
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/* vcpu power-off state */ |
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bool power_off; |
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/* Don't run the guest (internal implementation need) */ |
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bool pause; |
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/* Cache some mmu pages needed inside spinlock regions */ |
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struct kvm_mmu_memory_cache mmu_page_cache; |
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/* Target CPU and feature flags */ |
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int target; |
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DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES); |
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/* Detect first run of a vcpu */ |
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bool has_run_once; |
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/* Virtual SError ESR to restore when HCR_EL2.VSE is set */ |
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u64 vsesr_el2; |
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/* Additional reset state */ |
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struct vcpu_reset_state reset_state; |
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/* True when deferrable sysregs are loaded on the physical CPU, |
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* see kvm_vcpu_load_sysregs_vhe and kvm_vcpu_put_sysregs_vhe. */ |
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bool sysregs_loaded_on_cpu; |
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/* Guest PV state */ |
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struct { |
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u64 last_steal; |
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gpa_t base; |
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} steal; |
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}; |
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/* Pointer to the vcpu's SVE FFR for sve_{save,load}_state() */ |
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#define vcpu_sve_pffr(vcpu) ((void *)((char *)((vcpu)->arch.sve_state) + \ |
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sve_ffr_offset((vcpu)->arch.sve_max_vl))) |
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#define vcpu_sve_state_size(vcpu) ({ \ |
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size_t __size_ret; \ |
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unsigned int __vcpu_vq; \ |
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\ |
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if (WARN_ON(!sve_vl_valid((vcpu)->arch.sve_max_vl))) { \ |
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__size_ret = 0; \ |
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} else { \ |
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__vcpu_vq = sve_vq_from_vl((vcpu)->arch.sve_max_vl); \ |
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__size_ret = SVE_SIG_REGS_SIZE(__vcpu_vq); \ |
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} \ |
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\ |
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__size_ret; \ |
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}) |
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/* vcpu_arch flags field values: */ |
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#define KVM_ARM64_DEBUG_DIRTY (1 << 0) |
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#define KVM_ARM64_FP_ENABLED (1 << 1) /* guest FP regs loaded */ |
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#define KVM_ARM64_FP_HOST (1 << 2) /* host FP regs loaded */ |
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#define KVM_ARM64_HOST_SVE_IN_USE (1 << 3) /* backup for host TIF_SVE */ |
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#define KVM_ARM64_HOST_SVE_ENABLED (1 << 4) /* SVE enabled for EL0 */ |
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#define KVM_ARM64_GUEST_HAS_SVE (1 << 5) /* SVE exposed to guest */ |
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#define KVM_ARM64_VCPU_SVE_FINALIZED (1 << 6) /* SVE config completed */ |
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#define KVM_ARM64_GUEST_HAS_PTRAUTH (1 << 7) /* PTRAUTH exposed to guest */ |
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#define KVM_ARM64_PENDING_EXCEPTION (1 << 8) /* Exception pending */ |
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#define KVM_ARM64_EXCEPT_MASK (7 << 9) /* Target EL/MODE */ |
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/* |
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* When KVM_ARM64_PENDING_EXCEPTION is set, KVM_ARM64_EXCEPT_MASK can |
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* take the following values: |
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* |
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* For AArch32 EL1: |
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*/ |
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#define KVM_ARM64_EXCEPT_AA32_UND (0 << 9) |
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#define KVM_ARM64_EXCEPT_AA32_IABT (1 << 9) |
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#define KVM_ARM64_EXCEPT_AA32_DABT (2 << 9) |
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/* For AArch64: */ |
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#define KVM_ARM64_EXCEPT_AA64_ELx_SYNC (0 << 9) |
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#define KVM_ARM64_EXCEPT_AA64_ELx_IRQ (1 << 9) |
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#define KVM_ARM64_EXCEPT_AA64_ELx_FIQ (2 << 9) |
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#define KVM_ARM64_EXCEPT_AA64_ELx_SERR (3 << 9) |
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#define KVM_ARM64_EXCEPT_AA64_EL1 (0 << 11) |
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#define KVM_ARM64_EXCEPT_AA64_EL2 (1 << 11) |
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/* |
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* Overlaps with KVM_ARM64_EXCEPT_MASK on purpose so that it can't be |
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* set together with an exception... |
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*/ |
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#define KVM_ARM64_INCREMENT_PC (1 << 9) /* Increment PC */ |
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#define vcpu_has_sve(vcpu) (system_supports_sve() && \ |
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((vcpu)->arch.flags & KVM_ARM64_GUEST_HAS_SVE)) |
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#ifdef CONFIG_ARM64_PTR_AUTH |
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#define vcpu_has_ptrauth(vcpu) \ |
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((cpus_have_final_cap(ARM64_HAS_ADDRESS_AUTH) || \ |
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cpus_have_final_cap(ARM64_HAS_GENERIC_AUTH)) && \ |
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(vcpu)->arch.flags & KVM_ARM64_GUEST_HAS_PTRAUTH) |
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#else |
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#define vcpu_has_ptrauth(vcpu) false |
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#endif |
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#define vcpu_gp_regs(v) (&(v)->arch.ctxt.regs) |
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/* |
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* Only use __vcpu_sys_reg/ctxt_sys_reg if you know you want the |
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* memory backed version of a register, and not the one most recently |
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* accessed by a running VCPU. For example, for userspace access or |
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* for system registers that are never context switched, but only |
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* emulated. |
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*/ |
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#define __ctxt_sys_reg(c,r) (&(c)->sys_regs[(r)]) |
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#define ctxt_sys_reg(c,r) (*__ctxt_sys_reg(c,r)) |
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#define __vcpu_sys_reg(v,r) (ctxt_sys_reg(&(v)->arch.ctxt, (r))) |
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u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg); |
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void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg); |
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static inline bool __vcpu_read_sys_reg_from_cpu(int reg, u64 *val) |
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{ |
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/* |
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* *** VHE ONLY *** |
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* |
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* System registers listed in the switch are not saved on every |
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* exit from the guest but are only saved on vcpu_put. |
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* |
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* Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but |
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* should never be listed below, because the guest cannot modify its |
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* own MPIDR_EL1 and MPIDR_EL1 is accessed for VCPU A from VCPU B's |
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* thread when emulating cross-VCPU communication. |
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*/ |
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if (!has_vhe()) |
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return false; |
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switch (reg) { |
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case CSSELR_EL1: *val = read_sysreg_s(SYS_CSSELR_EL1); break; |
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case SCTLR_EL1: *val = read_sysreg_s(SYS_SCTLR_EL12); break; |
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case CPACR_EL1: *val = read_sysreg_s(SYS_CPACR_EL12); break; |
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case TTBR0_EL1: *val = read_sysreg_s(SYS_TTBR0_EL12); break; |
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case TTBR1_EL1: *val = read_sysreg_s(SYS_TTBR1_EL12); break; |
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case TCR_EL1: *val = read_sysreg_s(SYS_TCR_EL12); break; |
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case ESR_EL1: *val = read_sysreg_s(SYS_ESR_EL12); break; |
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case AFSR0_EL1: *val = read_sysreg_s(SYS_AFSR0_EL12); break; |
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case AFSR1_EL1: *val = read_sysreg_s(SYS_AFSR1_EL12); break; |
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case FAR_EL1: *val = read_sysreg_s(SYS_FAR_EL12); break; |
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case MAIR_EL1: *val = read_sysreg_s(SYS_MAIR_EL12); break; |
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case VBAR_EL1: *val = read_sysreg_s(SYS_VBAR_EL12); break; |
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case CONTEXTIDR_EL1: *val = read_sysreg_s(SYS_CONTEXTIDR_EL12);break; |
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case TPIDR_EL0: *val = read_sysreg_s(SYS_TPIDR_EL0); break; |
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case TPIDRRO_EL0: *val = read_sysreg_s(SYS_TPIDRRO_EL0); break; |
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case TPIDR_EL1: *val = read_sysreg_s(SYS_TPIDR_EL1); break; |
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case AMAIR_EL1: *val = read_sysreg_s(SYS_AMAIR_EL12); break; |
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case CNTKCTL_EL1: *val = read_sysreg_s(SYS_CNTKCTL_EL12); break; |
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case ELR_EL1: *val = read_sysreg_s(SYS_ELR_EL12); break; |
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case PAR_EL1: *val = read_sysreg_par(); break; |
|
case DACR32_EL2: *val = read_sysreg_s(SYS_DACR32_EL2); break; |
|
case IFSR32_EL2: *val = read_sysreg_s(SYS_IFSR32_EL2); break; |
|
case DBGVCR32_EL2: *val = read_sysreg_s(SYS_DBGVCR32_EL2); break; |
|
default: return false; |
|
} |
|
|
|
return true; |
|
} |
|
|
|
static inline bool __vcpu_write_sys_reg_to_cpu(u64 val, int reg) |
|
{ |
|
/* |
|
* *** VHE ONLY *** |
|
* |
|
* System registers listed in the switch are not restored on every |
|
* entry to the guest but are only restored on vcpu_load. |
|
* |
|
* Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but |
|
* should never be listed below, because the MPIDR should only be set |
|
* once, before running the VCPU, and never changed later. |
|
*/ |
|
if (!has_vhe()) |
|
return false; |
|
|
|
switch (reg) { |
|
case CSSELR_EL1: write_sysreg_s(val, SYS_CSSELR_EL1); break; |
|
case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); break; |
|
case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); break; |
|
case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); break; |
|
case TTBR1_EL1: write_sysreg_s(val, SYS_TTBR1_EL12); break; |
|
case TCR_EL1: write_sysreg_s(val, SYS_TCR_EL12); break; |
|
case ESR_EL1: write_sysreg_s(val, SYS_ESR_EL12); break; |
|
case AFSR0_EL1: write_sysreg_s(val, SYS_AFSR0_EL12); break; |
|
case AFSR1_EL1: write_sysreg_s(val, SYS_AFSR1_EL12); break; |
|
case FAR_EL1: write_sysreg_s(val, SYS_FAR_EL12); break; |
|
case MAIR_EL1: write_sysreg_s(val, SYS_MAIR_EL12); break; |
|
case VBAR_EL1: write_sysreg_s(val, SYS_VBAR_EL12); break; |
|
case CONTEXTIDR_EL1: write_sysreg_s(val, SYS_CONTEXTIDR_EL12);break; |
|
case TPIDR_EL0: write_sysreg_s(val, SYS_TPIDR_EL0); break; |
|
case TPIDRRO_EL0: write_sysreg_s(val, SYS_TPIDRRO_EL0); break; |
|
case TPIDR_EL1: write_sysreg_s(val, SYS_TPIDR_EL1); break; |
|
case AMAIR_EL1: write_sysreg_s(val, SYS_AMAIR_EL12); break; |
|
case CNTKCTL_EL1: write_sysreg_s(val, SYS_CNTKCTL_EL12); break; |
|
case ELR_EL1: write_sysreg_s(val, SYS_ELR_EL12); break; |
|
case PAR_EL1: write_sysreg_s(val, SYS_PAR_EL1); break; |
|
case DACR32_EL2: write_sysreg_s(val, SYS_DACR32_EL2); break; |
|
case IFSR32_EL2: write_sysreg_s(val, SYS_IFSR32_EL2); break; |
|
case DBGVCR32_EL2: write_sysreg_s(val, SYS_DBGVCR32_EL2); break; |
|
default: return false; |
|
} |
|
|
|
return true; |
|
} |
|
|
|
struct kvm_vm_stat { |
|
ulong remote_tlb_flush; |
|
}; |
|
|
|
struct kvm_vcpu_stat { |
|
u64 halt_successful_poll; |
|
u64 halt_attempted_poll; |
|
u64 halt_poll_success_ns; |
|
u64 halt_poll_fail_ns; |
|
u64 halt_poll_invalid; |
|
u64 halt_wakeup; |
|
u64 hvc_exit_stat; |
|
u64 wfe_exit_stat; |
|
u64 wfi_exit_stat; |
|
u64 mmio_exit_user; |
|
u64 mmio_exit_kernel; |
|
u64 exits; |
|
}; |
|
|
|
int kvm_vcpu_preferred_target(struct kvm_vcpu_init *init); |
|
unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu); |
|
int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices); |
|
int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); |
|
int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); |
|
|
|
unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu); |
|
int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices); |
|
int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *); |
|
int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *); |
|
|
|
int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu, |
|
struct kvm_vcpu_events *events); |
|
|
|
int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu, |
|
struct kvm_vcpu_events *events); |
|
|
|
#define KVM_ARCH_WANT_MMU_NOTIFIER |
|
int kvm_unmap_hva_range(struct kvm *kvm, |
|
unsigned long start, unsigned long end, unsigned flags); |
|
int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte); |
|
int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end); |
|
int kvm_test_age_hva(struct kvm *kvm, unsigned long hva); |
|
|
|
void kvm_arm_halt_guest(struct kvm *kvm); |
|
void kvm_arm_resume_guest(struct kvm *kvm); |
|
|
|
#define kvm_call_hyp_nvhe(f, ...) \ |
|
({ \ |
|
struct arm_smccc_res res; \ |
|
\ |
|
arm_smccc_1_1_hvc(KVM_HOST_SMCCC_FUNC(f), \ |
|
##__VA_ARGS__, &res); \ |
|
WARN_ON(res.a0 != SMCCC_RET_SUCCESS); \ |
|
\ |
|
res.a1; \ |
|
}) |
|
|
|
/* |
|
* The couple of isb() below are there to guarantee the same behaviour |
|
* on VHE as on !VHE, where the eret to EL1 acts as a context |
|
* synchronization event. |
|
*/ |
|
#define kvm_call_hyp(f, ...) \ |
|
do { \ |
|
if (has_vhe()) { \ |
|
f(__VA_ARGS__); \ |
|
isb(); \ |
|
} else { \ |
|
kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \ |
|
} \ |
|
} while(0) |
|
|
|
#define kvm_call_hyp_ret(f, ...) \ |
|
({ \ |
|
typeof(f(__VA_ARGS__)) ret; \ |
|
\ |
|
if (has_vhe()) { \ |
|
ret = f(__VA_ARGS__); \ |
|
isb(); \ |
|
} else { \ |
|
ret = kvm_call_hyp_nvhe(f, ##__VA_ARGS__); \ |
|
} \ |
|
\ |
|
ret; \ |
|
}) |
|
|
|
void force_vm_exit(const cpumask_t *mask); |
|
void kvm_mmu_wp_memory_region(struct kvm *kvm, int slot); |
|
|
|
int handle_exit(struct kvm_vcpu *vcpu, int exception_index); |
|
void handle_exit_early(struct kvm_vcpu *vcpu, int exception_index); |
|
|
|
int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu); |
|
int kvm_handle_cp14_32(struct kvm_vcpu *vcpu); |
|
int kvm_handle_cp14_64(struct kvm_vcpu *vcpu); |
|
int kvm_handle_cp15_32(struct kvm_vcpu *vcpu); |
|
int kvm_handle_cp15_64(struct kvm_vcpu *vcpu); |
|
int kvm_handle_sys_reg(struct kvm_vcpu *vcpu); |
|
|
|
void kvm_reset_sys_regs(struct kvm_vcpu *vcpu); |
|
|
|
void kvm_sys_reg_table_init(void); |
|
|
|
/* MMIO helpers */ |
|
void kvm_mmio_write_buf(void *buf, unsigned int len, unsigned long data); |
|
unsigned long kvm_mmio_read_buf(const void *buf, unsigned int len); |
|
|
|
int kvm_handle_mmio_return(struct kvm_vcpu *vcpu); |
|
int io_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa); |
|
|
|
int kvm_perf_init(void); |
|
int kvm_perf_teardown(void); |
|
|
|
long kvm_hypercall_pv_features(struct kvm_vcpu *vcpu); |
|
gpa_t kvm_init_stolen_time(struct kvm_vcpu *vcpu); |
|
void kvm_update_stolen_time(struct kvm_vcpu *vcpu); |
|
|
|
bool kvm_arm_pvtime_supported(void); |
|
int kvm_arm_pvtime_set_attr(struct kvm_vcpu *vcpu, |
|
struct kvm_device_attr *attr); |
|
int kvm_arm_pvtime_get_attr(struct kvm_vcpu *vcpu, |
|
struct kvm_device_attr *attr); |
|
int kvm_arm_pvtime_has_attr(struct kvm_vcpu *vcpu, |
|
struct kvm_device_attr *attr); |
|
|
|
static inline void kvm_arm_pvtime_vcpu_init(struct kvm_vcpu_arch *vcpu_arch) |
|
{ |
|
vcpu_arch->steal.base = GPA_INVALID; |
|
} |
|
|
|
static inline bool kvm_arm_is_pvtime_enabled(struct kvm_vcpu_arch *vcpu_arch) |
|
{ |
|
return (vcpu_arch->steal.base != GPA_INVALID); |
|
} |
|
|
|
void kvm_set_sei_esr(struct kvm_vcpu *vcpu, u64 syndrome); |
|
|
|
struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr); |
|
|
|
DECLARE_KVM_HYP_PER_CPU(struct kvm_host_data, kvm_host_data); |
|
|
|
static inline void kvm_init_host_cpu_context(struct kvm_cpu_context *cpu_ctxt) |
|
{ |
|
/* The host's MPIDR is immutable, so let's set it up at boot time */ |
|
ctxt_sys_reg(cpu_ctxt, MPIDR_EL1) = read_cpuid_mpidr(); |
|
} |
|
|
|
static inline bool kvm_arch_requires_vhe(void) |
|
{ |
|
/* |
|
* The Arm architecture specifies that implementation of SVE |
|
* requires VHE also to be implemented. The KVM code for arm64 |
|
* relies on this when SVE is present: |
|
*/ |
|
if (system_supports_sve()) |
|
return true; |
|
|
|
return false; |
|
} |
|
|
|
void kvm_arm_vcpu_ptrauth_trap(struct kvm_vcpu *vcpu); |
|
|
|
static inline void kvm_arch_hardware_unsetup(void) {} |
|
static inline void kvm_arch_sync_events(struct kvm *kvm) {} |
|
static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {} |
|
static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {} |
|
|
|
void kvm_arm_init_debug(void); |
|
void kvm_arm_vcpu_init_debug(struct kvm_vcpu *vcpu); |
|
void kvm_arm_setup_debug(struct kvm_vcpu *vcpu); |
|
void kvm_arm_clear_debug(struct kvm_vcpu *vcpu); |
|
void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu); |
|
int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu, |
|
struct kvm_device_attr *attr); |
|
int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu, |
|
struct kvm_device_attr *attr); |
|
int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu, |
|
struct kvm_device_attr *attr); |
|
|
|
/* Guest/host FPSIMD coordination helpers */ |
|
int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu); |
|
void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu); |
|
void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu); |
|
void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu); |
|
|
|
static inline bool kvm_pmu_counter_deferred(struct perf_event_attr *attr) |
|
{ |
|
return (!has_vhe() && attr->exclude_host); |
|
} |
|
|
|
#ifdef CONFIG_KVM /* Avoid conflicts with core headers if CONFIG_KVM=n */ |
|
static inline int kvm_arch_vcpu_run_pid_change(struct kvm_vcpu *vcpu) |
|
{ |
|
return kvm_arch_vcpu_run_map_fp(vcpu); |
|
} |
|
|
|
void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr); |
|
void kvm_clr_pmu_events(u32 clr); |
|
|
|
void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu); |
|
void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu); |
|
#else |
|
static inline void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr) {} |
|
static inline void kvm_clr_pmu_events(u32 clr) {} |
|
#endif |
|
|
|
void kvm_vcpu_load_sysregs_vhe(struct kvm_vcpu *vcpu); |
|
void kvm_vcpu_put_sysregs_vhe(struct kvm_vcpu *vcpu); |
|
|
|
int kvm_set_ipa_limit(void); |
|
|
|
#define __KVM_HAVE_ARCH_VM_ALLOC |
|
struct kvm *kvm_arch_alloc_vm(void); |
|
void kvm_arch_free_vm(struct kvm *kvm); |
|
|
|
int kvm_arm_setup_stage2(struct kvm *kvm, unsigned long type); |
|
|
|
int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature); |
|
bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu); |
|
|
|
#define kvm_arm_vcpu_sve_finalized(vcpu) \ |
|
((vcpu)->arch.flags & KVM_ARM64_VCPU_SVE_FINALIZED) |
|
|
|
#define kvm_vcpu_has_pmu(vcpu) \ |
|
(test_bit(KVM_ARM_VCPU_PMU_V3, (vcpu)->arch.features)) |
|
|
|
int kvm_trng_call(struct kvm_vcpu *vcpu); |
|
|
|
#endif /* __ARM64_KVM_HOST_H__ */
|
|
|