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204 lines
6.7 KiB
204 lines
6.7 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Based on arch/arm/include/asm/io.h |
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* |
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* Copyright (C) 1996-2000 Russell King |
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* Copyright (C) 2012 ARM Ltd. |
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*/ |
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#ifndef __ASM_IO_H |
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#define __ASM_IO_H |
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#include <linux/types.h> |
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#include <linux/pgtable.h> |
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#include <asm/byteorder.h> |
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#include <asm/barrier.h> |
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#include <asm/memory.h> |
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#include <asm/early_ioremap.h> |
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#include <asm/alternative.h> |
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#include <asm/cpufeature.h> |
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/* |
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* Generic IO read/write. These perform native-endian accesses. |
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*/ |
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#define __raw_writeb __raw_writeb |
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static inline void __raw_writeb(u8 val, volatile void __iomem *addr) |
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{ |
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asm volatile("strb %w0, [%1]" : : "rZ" (val), "r" (addr)); |
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} |
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#define __raw_writew __raw_writew |
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static inline void __raw_writew(u16 val, volatile void __iomem *addr) |
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{ |
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asm volatile("strh %w0, [%1]" : : "rZ" (val), "r" (addr)); |
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} |
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#define __raw_writel __raw_writel |
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static __always_inline void __raw_writel(u32 val, volatile void __iomem *addr) |
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{ |
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asm volatile("str %w0, [%1]" : : "rZ" (val), "r" (addr)); |
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} |
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#define __raw_writeq __raw_writeq |
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static inline void __raw_writeq(u64 val, volatile void __iomem *addr) |
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{ |
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asm volatile("str %x0, [%1]" : : "rZ" (val), "r" (addr)); |
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} |
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#define __raw_readb __raw_readb |
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static inline u8 __raw_readb(const volatile void __iomem *addr) |
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{ |
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u8 val; |
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asm volatile(ALTERNATIVE("ldrb %w0, [%1]", |
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"ldarb %w0, [%1]", |
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ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE) |
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: "=r" (val) : "r" (addr)); |
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return val; |
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} |
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#define __raw_readw __raw_readw |
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static inline u16 __raw_readw(const volatile void __iomem *addr) |
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{ |
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u16 val; |
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asm volatile(ALTERNATIVE("ldrh %w0, [%1]", |
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"ldarh %w0, [%1]", |
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ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE) |
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: "=r" (val) : "r" (addr)); |
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return val; |
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} |
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#define __raw_readl __raw_readl |
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static __always_inline u32 __raw_readl(const volatile void __iomem *addr) |
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{ |
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u32 val; |
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asm volatile(ALTERNATIVE("ldr %w0, [%1]", |
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"ldar %w0, [%1]", |
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ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE) |
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: "=r" (val) : "r" (addr)); |
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return val; |
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} |
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#define __raw_readq __raw_readq |
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static inline u64 __raw_readq(const volatile void __iomem *addr) |
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{ |
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u64 val; |
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asm volatile(ALTERNATIVE("ldr %0, [%1]", |
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"ldar %0, [%1]", |
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ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE) |
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: "=r" (val) : "r" (addr)); |
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return val; |
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} |
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/* IO barriers */ |
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#define __iormb(v) \ |
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({ \ |
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unsigned long tmp; \ |
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\ |
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dma_rmb(); \ |
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\ |
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/* \ |
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* Create a dummy control dependency from the IO read to any \ |
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* later instructions. This ensures that a subsequent call to \ |
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* udelay() will be ordered due to the ISB in get_cycles(). \ |
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*/ \ |
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asm volatile("eor %0, %1, %1\n" \ |
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"cbnz %0, ." \ |
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: "=r" (tmp) : "r" ((unsigned long)(v)) \ |
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: "memory"); \ |
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}) |
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#define __io_par(v) __iormb(v) |
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#define __iowmb() dma_wmb() |
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#define __iomb() dma_mb() |
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/* |
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* Relaxed I/O memory access primitives. These follow the Device memory |
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* ordering rules but do not guarantee any ordering relative to Normal memory |
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* accesses. |
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*/ |
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#define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; }) |
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#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16)__raw_readw(c)); __r; }) |
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#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; }) |
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#define readq_relaxed(c) ({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; }) |
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#define writeb_relaxed(v,c) ((void)__raw_writeb((v),(c))) |
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#define writew_relaxed(v,c) ((void)__raw_writew((__force u16)cpu_to_le16(v),(c))) |
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#define writel_relaxed(v,c) ((void)__raw_writel((__force u32)cpu_to_le32(v),(c))) |
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#define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c))) |
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/* |
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* I/O memory access primitives. Reads are ordered relative to any |
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* following Normal memory access. Writes are ordered relative to any prior |
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* Normal memory access. |
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*/ |
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#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(__v); __v; }) |
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#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(__v); __v; }) |
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#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(__v); __v; }) |
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#define readq(c) ({ u64 __v = readq_relaxed(c); __iormb(__v); __v; }) |
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#define writeb(v,c) ({ __iowmb(); writeb_relaxed((v),(c)); }) |
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#define writew(v,c) ({ __iowmb(); writew_relaxed((v),(c)); }) |
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#define writel(v,c) ({ __iowmb(); writel_relaxed((v),(c)); }) |
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#define writeq(v,c) ({ __iowmb(); writeq_relaxed((v),(c)); }) |
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/* |
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* I/O port access primitives. |
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*/ |
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#define arch_has_dev_port() (1) |
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#define IO_SPACE_LIMIT (PCI_IO_SIZE - 1) |
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#define PCI_IOBASE ((void __iomem *)PCI_IO_START) |
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/* |
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* String version of I/O memory access operations. |
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*/ |
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extern void __memcpy_fromio(void *, const volatile void __iomem *, size_t); |
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extern void __memcpy_toio(volatile void __iomem *, const void *, size_t); |
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extern void __memset_io(volatile void __iomem *, int, size_t); |
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#define memset_io(c,v,l) __memset_io((c),(v),(l)) |
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#define memcpy_fromio(a,c,l) __memcpy_fromio((a),(c),(l)) |
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#define memcpy_toio(c,a,l) __memcpy_toio((c),(a),(l)) |
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/* |
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* I/O memory mapping functions. |
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*/ |
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extern void __iomem *__ioremap(phys_addr_t phys_addr, size_t size, pgprot_t prot); |
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extern void iounmap(volatile void __iomem *addr); |
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extern void __iomem *ioremap_cache(phys_addr_t phys_addr, size_t size); |
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#define ioremap(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE)) |
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#define ioremap_wc(addr, size) __ioremap((addr), (size), __pgprot(PROT_NORMAL_NC)) |
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/* |
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* PCI configuration space mapping function. |
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* |
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* The PCI specification disallows posted write configuration transactions. |
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* Add an arch specific pci_remap_cfgspace() definition that is implemented |
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* through nGnRnE device memory attribute as recommended by the ARM v8 |
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* Architecture reference manual Issue A.k B2.8.2 "Device memory". |
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*/ |
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#define pci_remap_cfgspace(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRnE)) |
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/* |
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* io{read,write}{16,32,64}be() macros |
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*/ |
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#define ioread16be(p) ({ __u16 __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(__v); __v; }) |
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#define ioread32be(p) ({ __u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(__v); __v; }) |
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#define ioread64be(p) ({ __u64 __v = be64_to_cpu((__force __be64)__raw_readq(p)); __iormb(__v); __v; }) |
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#define iowrite16be(v,p) ({ __iowmb(); __raw_writew((__force __u16)cpu_to_be16(v), p); }) |
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#define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); }) |
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#define iowrite64be(v,p) ({ __iowmb(); __raw_writeq((__force __u64)cpu_to_be64(v), p); }) |
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#include <asm-generic/io.h> |
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/* |
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* More restrictive address range checking than the default implementation |
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* (PHYS_OFFSET and PHYS_MASK taken into account). |
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*/ |
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#define ARCH_HAS_VALID_PHYS_ADDR_RANGE |
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extern int valid_phys_addr_range(phys_addr_t addr, size_t size); |
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extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size); |
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#endif /* __ASM_IO_H */
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