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157 lines
4.0 KiB
157 lines
4.0 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Copyright (C) 2012 ARM Ltd. |
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*/ |
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#ifndef __ASM_HW_BREAKPOINT_H |
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#define __ASM_HW_BREAKPOINT_H |
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#include <asm/cputype.h> |
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#include <asm/cpufeature.h> |
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#include <asm/sysreg.h> |
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#include <asm/virt.h> |
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struct arch_hw_breakpoint_ctrl { |
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u32 __reserved : 19, |
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len : 8, |
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type : 2, |
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privilege : 2, |
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enabled : 1; |
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}; |
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struct arch_hw_breakpoint { |
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u64 address; |
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u64 trigger; |
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struct arch_hw_breakpoint_ctrl ctrl; |
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}; |
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/* Privilege Levels */ |
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#define AARCH64_BREAKPOINT_EL1 1 |
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#define AARCH64_BREAKPOINT_EL0 2 |
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#define DBG_HMC_HYP (1 << 13) |
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static inline u32 encode_ctrl_reg(struct arch_hw_breakpoint_ctrl ctrl) |
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{ |
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u32 val = (ctrl.len << 5) | (ctrl.type << 3) | (ctrl.privilege << 1) | |
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ctrl.enabled; |
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if (is_kernel_in_hyp_mode() && ctrl.privilege == AARCH64_BREAKPOINT_EL1) |
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val |= DBG_HMC_HYP; |
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return val; |
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} |
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static inline void decode_ctrl_reg(u32 reg, |
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struct arch_hw_breakpoint_ctrl *ctrl) |
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{ |
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ctrl->enabled = reg & 0x1; |
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reg >>= 1; |
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ctrl->privilege = reg & 0x3; |
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reg >>= 2; |
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ctrl->type = reg & 0x3; |
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reg >>= 2; |
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ctrl->len = reg & 0xff; |
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} |
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/* Breakpoint */ |
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#define ARM_BREAKPOINT_EXECUTE 0 |
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/* Watchpoints */ |
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#define ARM_BREAKPOINT_LOAD 1 |
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#define ARM_BREAKPOINT_STORE 2 |
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#define AARCH64_ESR_ACCESS_MASK (1 << 6) |
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/* Lengths */ |
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#define ARM_BREAKPOINT_LEN_1 0x1 |
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#define ARM_BREAKPOINT_LEN_2 0x3 |
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#define ARM_BREAKPOINT_LEN_3 0x7 |
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#define ARM_BREAKPOINT_LEN_4 0xf |
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#define ARM_BREAKPOINT_LEN_5 0x1f |
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#define ARM_BREAKPOINT_LEN_6 0x3f |
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#define ARM_BREAKPOINT_LEN_7 0x7f |
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#define ARM_BREAKPOINT_LEN_8 0xff |
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/* Kernel stepping */ |
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#define ARM_KERNEL_STEP_NONE 0 |
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#define ARM_KERNEL_STEP_ACTIVE 1 |
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#define ARM_KERNEL_STEP_SUSPEND 2 |
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/* |
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* Limits. |
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* Changing these will require modifications to the register accessors. |
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*/ |
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#define ARM_MAX_BRP 16 |
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#define ARM_MAX_WRP 16 |
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/* Virtual debug register bases. */ |
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#define AARCH64_DBG_REG_BVR 0 |
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#define AARCH64_DBG_REG_BCR (AARCH64_DBG_REG_BVR + ARM_MAX_BRP) |
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#define AARCH64_DBG_REG_WVR (AARCH64_DBG_REG_BCR + ARM_MAX_BRP) |
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#define AARCH64_DBG_REG_WCR (AARCH64_DBG_REG_WVR + ARM_MAX_WRP) |
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/* Debug register names. */ |
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#define AARCH64_DBG_REG_NAME_BVR bvr |
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#define AARCH64_DBG_REG_NAME_BCR bcr |
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#define AARCH64_DBG_REG_NAME_WVR wvr |
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#define AARCH64_DBG_REG_NAME_WCR wcr |
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/* Accessor macros for the debug registers. */ |
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#define AARCH64_DBG_READ(N, REG, VAL) do {\ |
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VAL = read_sysreg(dbg##REG##N##_el1);\ |
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} while (0) |
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#define AARCH64_DBG_WRITE(N, REG, VAL) do {\ |
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write_sysreg(VAL, dbg##REG##N##_el1);\ |
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} while (0) |
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struct task_struct; |
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struct notifier_block; |
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struct perf_event_attr; |
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struct perf_event; |
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struct pmu; |
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extern int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl, |
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int *gen_len, int *gen_type, int *offset); |
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extern int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw); |
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extern int hw_breakpoint_arch_parse(struct perf_event *bp, |
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const struct perf_event_attr *attr, |
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struct arch_hw_breakpoint *hw); |
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extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused, |
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unsigned long val, void *data); |
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extern int arch_install_hw_breakpoint(struct perf_event *bp); |
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extern void arch_uninstall_hw_breakpoint(struct perf_event *bp); |
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extern void hw_breakpoint_pmu_read(struct perf_event *bp); |
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extern int hw_breakpoint_slots(int type); |
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#ifdef CONFIG_HAVE_HW_BREAKPOINT |
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extern void hw_breakpoint_thread_switch(struct task_struct *next); |
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extern void ptrace_hw_copy_thread(struct task_struct *task); |
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#else |
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static inline void hw_breakpoint_thread_switch(struct task_struct *next) |
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{ |
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} |
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static inline void ptrace_hw_copy_thread(struct task_struct *task) |
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{ |
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} |
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#endif |
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/* Determine number of BRP registers available. */ |
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static inline int get_num_brps(void) |
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{ |
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u64 dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); |
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return 1 + |
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cpuid_feature_extract_unsigned_field(dfr0, |
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ID_AA64DFR0_BRPS_SHIFT); |
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} |
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/* Determine number of WRP registers available. */ |
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static inline int get_num_wrps(void) |
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{ |
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u64 dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); |
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return 1 + |
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cpuid_feature_extract_unsigned_field(dfr0, |
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ID_AA64DFR0_WRPS_SHIFT); |
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} |
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#endif /* __ASM_BREAKPOINT_H */
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