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246 lines
5.5 KiB
246 lines
5.5 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* arch/arm64/include/asm/arch_timer.h |
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* |
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* Copyright (C) 2012 ARM Ltd. |
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* Author: Marc Zyngier <[email protected]> |
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*/ |
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#ifndef __ASM_ARCH_TIMER_H |
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#define __ASM_ARCH_TIMER_H |
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#include <asm/barrier.h> |
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#include <asm/hwcap.h> |
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#include <asm/sysreg.h> |
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#include <linux/bug.h> |
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#include <linux/init.h> |
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#include <linux/jump_label.h> |
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#include <linux/smp.h> |
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#include <linux/types.h> |
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#include <clocksource/arm_arch_timer.h> |
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#if IS_ENABLED(CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND) |
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#define has_erratum_handler(h) \ |
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({ \ |
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const struct arch_timer_erratum_workaround *__wa; \ |
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__wa = __this_cpu_read(timer_unstable_counter_workaround); \ |
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(__wa && __wa->h); \ |
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}) |
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#define erratum_handler(h) \ |
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({ \ |
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const struct arch_timer_erratum_workaround *__wa; \ |
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__wa = __this_cpu_read(timer_unstable_counter_workaround); \ |
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(__wa && __wa->h) ? __wa->h : arch_timer_##h; \ |
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}) |
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#else |
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#define has_erratum_handler(h) false |
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#define erratum_handler(h) (arch_timer_##h) |
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#endif |
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enum arch_timer_erratum_match_type { |
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ate_match_dt, |
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ate_match_local_cap_id, |
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ate_match_acpi_oem_info, |
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}; |
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struct clock_event_device; |
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struct arch_timer_erratum_workaround { |
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enum arch_timer_erratum_match_type match_type; |
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const void *id; |
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const char *desc; |
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u32 (*read_cntp_tval_el0)(void); |
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u32 (*read_cntv_tval_el0)(void); |
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u64 (*read_cntpct_el0)(void); |
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u64 (*read_cntvct_el0)(void); |
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int (*set_next_event_phys)(unsigned long, struct clock_event_device *); |
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int (*set_next_event_virt)(unsigned long, struct clock_event_device *); |
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bool disable_compat_vdso; |
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}; |
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DECLARE_PER_CPU(const struct arch_timer_erratum_workaround *, |
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timer_unstable_counter_workaround); |
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/* inline sysreg accessors that make erratum_handler() work */ |
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static inline notrace u32 arch_timer_read_cntp_tval_el0(void) |
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{ |
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return read_sysreg(cntp_tval_el0); |
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} |
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static inline notrace u32 arch_timer_read_cntv_tval_el0(void) |
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{ |
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return read_sysreg(cntv_tval_el0); |
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} |
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static inline notrace u64 arch_timer_read_cntpct_el0(void) |
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{ |
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return read_sysreg(cntpct_el0); |
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} |
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static inline notrace u64 arch_timer_read_cntvct_el0(void) |
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{ |
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return read_sysreg(cntvct_el0); |
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} |
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#define arch_timer_reg_read_stable(reg) \ |
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({ \ |
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u64 _val; \ |
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\ |
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preempt_disable_notrace(); \ |
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_val = erratum_handler(read_ ## reg)(); \ |
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preempt_enable_notrace(); \ |
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\ |
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_val; \ |
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}) |
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/* |
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* These register accessors are marked inline so the compiler can |
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* nicely work out which register we want, and chuck away the rest of |
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* the code. |
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*/ |
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static __always_inline |
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void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val) |
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{ |
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if (access == ARCH_TIMER_PHYS_ACCESS) { |
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switch (reg) { |
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case ARCH_TIMER_REG_CTRL: |
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write_sysreg(val, cntp_ctl_el0); |
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break; |
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case ARCH_TIMER_REG_TVAL: |
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write_sysreg(val, cntp_tval_el0); |
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break; |
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} |
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} else if (access == ARCH_TIMER_VIRT_ACCESS) { |
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switch (reg) { |
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case ARCH_TIMER_REG_CTRL: |
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write_sysreg(val, cntv_ctl_el0); |
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break; |
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case ARCH_TIMER_REG_TVAL: |
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write_sysreg(val, cntv_tval_el0); |
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break; |
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} |
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} |
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isb(); |
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} |
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static __always_inline |
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u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg) |
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{ |
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if (access == ARCH_TIMER_PHYS_ACCESS) { |
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switch (reg) { |
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case ARCH_TIMER_REG_CTRL: |
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return read_sysreg(cntp_ctl_el0); |
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case ARCH_TIMER_REG_TVAL: |
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return arch_timer_reg_read_stable(cntp_tval_el0); |
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} |
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} else if (access == ARCH_TIMER_VIRT_ACCESS) { |
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switch (reg) { |
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case ARCH_TIMER_REG_CTRL: |
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return read_sysreg(cntv_ctl_el0); |
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case ARCH_TIMER_REG_TVAL: |
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return arch_timer_reg_read_stable(cntv_tval_el0); |
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} |
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} |
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BUG(); |
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} |
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static inline u32 arch_timer_get_cntfrq(void) |
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{ |
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return read_sysreg(cntfrq_el0); |
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} |
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static inline u32 arch_timer_get_cntkctl(void) |
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{ |
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return read_sysreg(cntkctl_el1); |
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} |
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static inline void arch_timer_set_cntkctl(u32 cntkctl) |
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{ |
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write_sysreg(cntkctl, cntkctl_el1); |
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isb(); |
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} |
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/* |
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* Ensure that reads of the counter are treated the same as memory reads |
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* for the purposes of ordering by subsequent memory barriers. |
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* |
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* This insanity brought to you by speculative system register reads, |
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* out-of-order memory accesses, sequence locks and Thomas Gleixner. |
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* |
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* http://lists.infradead.org/pipermail/linux-arm-kernel/2019-February/631195.html |
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*/ |
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#define arch_counter_enforce_ordering(val) do { \ |
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u64 tmp, _val = (val); \ |
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\ |
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asm volatile( \ |
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" eor %0, %1, %1\n" \ |
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" add %0, sp, %0\n" \ |
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" ldr xzr, [%0]" \ |
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: "=r" (tmp) : "r" (_val)); \ |
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} while (0) |
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static __always_inline u64 __arch_counter_get_cntpct_stable(void) |
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{ |
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u64 cnt; |
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isb(); |
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cnt = arch_timer_reg_read_stable(cntpct_el0); |
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arch_counter_enforce_ordering(cnt); |
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return cnt; |
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} |
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static __always_inline u64 __arch_counter_get_cntpct(void) |
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{ |
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u64 cnt; |
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isb(); |
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cnt = read_sysreg(cntpct_el0); |
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arch_counter_enforce_ordering(cnt); |
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return cnt; |
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} |
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static __always_inline u64 __arch_counter_get_cntvct_stable(void) |
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{ |
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u64 cnt; |
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isb(); |
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cnt = arch_timer_reg_read_stable(cntvct_el0); |
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arch_counter_enforce_ordering(cnt); |
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return cnt; |
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} |
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static __always_inline u64 __arch_counter_get_cntvct(void) |
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{ |
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u64 cnt; |
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isb(); |
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cnt = read_sysreg(cntvct_el0); |
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arch_counter_enforce_ordering(cnt); |
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return cnt; |
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} |
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#undef arch_counter_enforce_ordering |
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static inline int arch_timer_arch_init(void) |
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{ |
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return 0; |
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} |
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static inline void arch_timer_set_evtstrm_feature(void) |
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{ |
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cpu_set_named_feature(EVTSTRM); |
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#ifdef CONFIG_COMPAT |
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compat_elf_hwcap |= COMPAT_HWCAP_EVTSTRM; |
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#endif |
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} |
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static inline bool arch_timer_have_evtstrm_feature(void) |
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{ |
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return cpu_have_named_feature(EVTSTRM); |
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} |
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#endif
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