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883 lines
23 KiB
883 lines
23 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* dts file for Xilinx ZynqMP |
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* |
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* (C) Copyright 2014 - 2019, Xilinx, Inc. |
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* |
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* Michal Simek <[email protected]> |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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*/ |
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#include <dt-bindings/dma/xlnx-zynqmp-dpdma.h> |
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#include <dt-bindings/power/xlnx-zynqmp-power.h> |
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#include <dt-bindings/reset/xlnx-zynqmp-resets.h> |
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/ { |
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compatible = "xlnx,zynqmp"; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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cpus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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cpu0: cpu@0 { |
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compatible = "arm,cortex-a53"; |
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device_type = "cpu"; |
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enable-method = "psci"; |
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operating-points-v2 = <&cpu_opp_table>; |
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reg = <0x0>; |
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cpu-idle-states = <&CPU_SLEEP_0>; |
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}; |
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cpu1: cpu@1 { |
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compatible = "arm,cortex-a53"; |
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device_type = "cpu"; |
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enable-method = "psci"; |
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reg = <0x1>; |
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operating-points-v2 = <&cpu_opp_table>; |
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cpu-idle-states = <&CPU_SLEEP_0>; |
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}; |
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cpu2: cpu@2 { |
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compatible = "arm,cortex-a53"; |
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device_type = "cpu"; |
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enable-method = "psci"; |
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reg = <0x2>; |
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operating-points-v2 = <&cpu_opp_table>; |
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cpu-idle-states = <&CPU_SLEEP_0>; |
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}; |
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cpu3: cpu@3 { |
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compatible = "arm,cortex-a53"; |
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device_type = "cpu"; |
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enable-method = "psci"; |
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reg = <0x3>; |
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operating-points-v2 = <&cpu_opp_table>; |
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cpu-idle-states = <&CPU_SLEEP_0>; |
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}; |
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idle-states { |
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entry-method = "psci"; |
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CPU_SLEEP_0: cpu-sleep-0 { |
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compatible = "arm,idle-state"; |
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arm,psci-suspend-param = <0x40000000>; |
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local-timer-stop; |
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entry-latency-us = <300>; |
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exit-latency-us = <600>; |
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min-residency-us = <10000>; |
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}; |
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}; |
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}; |
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cpu_opp_table: cpu-opp-table { |
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compatible = "operating-points-v2"; |
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opp-shared; |
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opp00 { |
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opp-hz = /bits/ 64 <1199999988>; |
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opp-microvolt = <1000000>; |
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clock-latency-ns = <500000>; |
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}; |
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opp01 { |
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opp-hz = /bits/ 64 <599999994>; |
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opp-microvolt = <1000000>; |
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clock-latency-ns = <500000>; |
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}; |
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opp02 { |
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opp-hz = /bits/ 64 <399999996>; |
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opp-microvolt = <1000000>; |
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clock-latency-ns = <500000>; |
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}; |
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opp03 { |
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opp-hz = /bits/ 64 <299999997>; |
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opp-microvolt = <1000000>; |
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clock-latency-ns = <500000>; |
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}; |
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}; |
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zynqmp_ipi: zynqmp_ipi { |
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compatible = "xlnx,zynqmp-ipi-mailbox"; |
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interrupt-parent = <&gic>; |
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interrupts = <0 35 4>; |
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xlnx,ipi-id = <0>; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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ranges; |
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ipi_mailbox_pmu1: mailbox@ff990400 { |
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reg = <0x0 0xff9905c0 0x0 0x20>, |
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<0x0 0xff9905e0 0x0 0x20>, |
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<0x0 0xff990e80 0x0 0x20>, |
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<0x0 0xff990ea0 0x0 0x20>; |
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reg-names = "local_request_region", |
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"local_response_region", |
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"remote_request_region", |
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"remote_response_region"; |
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#mbox-cells = <1>; |
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xlnx,ipi-id = <4>; |
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}; |
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}; |
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dcc: dcc { |
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compatible = "arm,dcc"; |
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status = "disabled"; |
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}; |
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pmu { |
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compatible = "arm,armv8-pmuv3"; |
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interrupt-parent = <&gic>; |
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interrupts = <0 143 4>, |
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<0 144 4>, |
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<0 145 4>, |
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<0 146 4>; |
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}; |
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psci { |
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compatible = "arm,psci-0.2"; |
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method = "smc"; |
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}; |
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firmware { |
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zynqmp_firmware: zynqmp-firmware { |
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compatible = "xlnx,zynqmp-firmware"; |
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#power-domain-cells = <1>; |
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method = "smc"; |
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zynqmp_power: zynqmp-power { |
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compatible = "xlnx,zynqmp-power"; |
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interrupt-parent = <&gic>; |
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interrupts = <0 35 4>; |
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mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; |
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mbox-names = "tx", "rx"; |
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}; |
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zynqmp_clk: clock-controller { |
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#clock-cells = <1>; |
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compatible = "xlnx,zynqmp-clk"; |
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clocks = <&pss_ref_clk>, |
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<&video_clk>, |
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<&pss_alt_ref_clk>, |
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<&aux_ref_clk>, |
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<>_crx_ref_clk>; |
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clock-names = "pss_ref_clk", |
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"video_clk", |
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"pss_alt_ref_clk", |
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"aux_ref_clk", |
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"gt_crx_ref_clk"; |
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}; |
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nvmem_firmware { |
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compatible = "xlnx,zynqmp-nvmem-fw"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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soc_revision: soc_revision@0 { |
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reg = <0x0 0x4>; |
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}; |
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}; |
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zynqmp_pcap: pcap { |
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compatible = "xlnx,zynqmp-pcap-fpga"; |
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}; |
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xlnx_aes: zynqmp-aes { |
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compatible = "xlnx,zynqmp-aes"; |
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}; |
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zynqmp_reset: reset-controller { |
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compatible = "xlnx,zynqmp-reset"; |
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#reset-cells = <1>; |
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}; |
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}; |
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}; |
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timer { |
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compatible = "arm,armv8-timer"; |
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interrupt-parent = <&gic>; |
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interrupts = <1 13 0xf08>, |
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<1 14 0xf08>, |
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<1 11 0xf08>, |
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<1 10 0xf08>; |
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}; |
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fpga_full: fpga-full { |
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compatible = "fpga-region"; |
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fpga-mgr = <&zynqmp_pcap>; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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ranges; |
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}; |
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amba: axi { |
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compatible = "simple-bus"; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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ranges; |
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can0: can@ff060000 { |
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compatible = "xlnx,zynq-can-1.0"; |
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status = "disabled"; |
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clock-names = "can_clk", "pclk"; |
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reg = <0x0 0xff060000 0x0 0x1000>; |
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interrupts = <0 23 4>; |
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interrupt-parent = <&gic>; |
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tx-fifo-depth = <0x40>; |
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rx-fifo-depth = <0x40>; |
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power-domains = <&zynqmp_firmware PD_CAN_0>; |
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}; |
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can1: can@ff070000 { |
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compatible = "xlnx,zynq-can-1.0"; |
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status = "disabled"; |
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clock-names = "can_clk", "pclk"; |
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reg = <0x0 0xff070000 0x0 0x1000>; |
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interrupts = <0 24 4>; |
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interrupt-parent = <&gic>; |
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tx-fifo-depth = <0x40>; |
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rx-fifo-depth = <0x40>; |
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power-domains = <&zynqmp_firmware PD_CAN_1>; |
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}; |
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cci: cci@fd6e0000 { |
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compatible = "arm,cci-400"; |
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reg = <0x0 0xfd6e0000 0x0 0x9000>; |
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ranges = <0x0 0x0 0xfd6e0000 0x10000>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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pmu@9000 { |
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compatible = "arm,cci-400-pmu,r1"; |
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reg = <0x9000 0x5000>; |
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interrupt-parent = <&gic>; |
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interrupts = <0 123 4>, |
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<0 123 4>, |
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<0 123 4>, |
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<0 123 4>, |
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<0 123 4>; |
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}; |
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}; |
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/* GDMA */ |
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fpd_dma_chan1: dma@fd500000 { |
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status = "disabled"; |
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compatible = "xlnx,zynqmp-dma-1.0"; |
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reg = <0x0 0xfd500000 0x0 0x1000>; |
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interrupt-parent = <&gic>; |
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interrupts = <0 124 4>; |
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clock-names = "clk_main", "clk_apb"; |
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xlnx,bus-width = <128>; |
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#stream-id-cells = <1>; |
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iommus = <&smmu 0x14e8>; |
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power-domains = <&zynqmp_firmware PD_GDMA>; |
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}; |
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fpd_dma_chan2: dma@fd510000 { |
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status = "disabled"; |
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compatible = "xlnx,zynqmp-dma-1.0"; |
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reg = <0x0 0xfd510000 0x0 0x1000>; |
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interrupt-parent = <&gic>; |
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interrupts = <0 125 4>; |
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clock-names = "clk_main", "clk_apb"; |
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xlnx,bus-width = <128>; |
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#stream-id-cells = <1>; |
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iommus = <&smmu 0x14e9>; |
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power-domains = <&zynqmp_firmware PD_GDMA>; |
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}; |
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fpd_dma_chan3: dma@fd520000 { |
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status = "disabled"; |
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compatible = "xlnx,zynqmp-dma-1.0"; |
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reg = <0x0 0xfd520000 0x0 0x1000>; |
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interrupt-parent = <&gic>; |
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interrupts = <0 126 4>; |
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clock-names = "clk_main", "clk_apb"; |
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xlnx,bus-width = <128>; |
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#stream-id-cells = <1>; |
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iommus = <&smmu 0x14ea>; |
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power-domains = <&zynqmp_firmware PD_GDMA>; |
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}; |
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fpd_dma_chan4: dma@fd530000 { |
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status = "disabled"; |
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compatible = "xlnx,zynqmp-dma-1.0"; |
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reg = <0x0 0xfd530000 0x0 0x1000>; |
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interrupt-parent = <&gic>; |
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interrupts = <0 127 4>; |
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clock-names = "clk_main", "clk_apb"; |
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xlnx,bus-width = <128>; |
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#stream-id-cells = <1>; |
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iommus = <&smmu 0x14eb>; |
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power-domains = <&zynqmp_firmware PD_GDMA>; |
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}; |
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fpd_dma_chan5: dma@fd540000 { |
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status = "disabled"; |
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compatible = "xlnx,zynqmp-dma-1.0"; |
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reg = <0x0 0xfd540000 0x0 0x1000>; |
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interrupt-parent = <&gic>; |
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interrupts = <0 128 4>; |
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clock-names = "clk_main", "clk_apb"; |
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xlnx,bus-width = <128>; |
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#stream-id-cells = <1>; |
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iommus = <&smmu 0x14ec>; |
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power-domains = <&zynqmp_firmware PD_GDMA>; |
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}; |
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fpd_dma_chan6: dma@fd550000 { |
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status = "disabled"; |
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compatible = "xlnx,zynqmp-dma-1.0"; |
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reg = <0x0 0xfd550000 0x0 0x1000>; |
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interrupt-parent = <&gic>; |
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interrupts = <0 129 4>; |
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clock-names = "clk_main", "clk_apb"; |
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xlnx,bus-width = <128>; |
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#stream-id-cells = <1>; |
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iommus = <&smmu 0x14ed>; |
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power-domains = <&zynqmp_firmware PD_GDMA>; |
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}; |
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fpd_dma_chan7: dma@fd560000 { |
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status = "disabled"; |
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compatible = "xlnx,zynqmp-dma-1.0"; |
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reg = <0x0 0xfd560000 0x0 0x1000>; |
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interrupt-parent = <&gic>; |
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interrupts = <0 130 4>; |
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clock-names = "clk_main", "clk_apb"; |
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xlnx,bus-width = <128>; |
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#stream-id-cells = <1>; |
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iommus = <&smmu 0x14ee>; |
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power-domains = <&zynqmp_firmware PD_GDMA>; |
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}; |
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fpd_dma_chan8: dma@fd570000 { |
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status = "disabled"; |
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compatible = "xlnx,zynqmp-dma-1.0"; |
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reg = <0x0 0xfd570000 0x0 0x1000>; |
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interrupt-parent = <&gic>; |
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interrupts = <0 131 4>; |
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clock-names = "clk_main", "clk_apb"; |
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xlnx,bus-width = <128>; |
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#stream-id-cells = <1>; |
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iommus = <&smmu 0x14ef>; |
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power-domains = <&zynqmp_firmware PD_GDMA>; |
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}; |
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gic: interrupt-controller@f9010000 { |
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compatible = "arm,gic-400"; |
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#address-cells = <0>; |
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#interrupt-cells = <3>; |
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reg = <0x0 0xf9010000 0x0 0x10000>, |
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<0x0 0xf9020000 0x0 0x20000>, |
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<0x0 0xf9040000 0x0 0x20000>, |
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<0x0 0xf9060000 0x0 0x20000>; |
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interrupt-controller; |
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interrupt-parent = <&gic>; |
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interrupts = <1 9 0xf04>; |
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}; |
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/* LPDDMA default allows only secured access. inorder to enable |
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* These dma channels, Users should ensure that these dma |
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* Channels are allowed for non secure access. |
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*/ |
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lpd_dma_chan1: dma@ffa80000 { |
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status = "disabled"; |
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compatible = "xlnx,zynqmp-dma-1.0"; |
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reg = <0x0 0xffa80000 0x0 0x1000>; |
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interrupt-parent = <&gic>; |
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interrupts = <0 77 4>; |
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clock-names = "clk_main", "clk_apb"; |
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xlnx,bus-width = <64>; |
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#stream-id-cells = <1>; |
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iommus = <&smmu 0x868>; |
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power-domains = <&zynqmp_firmware PD_ADMA>; |
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}; |
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lpd_dma_chan2: dma@ffa90000 { |
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status = "disabled"; |
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compatible = "xlnx,zynqmp-dma-1.0"; |
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reg = <0x0 0xffa90000 0x0 0x1000>; |
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interrupt-parent = <&gic>; |
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interrupts = <0 78 4>; |
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clock-names = "clk_main", "clk_apb"; |
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xlnx,bus-width = <64>; |
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#stream-id-cells = <1>; |
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iommus = <&smmu 0x869>; |
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power-domains = <&zynqmp_firmware PD_ADMA>; |
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}; |
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lpd_dma_chan3: dma@ffaa0000 { |
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status = "disabled"; |
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compatible = "xlnx,zynqmp-dma-1.0"; |
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reg = <0x0 0xffaa0000 0x0 0x1000>; |
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interrupt-parent = <&gic>; |
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interrupts = <0 79 4>; |
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clock-names = "clk_main", "clk_apb"; |
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xlnx,bus-width = <64>; |
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#stream-id-cells = <1>; |
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iommus = <&smmu 0x86a>; |
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power-domains = <&zynqmp_firmware PD_ADMA>; |
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}; |
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lpd_dma_chan4: dma@ffab0000 { |
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status = "disabled"; |
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compatible = "xlnx,zynqmp-dma-1.0"; |
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reg = <0x0 0xffab0000 0x0 0x1000>; |
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interrupt-parent = <&gic>; |
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interrupts = <0 80 4>; |
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clock-names = "clk_main", "clk_apb"; |
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xlnx,bus-width = <64>; |
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#stream-id-cells = <1>; |
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iommus = <&smmu 0x86b>; |
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power-domains = <&zynqmp_firmware PD_ADMA>; |
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}; |
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lpd_dma_chan5: dma@ffac0000 { |
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status = "disabled"; |
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compatible = "xlnx,zynqmp-dma-1.0"; |
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reg = <0x0 0xffac0000 0x0 0x1000>; |
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interrupt-parent = <&gic>; |
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interrupts = <0 81 4>; |
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clock-names = "clk_main", "clk_apb"; |
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xlnx,bus-width = <64>; |
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#stream-id-cells = <1>; |
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iommus = <&smmu 0x86c>; |
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power-domains = <&zynqmp_firmware PD_ADMA>; |
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}; |
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lpd_dma_chan6: dma@ffad0000 { |
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status = "disabled"; |
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compatible = "xlnx,zynqmp-dma-1.0"; |
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reg = <0x0 0xffad0000 0x0 0x1000>; |
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interrupt-parent = <&gic>; |
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interrupts = <0 82 4>; |
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clock-names = "clk_main", "clk_apb"; |
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xlnx,bus-width = <64>; |
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#stream-id-cells = <1>; |
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iommus = <&smmu 0x86d>; |
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power-domains = <&zynqmp_firmware PD_ADMA>; |
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}; |
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lpd_dma_chan7: dma@ffae0000 { |
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status = "disabled"; |
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compatible = "xlnx,zynqmp-dma-1.0"; |
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reg = <0x0 0xffae0000 0x0 0x1000>; |
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interrupt-parent = <&gic>; |
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interrupts = <0 83 4>; |
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clock-names = "clk_main", "clk_apb"; |
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xlnx,bus-width = <64>; |
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#stream-id-cells = <1>; |
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iommus = <&smmu 0x86e>; |
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power-domains = <&zynqmp_firmware PD_ADMA>; |
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}; |
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lpd_dma_chan8: dma@ffaf0000 { |
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status = "disabled"; |
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compatible = "xlnx,zynqmp-dma-1.0"; |
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reg = <0x0 0xffaf0000 0x0 0x1000>; |
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interrupt-parent = <&gic>; |
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interrupts = <0 84 4>; |
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clock-names = "clk_main", "clk_apb"; |
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xlnx,bus-width = <64>; |
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#stream-id-cells = <1>; |
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iommus = <&smmu 0x86f>; |
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power-domains = <&zynqmp_firmware PD_ADMA>; |
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}; |
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mc: memory-controller@fd070000 { |
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compatible = "xlnx,zynqmp-ddrc-2.40a"; |
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reg = <0x0 0xfd070000 0x0 0x30000>; |
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interrupt-parent = <&gic>; |
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interrupts = <0 112 4>; |
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}; |
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nand0: nand-controller@ff100000 { |
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compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10"; |
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status = "disabled"; |
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reg = <0x0 0xff100000 0x0 0x1000>; |
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clock-names = "controller", "bus"; |
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interrupt-parent = <&gic>; |
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interrupts = <0 14 4>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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#stream-id-cells = <1>; |
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iommus = <&smmu 0x872>; |
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power-domains = <&zynqmp_firmware PD_NAND>; |
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}; |
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gem0: ethernet@ff0b0000 { |
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compatible = "cdns,zynqmp-gem", "cdns,gem"; |
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status = "disabled"; |
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interrupt-parent = <&gic>; |
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interrupts = <0 57 4>, <0 57 4>; |
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reg = <0x0 0xff0b0000 0x0 0x1000>; |
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clock-names = "pclk", "hclk", "tx_clk"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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#stream-id-cells = <1>; |
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iommus = <&smmu 0x874>; |
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power-domains = <&zynqmp_firmware PD_ETH_0>; |
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}; |
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gem1: ethernet@ff0c0000 { |
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compatible = "cdns,zynqmp-gem", "cdns,gem"; |
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status = "disabled"; |
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interrupt-parent = <&gic>; |
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interrupts = <0 59 4>, <0 59 4>; |
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reg = <0x0 0xff0c0000 0x0 0x1000>; |
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clock-names = "pclk", "hclk", "tx_clk"; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
#stream-id-cells = <1>; |
|
iommus = <&smmu 0x875>; |
|
power-domains = <&zynqmp_firmware PD_ETH_1>; |
|
}; |
|
|
|
gem2: ethernet@ff0d0000 { |
|
compatible = "cdns,zynqmp-gem", "cdns,gem"; |
|
status = "disabled"; |
|
interrupt-parent = <&gic>; |
|
interrupts = <0 61 4>, <0 61 4>; |
|
reg = <0x0 0xff0d0000 0x0 0x1000>; |
|
clock-names = "pclk", "hclk", "tx_clk"; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
#stream-id-cells = <1>; |
|
iommus = <&smmu 0x876>; |
|
power-domains = <&zynqmp_firmware PD_ETH_2>; |
|
}; |
|
|
|
gem3: ethernet@ff0e0000 { |
|
compatible = "cdns,zynqmp-gem", "cdns,gem"; |
|
status = "disabled"; |
|
interrupt-parent = <&gic>; |
|
interrupts = <0 63 4>, <0 63 4>; |
|
reg = <0x0 0xff0e0000 0x0 0x1000>; |
|
clock-names = "pclk", "hclk", "tx_clk"; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
#stream-id-cells = <1>; |
|
iommus = <&smmu 0x877>; |
|
power-domains = <&zynqmp_firmware PD_ETH_3>; |
|
}; |
|
|
|
gpio: gpio@ff0a0000 { |
|
compatible = "xlnx,zynqmp-gpio-1.0"; |
|
status = "disabled"; |
|
#address-cells = <0>; |
|
#gpio-cells = <0x2>; |
|
gpio-controller; |
|
interrupt-parent = <&gic>; |
|
interrupts = <0 16 4>; |
|
interrupt-controller; |
|
#interrupt-cells = <2>; |
|
reg = <0x0 0xff0a0000 0x0 0x1000>; |
|
power-domains = <&zynqmp_firmware PD_GPIO>; |
|
}; |
|
|
|
i2c0: i2c@ff020000 { |
|
compatible = "cdns,i2c-r1p14"; |
|
status = "disabled"; |
|
interrupt-parent = <&gic>; |
|
interrupts = <0 17 4>; |
|
reg = <0x0 0xff020000 0x0 0x1000>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
power-domains = <&zynqmp_firmware PD_I2C_0>; |
|
}; |
|
|
|
i2c1: i2c@ff030000 { |
|
compatible = "cdns,i2c-r1p14"; |
|
status = "disabled"; |
|
interrupt-parent = <&gic>; |
|
interrupts = <0 18 4>; |
|
reg = <0x0 0xff030000 0x0 0x1000>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
power-domains = <&zynqmp_firmware PD_I2C_1>; |
|
}; |
|
|
|
pcie: pcie@fd0e0000 { |
|
compatible = "xlnx,nwl-pcie-2.11"; |
|
status = "disabled"; |
|
#address-cells = <3>; |
|
#size-cells = <2>; |
|
#interrupt-cells = <1>; |
|
msi-controller; |
|
device_type = "pci"; |
|
interrupt-parent = <&gic>; |
|
interrupts = <0 118 4>, |
|
<0 117 4>, |
|
<0 116 4>, |
|
<0 115 4>, /* MSI_1 [63...32] */ |
|
<0 114 4>; /* MSI_0 [31...0] */ |
|
interrupt-names = "misc", "dummy", "intx", |
|
"msi1", "msi0"; |
|
msi-parent = <&pcie>; |
|
reg = <0x0 0xfd0e0000 0x0 0x1000>, |
|
<0x0 0xfd480000 0x0 0x1000>, |
|
<0x80 0x00000000 0x0 0x1000000>; |
|
reg-names = "breg", "pcireg", "cfg"; |
|
ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-prefetchable memory */ |
|
<0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ |
|
bus-range = <0x00 0xff>; |
|
interrupt-map-mask = <0x0 0x0 0x0 0x7>; |
|
interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, |
|
<0x0 0x0 0x0 0x2 &pcie_intc 0x2>, |
|
<0x0 0x0 0x0 0x3 &pcie_intc 0x3>, |
|
<0x0 0x0 0x0 0x4 &pcie_intc 0x4>; |
|
power-domains = <&zynqmp_firmware PD_PCIE>; |
|
pcie_intc: legacy-interrupt-controller { |
|
interrupt-controller; |
|
#address-cells = <0>; |
|
#interrupt-cells = <1>; |
|
}; |
|
}; |
|
|
|
qspi: spi@ff0f0000 { |
|
compatible = "xlnx,zynqmp-qspi-1.0"; |
|
status = "disabled"; |
|
clock-names = "ref_clk", "pclk"; |
|
interrupts = <0 15 4>; |
|
interrupt-parent = <&gic>; |
|
num-cs = <1>; |
|
reg = <0x0 0xff0f0000 0x0 0x1000>, |
|
<0x0 0xc0000000 0x0 0x8000000>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
#stream-id-cells = <1>; |
|
iommus = <&smmu 0x873>; |
|
power-domains = <&zynqmp_firmware PD_QSPI>; |
|
}; |
|
|
|
psgtr: phy@fd400000 { |
|
compatible = "xlnx,zynqmp-psgtr-v1.1"; |
|
status = "disabled"; |
|
reg = <0x0 0xfd400000 0x0 0x40000>, |
|
<0x0 0xfd3d0000 0x0 0x1000>; |
|
reg-names = "serdes", "siou"; |
|
#phy-cells = <4>; |
|
}; |
|
|
|
rtc: rtc@ffa60000 { |
|
compatible = "xlnx,zynqmp-rtc"; |
|
status = "disabled"; |
|
reg = <0x0 0xffa60000 0x0 0x100>; |
|
interrupt-parent = <&gic>; |
|
interrupts = <0 26 4>, <0 27 4>; |
|
interrupt-names = "alarm", "sec"; |
|
calibration = <0x8000>; |
|
}; |
|
|
|
sata: ahci@fd0c0000 { |
|
compatible = "ceva,ahci-1v84"; |
|
status = "disabled"; |
|
reg = <0x0 0xfd0c0000 0x0 0x2000>; |
|
interrupt-parent = <&gic>; |
|
interrupts = <0 133 4>; |
|
power-domains = <&zynqmp_firmware PD_SATA>; |
|
#stream-id-cells = <4>; |
|
iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, |
|
<&smmu 0x4c2>, <&smmu 0x4c3>; |
|
}; |
|
|
|
sdhci0: mmc@ff160000 { |
|
compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; |
|
status = "disabled"; |
|
interrupt-parent = <&gic>; |
|
interrupts = <0 48 4>; |
|
reg = <0x0 0xff160000 0x0 0x1000>; |
|
clock-names = "clk_xin", "clk_ahb"; |
|
#stream-id-cells = <1>; |
|
iommus = <&smmu 0x870>; |
|
#clock-cells = <1>; |
|
clock-output-names = "clk_out_sd0", "clk_in_sd0"; |
|
power-domains = <&zynqmp_firmware PD_SD_0>; |
|
}; |
|
|
|
sdhci1: mmc@ff170000 { |
|
compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; |
|
status = "disabled"; |
|
interrupt-parent = <&gic>; |
|
interrupts = <0 49 4>; |
|
reg = <0x0 0xff170000 0x0 0x1000>; |
|
clock-names = "clk_xin", "clk_ahb"; |
|
#stream-id-cells = <1>; |
|
iommus = <&smmu 0x871>; |
|
#clock-cells = <1>; |
|
clock-output-names = "clk_out_sd1", "clk_in_sd1"; |
|
power-domains = <&zynqmp_firmware PD_SD_1>; |
|
}; |
|
|
|
smmu: iommu@fd800000 { |
|
compatible = "arm,mmu-500"; |
|
reg = <0x0 0xfd800000 0x0 0x20000>; |
|
#iommu-cells = <1>; |
|
status = "disabled"; |
|
#global-interrupts = <1>; |
|
interrupt-parent = <&gic>; |
|
interrupts = <0 155 4>, |
|
<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, |
|
<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, |
|
<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, |
|
<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; |
|
}; |
|
|
|
spi0: spi@ff040000 { |
|
compatible = "cdns,spi-r1p6"; |
|
status = "disabled"; |
|
interrupt-parent = <&gic>; |
|
interrupts = <0 19 4>; |
|
reg = <0x0 0xff040000 0x0 0x1000>; |
|
clock-names = "ref_clk", "pclk"; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
power-domains = <&zynqmp_firmware PD_SPI_0>; |
|
}; |
|
|
|
spi1: spi@ff050000 { |
|
compatible = "cdns,spi-r1p6"; |
|
status = "disabled"; |
|
interrupt-parent = <&gic>; |
|
interrupts = <0 20 4>; |
|
reg = <0x0 0xff050000 0x0 0x1000>; |
|
clock-names = "ref_clk", "pclk"; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
power-domains = <&zynqmp_firmware PD_SPI_1>; |
|
}; |
|
|
|
ttc0: timer@ff110000 { |
|
compatible = "cdns,ttc"; |
|
status = "disabled"; |
|
interrupt-parent = <&gic>; |
|
interrupts = <0 36 4>, <0 37 4>, <0 38 4>; |
|
reg = <0x0 0xff110000 0x0 0x1000>; |
|
timer-width = <32>; |
|
power-domains = <&zynqmp_firmware PD_TTC_0>; |
|
}; |
|
|
|
ttc1: timer@ff120000 { |
|
compatible = "cdns,ttc"; |
|
status = "disabled"; |
|
interrupt-parent = <&gic>; |
|
interrupts = <0 39 4>, <0 40 4>, <0 41 4>; |
|
reg = <0x0 0xff120000 0x0 0x1000>; |
|
timer-width = <32>; |
|
power-domains = <&zynqmp_firmware PD_TTC_1>; |
|
}; |
|
|
|
ttc2: timer@ff130000 { |
|
compatible = "cdns,ttc"; |
|
status = "disabled"; |
|
interrupt-parent = <&gic>; |
|
interrupts = <0 42 4>, <0 43 4>, <0 44 4>; |
|
reg = <0x0 0xff130000 0x0 0x1000>; |
|
timer-width = <32>; |
|
power-domains = <&zynqmp_firmware PD_TTC_2>; |
|
}; |
|
|
|
ttc3: timer@ff140000 { |
|
compatible = "cdns,ttc"; |
|
status = "disabled"; |
|
interrupt-parent = <&gic>; |
|
interrupts = <0 45 4>, <0 46 4>, <0 47 4>; |
|
reg = <0x0 0xff140000 0x0 0x1000>; |
|
timer-width = <32>; |
|
power-domains = <&zynqmp_firmware PD_TTC_3>; |
|
}; |
|
|
|
uart0: serial@ff000000 { |
|
compatible = "cdns,uart-r1p12", "xlnx,xuartps"; |
|
status = "disabled"; |
|
interrupt-parent = <&gic>; |
|
interrupts = <0 21 4>; |
|
reg = <0x0 0xff000000 0x0 0x1000>; |
|
clock-names = "uart_clk", "pclk"; |
|
power-domains = <&zynqmp_firmware PD_UART_0>; |
|
}; |
|
|
|
uart1: serial@ff010000 { |
|
compatible = "cdns,uart-r1p12", "xlnx,xuartps"; |
|
status = "disabled"; |
|
interrupt-parent = <&gic>; |
|
interrupts = <0 22 4>; |
|
reg = <0x0 0xff010000 0x0 0x1000>; |
|
clock-names = "uart_clk", "pclk"; |
|
power-domains = <&zynqmp_firmware PD_UART_1>; |
|
}; |
|
|
|
usb0: usb@fe200000 { |
|
compatible = "snps,dwc3"; |
|
status = "disabled"; |
|
interrupt-parent = <&gic>; |
|
interrupts = <0 65 4>; |
|
reg = <0x0 0xfe200000 0x0 0x40000>; |
|
clock-names = "clk_xin", "clk_ahb"; |
|
power-domains = <&zynqmp_firmware PD_USB_0>; |
|
}; |
|
|
|
usb1: usb@fe300000 { |
|
compatible = "snps,dwc3"; |
|
status = "disabled"; |
|
interrupt-parent = <&gic>; |
|
interrupts = <0 70 4>; |
|
reg = <0x0 0xfe300000 0x0 0x40000>; |
|
clock-names = "clk_xin", "clk_ahb"; |
|
power-domains = <&zynqmp_firmware PD_USB_1>; |
|
}; |
|
|
|
watchdog0: watchdog@fd4d0000 { |
|
compatible = "cdns,wdt-r1p2"; |
|
status = "disabled"; |
|
interrupt-parent = <&gic>; |
|
interrupts = <0 113 1>; |
|
reg = <0x0 0xfd4d0000 0x0 0x1000>; |
|
timeout-sec = <10>; |
|
}; |
|
|
|
lpd_watchdog: watchdog@ff150000 { |
|
compatible = "cdns,wdt-r1p2"; |
|
status = "disabled"; |
|
interrupt-parent = <&gic>; |
|
interrupts = <0 52 1>; |
|
reg = <0x0 0xff150000 0x0 0x1000>; |
|
timeout-sec = <10>; |
|
}; |
|
|
|
zynqmp_dpdma: dma-controller@fd4c0000 { |
|
compatible = "xlnx,zynqmp-dpdma"; |
|
status = "disabled"; |
|
reg = <0x0 0xfd4c0000 0x0 0x1000>; |
|
interrupts = <0 122 4>; |
|
interrupt-parent = <&gic>; |
|
clock-names = "axi_clk"; |
|
#dma-cells = <1>; |
|
}; |
|
|
|
zynqmp_dpsub: display@fd4a0000 { |
|
compatible = "xlnx,zynqmp-dpsub-1.7"; |
|
status = "disabled"; |
|
reg = <0x0 0xfd4a0000 0x0 0x1000>, |
|
<0x0 0xfd4aa000 0x0 0x1000>, |
|
<0x0 0xfd4ab000 0x0 0x1000>, |
|
<0x0 0xfd4ac000 0x0 0x1000>; |
|
reg-names = "dp", "blend", "av_buf", "aud"; |
|
interrupts = <0 119 4>; |
|
interrupt-parent = <&gic>; |
|
clock-names = "dp_apb_clk", "dp_aud_clk", |
|
"dp_vtc_pixel_clk_in"; |
|
power-domains = <&zynqmp_firmware PD_DP>; |
|
resets = <&zynqmp_reset ZYNQMP_RESET_DP>; |
|
dma-names = "vid0", "vid1", "vid2", "gfx0"; |
|
dmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>, |
|
<&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>, |
|
<&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>, |
|
<&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>; |
|
}; |
|
}; |
|
};
|
|
|