mirror of https://github.com/Qortal/Brooklyn
You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
123 lines
4.2 KiB
123 lines
4.2 KiB
// SPDX-License-Identifier: GPL-2.0 |
|
/* |
|
* Device Tree Source for AM6 SoC Family |
|
* |
|
* Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ |
|
*/ |
|
|
|
#include <dt-bindings/gpio/gpio.h> |
|
#include <dt-bindings/interrupt-controller/irq.h> |
|
#include <dt-bindings/interrupt-controller/arm-gic.h> |
|
#include <dt-bindings/pinctrl/k3.h> |
|
#include <dt-bindings/soc/ti,sci_pm_domain.h> |
|
|
|
/ { |
|
model = "Texas Instruments K3 AM654 SoC"; |
|
compatible = "ti,am654"; |
|
interrupt-parent = <&gic500>; |
|
#address-cells = <2>; |
|
#size-cells = <2>; |
|
|
|
aliases { |
|
serial0 = &wkup_uart0; |
|
serial1 = &mcu_uart0; |
|
serial2 = &main_uart0; |
|
serial3 = &main_uart1; |
|
serial4 = &main_uart2; |
|
i2c0 = &wkup_i2c0; |
|
i2c1 = &mcu_i2c0; |
|
i2c2 = &main_i2c0; |
|
i2c3 = &main_i2c1; |
|
i2c4 = &main_i2c2; |
|
i2c5 = &main_i2c3; |
|
ethernet0 = &cpsw_port1; |
|
}; |
|
|
|
chosen { }; |
|
|
|
firmware { |
|
optee { |
|
compatible = "linaro,optee-tz"; |
|
method = "smc"; |
|
}; |
|
|
|
psci: psci { |
|
compatible = "arm,psci-1.0"; |
|
method = "smc"; |
|
}; |
|
}; |
|
|
|
a53_timer0: timer-cl0-cpu0 { |
|
compatible = "arm,armv8-timer"; |
|
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ |
|
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ |
|
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ |
|
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ |
|
}; |
|
|
|
pmu: pmu { |
|
compatible = "arm,cortex-a53-pmu"; |
|
/* Recommendation from GIC500 TRM Table A.3 */ |
|
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; |
|
}; |
|
|
|
cbass_main: bus@100000 { |
|
compatible = "simple-bus"; |
|
#address-cells = <2>; |
|
#size-cells = <2>; |
|
ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ |
|
<0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ |
|
<0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */ |
|
<0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */ |
|
<0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */ |
|
<0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* MSMC SRAM */ |
|
<0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */ |
|
/* MCUSS Range */ |
|
<0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, |
|
<0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, |
|
<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ |
|
<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, |
|
<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, |
|
<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>, |
|
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, |
|
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, |
|
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, |
|
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, |
|
<0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>, |
|
<0x00 0x70000000 0x00 0x70000000 0x00 0x200000>, |
|
<0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>, |
|
<0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>; |
|
|
|
cbass_mcu: bus@28380000 { |
|
compatible = "simple-bus"; |
|
#address-cells = <2>; |
|
#size-cells = <2>; |
|
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/ |
|
<0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>, /* First peripheral window */ |
|
<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ |
|
<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ |
|
<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ |
|
<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>, /* MCU SRAM */ |
|
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP */ |
|
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */ |
|
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */ |
|
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI space 1 */ |
|
<0x00 0x50000000 0x00 0x50000000 0x00 0x8000000>, /* FSS OSPI0 data region 1 */ |
|
<0x05 0x00000000 0x05 0x00000000 0x01 0x0000000>, /* FSS OSPI0 data region 3*/ |
|
<0x07 0x00000000 0x07 0x00000000 0x01 0x0000000>; /* FSS OSPI1 data region 3*/ |
|
|
|
cbass_wakeup: bus@42040000 { |
|
compatible = "simple-bus"; |
|
#address-cells = <1>; |
|
#size-cells = <1>; |
|
/* WKUP Basic peripherals */ |
|
ranges = <0x42040000 0x00 0x42040000 0x03ac2400>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
/* Now include the peripherals for each bus segments */ |
|
#include "k3-am65-main.dtsi" |
|
#include "k3-am65-mcu.dtsi" |
|
#include "k3-am65-wakeup.dtsi"
|
|
|