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589 lines
11 KiB
589 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Unisoc SC9863A SoC DTS file |
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* |
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* Copyright (C) 2019, Unisoc Inc. |
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*/ |
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#include <dt-bindings/clock/sprd,sc9863a-clk.h> |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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#include "sharkl3.dtsi" |
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/ { |
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cpus { |
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#address-cells = <2>; |
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#size-cells = <0>; |
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cpu-map { |
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cluster0 { |
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core0 { |
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cpu = <&CPU0>; |
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}; |
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core1 { |
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cpu = <&CPU1>; |
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}; |
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core2 { |
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cpu = <&CPU2>; |
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}; |
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core3 { |
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cpu = <&CPU3>; |
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}; |
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core4 { |
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cpu = <&CPU4>; |
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}; |
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core5 { |
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cpu = <&CPU5>; |
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}; |
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core6 { |
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cpu = <&CPU6>; |
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}; |
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core7 { |
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cpu = <&CPU7>; |
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}; |
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}; |
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}; |
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CPU0: cpu@0 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a55"; |
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reg = <0x0 0x0>; |
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enable-method = "psci"; |
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cpu-idle-states = <&CORE_PD>; |
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}; |
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CPU1: cpu@100 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a55"; |
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reg = <0x0 0x100>; |
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enable-method = "psci"; |
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cpu-idle-states = <&CORE_PD>; |
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}; |
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CPU2: cpu@200 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a55"; |
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reg = <0x0 0x200>; |
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enable-method = "psci"; |
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cpu-idle-states = <&CORE_PD>; |
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}; |
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CPU3: cpu@300 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a55"; |
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reg = <0x0 0x300>; |
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enable-method = "psci"; |
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cpu-idle-states = <&CORE_PD>; |
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}; |
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CPU4: cpu@400 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a55"; |
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reg = <0x0 0x400>; |
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enable-method = "psci"; |
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cpu-idle-states = <&CORE_PD>; |
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}; |
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CPU5: cpu@500 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a55"; |
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reg = <0x0 0x500>; |
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enable-method = "psci"; |
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cpu-idle-states = <&CORE_PD>; |
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}; |
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CPU6: cpu@600 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a55"; |
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reg = <0x0 0x600>; |
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enable-method = "psci"; |
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cpu-idle-states = <&CORE_PD>; |
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}; |
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CPU7: cpu@700 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a55"; |
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reg = <0x0 0x700>; |
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enable-method = "psci"; |
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cpu-idle-states = <&CORE_PD>; |
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}; |
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}; |
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idle-states { |
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entry-method = "psci"; |
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CORE_PD: core-pd { |
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compatible = "arm,idle-state"; |
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entry-latency-us = <4000>; |
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exit-latency-us = <4000>; |
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min-residency-us = <10000>; |
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local-timer-stop; |
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arm,psci-suspend-param = <0x00010000>; |
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}; |
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}; |
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psci { |
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compatible = "arm,psci-0.2"; |
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method = "smc"; |
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}; |
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timer { |
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compatible = "arm,armv8-timer"; |
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, /* Physical Secure PPI */ |
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<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, /* Physical Non-Secure PPI */ |
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<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, /* Virtual PPI */ |
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<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; /* Hipervisor PPI */ |
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}; |
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pmu { |
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compatible = "arm,armv8-pmuv3"; |
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interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; |
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}; |
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soc { |
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gic: interrupt-controller@14000000 { |
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compatible = "arm,gic-v3"; |
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#interrupt-cells = <3>; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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ranges; |
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redistributor-stride = <0x0 0x20000>; /* 128KB stride */ |
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#redistributor-regions = <1>; |
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interrupt-controller; |
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reg = <0x0 0x14000000 0 0x20000>, /* GICD */ |
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<0x0 0x14040000 0 0x100000>; /* GICR */ |
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
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}; |
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ap_clk: clock-controller@21500000 { |
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compatible = "sprd,sc9863a-ap-clk"; |
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reg = <0 0x21500000 0 0x1000>; |
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clocks = <&ext_32k>, <&ext_26m>; |
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clock-names = "ext-32k", "ext-26m"; |
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#clock-cells = <1>; |
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}; |
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aon_clk: clock-controller@402d0000 { |
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compatible = "sprd,sc9863a-aon-clk"; |
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reg = <0 0x402d0000 0 0x1000>; |
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clocks = <&ext_26m>, <&rco_100m>, |
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<&ext_32k>, <&ext_4m>; |
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clock-names = "ext-26m", "rco-100m", |
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"ext-32k", "ext-4m"; |
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#clock-cells = <1>; |
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}; |
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mm_clk: clock-controller@60900000 { |
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compatible = "sprd,sc9863a-mm-clk"; |
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reg = <0 0x60900000 0 0x1000>; |
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#clock-cells = <1>; |
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}; |
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funnel@10001000 { |
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compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; |
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reg = <0 0x10001000 0 0x1000>; |
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clocks = <&ext_26m>; |
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clock-names = "apb_pclk"; |
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out-ports { |
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port { |
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funnel_soc_out_port: endpoint { |
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remote-endpoint = <&etb_in>; |
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}; |
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}; |
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}; |
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in-ports { |
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port { |
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funnel_soc_in_port: endpoint { |
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remote-endpoint = |
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<&funnel_ca55_out_port>; |
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}; |
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}; |
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}; |
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}; |
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etb@10003000 { |
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compatible = "arm,coresight-tmc", "arm,primecell"; |
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reg = <0 0x10003000 0 0x1000>; |
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clocks = <&ext_26m>; |
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clock-names = "apb_pclk"; |
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in-ports { |
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port { |
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etb_in: endpoint { |
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remote-endpoint = |
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<&funnel_soc_out_port>; |
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}; |
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}; |
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}; |
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}; |
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funnel@12001000 { |
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compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; |
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reg = <0 0x12001000 0 0x1000>; |
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clocks = <&ext_26m>; |
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clock-names = "apb_pclk"; |
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out-ports { |
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port { |
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funnel_little_out_port: endpoint { |
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remote-endpoint = |
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<&etf_little_in>; |
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}; |
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}; |
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}; |
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in-ports { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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port@0 { |
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reg = <0>; |
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funnel_little_in_port0: endpoint { |
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remote-endpoint = <&etm0_out>; |
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}; |
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}; |
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port@1 { |
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reg = <1>; |
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funnel_little_in_port1: endpoint { |
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remote-endpoint = <&etm1_out>; |
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}; |
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}; |
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port@2 { |
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reg = <2>; |
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funnel_little_in_port2: endpoint { |
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remote-endpoint = <&etm2_out>; |
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}; |
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}; |
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port@3 { |
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reg = <3>; |
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funnel_little_in_port3: endpoint { |
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remote-endpoint = <&etm3_out>; |
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}; |
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}; |
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}; |
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}; |
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etf@12002000 { |
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compatible = "arm,coresight-tmc", "arm,primecell"; |
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reg = <0 0x12002000 0 0x1000>; |
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clocks = <&ext_26m>; |
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clock-names = "apb_pclk"; |
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out-ports { |
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port { |
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etf_little_out: endpoint { |
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remote-endpoint = |
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<&funnel_ca55_in_port0>; |
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}; |
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}; |
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}; |
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in-port { |
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port { |
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etf_little_in: endpoint { |
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remote-endpoint = |
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<&funnel_little_out_port>; |
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}; |
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}; |
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}; |
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}; |
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etf@12003000 { |
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compatible = "arm,coresight-tmc", "arm,primecell"; |
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reg = <0 0x12003000 0 0x1000>; |
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clocks = <&ext_26m>; |
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clock-names = "apb_pclk"; |
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out-ports { |
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port { |
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etf_big_out: endpoint { |
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remote-endpoint = |
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<&funnel_ca55_in_port1>; |
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}; |
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}; |
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}; |
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in-ports { |
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port { |
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etf_big_in: endpoint { |
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remote-endpoint = |
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<&funnel_big_out_port>; |
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}; |
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}; |
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}; |
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}; |
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funnel@12004000 { |
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compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; |
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reg = <0 0x12004000 0 0x1000>; |
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clocks = <&ext_26m>; |
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clock-names = "apb_pclk"; |
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out-ports { |
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port { |
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funnel_ca55_out_port: endpoint { |
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remote-endpoint = |
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<&funnel_soc_in_port>; |
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}; |
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}; |
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}; |
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in-ports { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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port@0 { |
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reg = <0>; |
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funnel_ca55_in_port0: endpoint { |
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remote-endpoint = |
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<&etf_little_out>; |
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}; |
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}; |
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port@1 { |
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reg = <1>; |
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funnel_ca55_in_port1: endpoint { |
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remote-endpoint = |
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<&etf_big_out>; |
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}; |
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}; |
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}; |
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}; |
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funnel@12005000 { |
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compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; |
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reg = <0 0x12005000 0 0x1000>; |
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clocks = <&ext_26m>; |
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clock-names = "apb_pclk"; |
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out-ports { |
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port { |
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funnel_big_out_port: endpoint { |
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remote-endpoint = |
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<&etf_big_in>; |
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}; |
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}; |
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}; |
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in-ports { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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port@0 { |
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reg = <0>; |
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funnel_big_in_port0: endpoint { |
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remote-endpoint = <&etm4_out>; |
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}; |
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}; |
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port@1 { |
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reg = <1>; |
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funnel_big_in_port1: endpoint { |
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remote-endpoint = <&etm5_out>; |
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}; |
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}; |
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port@2 { |
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reg = <2>; |
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funnel_big_in_port2: endpoint { |
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remote-endpoint = <&etm6_out>; |
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}; |
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}; |
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port@3 { |
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reg = <3>; |
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funnel_big_in_port3: endpoint { |
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remote-endpoint = <&etm7_out>; |
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}; |
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}; |
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}; |
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}; |
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etm@13040000 { |
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compatible = "arm,coresight-etm4x", "arm,primecell"; |
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reg = <0 0x13040000 0 0x1000>; |
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cpu = <&CPU0>; |
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clocks = <&ext_26m>; |
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clock-names = "apb_pclk"; |
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out-ports { |
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port { |
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etm0_out: endpoint { |
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remote-endpoint = |
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<&funnel_little_in_port0>; |
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}; |
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}; |
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}; |
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}; |
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etm@13140000 { |
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compatible = "arm,coresight-etm4x", "arm,primecell"; |
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reg = <0 0x13140000 0 0x1000>; |
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cpu = <&CPU1>; |
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clocks = <&ext_26m>; |
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clock-names = "apb_pclk"; |
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out-ports { |
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port { |
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etm1_out: endpoint { |
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remote-endpoint = |
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<&funnel_little_in_port1>; |
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}; |
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}; |
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}; |
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}; |
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etm@13240000 { |
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compatible = "arm,coresight-etm4x", "arm,primecell"; |
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reg = <0 0x13240000 0 0x1000>; |
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cpu = <&CPU2>; |
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clocks = <&ext_26m>; |
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clock-names = "apb_pclk"; |
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out-ports { |
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port { |
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etm2_out: endpoint { |
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remote-endpoint = |
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<&funnel_little_in_port2>; |
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}; |
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}; |
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}; |
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}; |
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etm@13340000 { |
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compatible = "arm,coresight-etm4x", "arm,primecell"; |
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reg = <0 0x13340000 0 0x1000>; |
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cpu = <&CPU3>; |
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clocks = <&ext_26m>; |
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clock-names = "apb_pclk"; |
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out-ports { |
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port { |
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etm3_out: endpoint { |
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remote-endpoint = |
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<&funnel_little_in_port3>; |
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}; |
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}; |
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}; |
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}; |
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etm@13440000 { |
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compatible = "arm,coresight-etm4x", "arm,primecell"; |
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reg = <0 0x13440000 0 0x1000>; |
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cpu = <&CPU4>; |
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clocks = <&ext_26m>; |
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clock-names = "apb_pclk"; |
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out-ports { |
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port { |
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etm4_out: endpoint { |
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remote-endpoint = |
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<&funnel_big_in_port0>; |
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}; |
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}; |
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}; |
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}; |
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etm@13540000 { |
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compatible = "arm,coresight-etm4x", "arm,primecell"; |
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reg = <0 0x13540000 0 0x1000>; |
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cpu = <&CPU5>; |
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clocks = <&ext_26m>; |
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clock-names = "apb_pclk"; |
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out-ports { |
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port { |
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etm5_out: endpoint { |
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remote-endpoint = |
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<&funnel_big_in_port1>; |
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}; |
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}; |
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}; |
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}; |
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etm@13640000 { |
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compatible = "arm,coresight-etm4x", "arm,primecell"; |
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reg = <0 0x13640000 0 0x1000>; |
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cpu = <&CPU6>; |
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clocks = <&ext_26m>; |
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clock-names = "apb_pclk"; |
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out-ports { |
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port { |
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etm6_out: endpoint { |
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remote-endpoint = |
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<&funnel_big_in_port2>; |
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}; |
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}; |
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}; |
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}; |
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etm@13740000 { |
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compatible = "arm,coresight-etm4x", "arm,primecell"; |
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reg = <0 0x13740000 0 0x1000>; |
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cpu = <&CPU7>; |
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clocks = <&ext_26m>; |
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clock-names = "apb_pclk"; |
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out-ports { |
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port { |
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etm7_out: endpoint { |
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remote-endpoint = |
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<&funnel_big_in_port3>; |
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}; |
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}; |
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}; |
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}; |
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ap-ahb { |
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compatible = "simple-bus"; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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ranges; |
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sdio0: sdio@20300000 { |
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compatible = "sprd,sdhci-r11"; |
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reg = <0 0x20300000 0 0x1000>; |
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; |
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clock-names = "sdio", "enable"; |
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clocks = <&aon_clk CLK_SDIO0_2X>, |
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<&apahb_gate CLK_SDIO0_EB>; |
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assigned-clocks = <&aon_clk CLK_SDIO0_2X>; |
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assigned-clock-parents = <&rpll CLK_RPLL_390M>; |
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bus-width = <4>; |
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no-sdio; |
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no-mmc; |
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}; |
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sdio3: sdio@20600000 { |
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compatible = "sprd,sdhci-r11"; |
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reg = <0 0x20600000 0 0x1000>; |
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interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; |
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clock-names = "sdio", "enable"; |
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clocks = <&aon_clk CLK_EMMC_2X>, |
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<&apahb_gate CLK_EMMC_EB>; |
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assigned-clocks = <&aon_clk CLK_EMMC_2X>; |
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assigned-clock-parents = <&rpll CLK_RPLL_390M>; |
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bus-width = <8>; |
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non-removable; |
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no-sdio; |
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no-sd; |
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cap-mmc-hw-reset; |
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}; |
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}; |
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}; |
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};
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