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690 lines
14 KiB
690 lines
14 KiB
// SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
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/* |
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* Google Gru-scarlet board device tree source |
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* |
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* Copyright 2018 Google, Inc |
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*/ |
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#include "rk3399-gru.dtsi" |
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/{ |
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/* Power tree */ |
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/* ppvar_sys children, sorted by name */ |
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pp1250_s3: pp1250-s3 { |
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compatible = "regulator-fixed"; |
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regulator-name = "pp1250_s3"; |
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/* EC turns on w/ pp1250_s3_en; always on for AP */ |
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regulator-always-on; |
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regulator-boot-on; |
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regulator-min-microvolt = <1250000>; |
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regulator-max-microvolt = <1250000>; |
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vin-supply = <&ppvar_sys>; |
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}; |
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pp1250_cam: pp1250-dvdd { |
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compatible = "regulator-fixed"; |
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regulator-name = "pp1250_dvdd"; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pp1250_cam_en>; |
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enable-active-high; |
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gpio = <&gpio2 4 GPIO_ACTIVE_HIGH>; |
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/* 740us delay from gpio output high to pp1250 stable, |
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* rounding up to 1ms for safety. |
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*/ |
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startup-delay-us = <1000>; |
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vin-supply = <&pp1250_s3>; |
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}; |
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pp900_s0: pp900-s0 { |
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compatible = "regulator-fixed"; |
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regulator-name = "pp900_s0"; |
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/* EC turns on w/ pp900_s0_en; always on for AP */ |
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regulator-always-on; |
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regulator-boot-on; |
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regulator-min-microvolt = <900000>; |
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regulator-max-microvolt = <900000>; |
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vin-supply = <&ppvar_sys>; |
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}; |
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ppvarn_lcd: ppvarn-lcd { |
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compatible = "regulator-fixed"; |
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regulator-name = "ppvarn_lcd"; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&ppvarn_lcd_en>; |
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enable-active-high; |
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gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>; |
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vin-supply = <&ppvar_sys>; |
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}; |
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ppvarp_lcd: ppvarp-lcd { |
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compatible = "regulator-fixed"; |
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regulator-name = "ppvarp_lcd"; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&ppvarp_lcd_en>; |
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enable-active-high; |
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gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; |
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vin-supply = <&ppvar_sys>; |
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}; |
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/* pp1800 children, sorted by name */ |
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pp900_s3: pp900-s3 { |
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compatible = "regulator-fixed"; |
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regulator-name = "pp900_s3"; |
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/* EC turns on w/ pp900_s3_en; always on for AP */ |
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regulator-always-on; |
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regulator-boot-on; |
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regulator-min-microvolt = <900000>; |
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regulator-max-microvolt = <900000>; |
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vin-supply = <&pp1800>; |
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}; |
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/* EC turns on pp1800_s3_en */ |
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pp1800_s3: pp1800 { |
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}; |
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/* pp3300 children, sorted by name */ |
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pp2800_cam: pp2800-avdd { |
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compatible = "regulator-fixed"; |
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regulator-name = "pp2800_avdd"; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pp2800_cam_en>; |
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enable-active-high; |
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gpio = <&gpio2 24 GPIO_ACTIVE_HIGH>; |
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startup-delay-us = <100>; |
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vin-supply = <&pp3300>; |
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}; |
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/* EC turns on pp3300_s0_en */ |
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pp3300_s0: pp3300 { |
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}; |
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/* EC turns on pp3300_s3_en */ |
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pp3300_s3: pp3300 { |
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}; |
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/* |
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* See b/66922012 |
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* |
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* This is a hack to make sure the Bluetooth part of the QCA6174A |
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* is reset at boot by toggling BT_EN. At boot BT_EN is first set |
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* to low when the bt_3v3 regulator is registered (in disabled |
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* state). The fake regulator is configured as a supply of the |
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* wlan_3v3 regulator below. When wlan_3v3 is enabled early in |
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* the boot process it also enables its supply regulator bt_3v3, |
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* which changes BT_EN to high. |
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*/ |
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bt_3v3: bt-3v3 { |
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compatible = "regulator-fixed"; |
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regulator-name = "bt_3v3"; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&bt_en_1v8_l>; |
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enable-active-high; |
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gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>; |
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vin-supply = <&pp3300_s3>; |
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}; |
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wlan_3v3: wlan-3v3 { |
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compatible = "regulator-fixed"; |
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regulator-name = "wlan_3v3"; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&wlan_pd_1v8_l>; |
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/* |
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* The WL_EN pin is driven low when the regulator is |
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* registered, and transitions to high when the PCIe bus |
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* is powered up. |
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*/ |
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enable-active-high; |
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gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; |
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/* |
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* Require minimum 10ms from power-on (e.g., PD#) to init PCIe. |
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* TODO (b/64444991): how long to assert PD#? |
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*/ |
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regulator-enable-ramp-delay = <10000>; |
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/* See bt_3v3 hack above */ |
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vin-supply = <&bt_3v3>; |
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}; |
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backlight: backlight { |
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compatible = "pwm-backlight"; |
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enable-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&bl_en>; |
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pwms = <&pwm1 0 1000000 0>; |
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pwm-delay-us = <10000>; |
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}; |
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dmic: dmic { |
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compatible = "dmic-codec"; |
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dmicen-gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&dmic_en>; |
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wakeup-delay-ms = <250>; |
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}; |
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gpio_keys: gpio-keys { |
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compatible = "gpio-keys"; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pen_eject_odl>; |
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pen-insert { |
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label = "Pen Insert"; |
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/* Insert = low, eject = high */ |
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gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; |
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linux,code = <SW_PEN_INSERTED>; |
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linux,input-type = <EV_SW>; |
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wakeup-source; |
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}; |
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}; |
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}; |
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/* pp900_s0 aliases */ |
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pp900_ddrpll_ap: &pp900_s0 { |
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}; |
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pp900_pcie: &pp900_s0 { |
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}; |
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pp900_usb: &pp900_s0 { |
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}; |
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/* pp900_s3 aliases */ |
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pp900_emmcpll: &pp900_s3 { |
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}; |
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/* EC turns on; alias for pp1800_s0 */ |
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pp1800_pcie: &pp1800_s0 { |
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}; |
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/* On scarlet PPVAR(big_cpu, lit_cpu, gpu) need to adjust voltage ranges */ |
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&ppvar_bigcpu { |
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ctrl-voltage-range = <800074 1299226>; |
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regulator-min-microvolt = <800074>; |
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regulator-max-microvolt = <1299226>; |
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}; |
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&ppvar_bigcpu_pwm { |
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/* On scarlet ppvar big cpu use pwm3 */ |
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pwms = <&pwm3 0 3337 0>; |
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regulator-min-microvolt = <800074>; |
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regulator-max-microvolt = <1299226>; |
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}; |
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&ppvar_litcpu { |
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ctrl-voltage-range = <802122 1199620>; |
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regulator-min-microvolt = <802122>; |
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regulator-max-microvolt = <1199620>; |
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}; |
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&ppvar_litcpu_pwm { |
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regulator-min-microvolt = <802122>; |
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regulator-max-microvolt = <1199620>; |
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}; |
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&ppvar_gpu { |
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ctrl-voltage-range = <799600 1099600>; |
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regulator-min-microvolt = <799600>; |
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regulator-max-microvolt = <1099600>; |
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}; |
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&ppvar_gpu_pwm { |
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regulator-min-microvolt = <799600>; |
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regulator-max-microvolt = <1099600>; |
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}; |
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&ppvar_sd_card_io { |
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states = <1800000 0x0 3300000 0x1>; |
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regulator-max-microvolt = <3300000>; |
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}; |
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&pp3000_sd_slot { |
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vin-supply = <&pp3300>; |
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}; |
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ap_i2c_dig: &i2c2 { |
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status = "okay"; |
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clock-frequency = <400000>; |
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/* These are relatively safe rise/fall times. */ |
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i2c-scl-falling-time-ns = <50>; |
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i2c-scl-rising-time-ns = <300>; |
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digitizer: digitizer@9 { |
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compatible = "hid-over-i2c"; |
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reg = <0x9>; |
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interrupt-parent = <&gpio1>; |
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interrupts = <0 IRQ_TYPE_LEVEL_LOW>; |
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hid-descr-addr = <0x1>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pen_int_odl &pen_reset_l>; |
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}; |
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}; |
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&ap_i2c_ts { |
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touchscreen: touchscreen@10 { |
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compatible = "elan,ekth3500"; |
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reg = <0x10>; |
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interrupt-parent = <&gpio1>; |
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interrupts = <4 IRQ_TYPE_LEVEL_LOW>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&touch_int_l &touch_reset_l>; |
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reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; |
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}; |
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}; |
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camera: &i2c7 { |
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status = "okay"; |
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clock-frequency = <400000>; |
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/* These are relatively safe rise/fall times; TODO: measure */ |
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i2c-scl-falling-time-ns = <50>; |
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i2c-scl-rising-time-ns = <300>; |
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/* 24M mclk is shared between world and user cameras */ |
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pinctrl-0 = <&i2c7_xfer &test_clkout1>; |
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/* Rear-facing camera */ |
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wcam: camera@36 { |
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compatible = "ovti,ov5695"; |
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reg = <0x36>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&wcam_rst>; |
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clocks = <&cru SCLK_TESTCLKOUT1>; |
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clock-names = "xvclk"; |
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avdd-supply = <&pp2800_cam>; |
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dvdd-supply = <&pp1250_cam>; |
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dovdd-supply = <&pp1800_s0>; |
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reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; |
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port { |
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wcam_out: endpoint { |
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remote-endpoint = <&mipi_in_wcam>; |
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data-lanes = <1 2>; |
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}; |
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}; |
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}; |
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/* Front-facing camera */ |
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ucam: camera@3c { |
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compatible = "ovti,ov2685"; |
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reg = <0x3c>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&ucam_rst>; |
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clocks = <&cru SCLK_TESTCLKOUT1>; |
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clock-names = "xvclk"; |
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avdd-supply = <&pp2800_cam>; |
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dovdd-supply = <&pp1800_s0>; |
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dvdd-supply = <&pp1800_s0>; |
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reset-gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; |
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port { |
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ucam_out: endpoint { |
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remote-endpoint = <&mipi_in_ucam>; |
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data-lanes = <1>; |
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}; |
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}; |
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}; |
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}; |
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&cdn_dp { |
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extcon = <&usbc_extcon0>; |
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phys = <&tcphy0_dp>; |
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}; |
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&cpu_alert0 { |
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temperature = <66000>; |
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}; |
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&cpu_alert1 { |
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temperature = <71000>; |
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}; |
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&cros_ec { |
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interrupt-parent = <&gpio1>; |
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interrupts = <18 IRQ_TYPE_LEVEL_LOW>; |
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}; |
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&cru { |
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assigned-clocks = |
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<&cru PLL_GPLL>, <&cru PLL_CPLL>, |
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<&cru PLL_NPLL>, |
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<&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, |
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<&cru PCLK_PERIHP>, |
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<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, |
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<&cru PCLK_PERILP0>, <&cru ACLK_CCI>, |
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<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, |
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<&cru ACLK_VIO>, |
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<&cru ACLK_GIC_PRE>, |
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<&cru PCLK_DDR>, |
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<&cru ACLK_HDCP>; |
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assigned-clock-rates = |
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<600000000>, <1600000000>, |
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<1000000000>, |
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<150000000>, <75000000>, |
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<37500000>, |
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<100000000>, <100000000>, |
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<50000000>, <800000000>, |
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<100000000>, <50000000>, |
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<400000000>, |
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<200000000>, |
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<200000000>, |
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<400000000>; |
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}; |
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&i2c_tunnel { |
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google,remote-bus = <0>; |
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}; |
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&io_domains { |
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bt656-supply = <&pp1800_s0>; /* APIO2_VDD; 2a 2b */ |
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audio-supply = <&pp1800_s0>; /* APIO5_VDD; 3d 4a */ |
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gpio1830-supply = <&pp1800_s0>; /* APIO4_VDD; 4c 4d */ |
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}; |
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&isp0 { |
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status = "okay"; |
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ports { |
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port@0 { |
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mipi_in_wcam: endpoint@0 { |
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reg = <0>; |
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remote-endpoint = <&wcam_out>; |
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data-lanes = <1 2>; |
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}; |
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mipi_in_ucam: endpoint@1 { |
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reg = <1>; |
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remote-endpoint = <&ucam_out>; |
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data-lanes = <1>; |
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}; |
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}; |
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}; |
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}; |
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&isp0_mmu { |
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status = "okay"; |
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}; |
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&max98357a { |
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sdmode-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; |
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}; |
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&mipi_dphy_rx0 { |
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status = "okay"; |
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}; |
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&mipi_dsi { |
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status = "okay"; |
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clock-master; |
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ports { |
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mipi_out: port@1 { |
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reg = <1>; |
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mipi_out_panel: endpoint { |
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remote-endpoint = <&mipi_in_panel>; |
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}; |
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}; |
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}; |
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mipi_panel: panel@0 { |
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/* 2 different panels are used, compatibles are in dts files */ |
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reg = <0>; |
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backlight = <&backlight>; |
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enable-gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&display_rst_l>; |
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ports { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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port@0 { |
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reg = <0>; |
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mipi_in_panel: endpoint { |
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remote-endpoint = <&mipi_out_panel>; |
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}; |
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}; |
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port@1 { |
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reg = <1>; |
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mipi1_in_panel: endpoint@1 { |
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remote-endpoint = <&mipi1_out_panel>; |
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}; |
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}; |
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}; |
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}; |
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}; |
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&mipi_dsi1 { |
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status = "okay"; |
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ports { |
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mipi1_out: port@1 { |
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reg = <1>; |
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mipi1_out_panel: endpoint { |
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remote-endpoint = <&mipi1_in_panel>; |
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}; |
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}; |
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}; |
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}; |
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&pcie0 { |
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ep-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; |
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/* PERST# asserted in S3 */ |
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pcie-reset-suspend = <1>; |
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vpcie3v3-supply = <&wlan_3v3>; |
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vpcie1v8-supply = <&pp1800_pcie>; |
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}; |
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&sdmmc { |
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cd-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; |
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}; |
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&sound { |
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rockchip,codec = <&max98357a &dmic &codec &cdn_dp>; |
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}; |
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&spi2 { |
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status = "okay"; |
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cr50@0 { |
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compatible = "google,cr50"; |
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reg = <0>; |
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interrupt-parent = <&gpio1>; |
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interrupts = <17 IRQ_TYPE_EDGE_RISING>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&h1_int_od_l>; |
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spi-max-frequency = <800000>; |
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}; |
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}; |
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&usb_host0_ohci { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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qca_bt: bluetooth@1 { |
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compatible = "usbcf3,e300", "usb4ca,301a"; |
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reg = <1>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&bt_host_wake_l>; |
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interrupt-parent = <&gpio1>; |
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interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; |
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interrupt-names = "wakeup"; |
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}; |
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}; |
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|
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/* PINCTRL OVERRIDES */ |
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&ec_ap_int_l { |
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rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; |
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}; |
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&ap_fw_wp { |
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rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; |
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}; |
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&bl_en { |
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rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; |
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}; |
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&bt_host_wake_l { |
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rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; |
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}; |
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&ec_ap_int_l { |
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rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; |
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}; |
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&headset_int_l { |
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rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; |
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}; |
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&i2s0_8ch_bus { |
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rockchip,pins = |
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<3 RK_PD0 1 &pcfg_pull_none_6ma>, |
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<3 RK_PD1 1 &pcfg_pull_none_6ma>, |
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<3 RK_PD2 1 &pcfg_pull_none_6ma>, |
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<3 RK_PD3 1 &pcfg_pull_none_6ma>, |
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<3 RK_PD7 1 &pcfg_pull_none_6ma>, |
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<4 RK_PA0 1 &pcfg_pull_none_6ma>; |
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}; |
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/* there is no external pull up, so need to set this pin pull up */ |
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&sdmmc_cd_pin { |
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rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; |
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}; |
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&sd_pwr_1800_sel { |
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rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; |
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}; |
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&sdmode_en { |
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rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>; |
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}; |
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&touch_reset_l { |
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rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; |
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}; |
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|
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&touch_int_l { |
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rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; |
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}; |
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|
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&pinctrl { |
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pinctrl-0 = < |
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&ap_pwroff /* AP will auto-assert this when in S3 */ |
|
&clk_32k /* This pin is always 32k on gru boards */ |
|
&wlan_rf_kill_1v8_l |
|
>; |
|
|
|
pcfg_pull_none_6ma: pcfg-pull-none-6ma { |
|
bias-disable; |
|
drive-strength = <6>; |
|
}; |
|
|
|
camera { |
|
pp1250_cam_en: pp1250-dvdd { |
|
rockchip,pins = <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; |
|
}; |
|
|
|
pp2800_cam_en: pp2800-avdd { |
|
rockchip,pins = <2 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; |
|
}; |
|
|
|
ucam_rst: ucam_rst { |
|
rockchip,pins = <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; |
|
}; |
|
|
|
wcam_rst: wcam_rst { |
|
rockchip,pins = <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; |
|
}; |
|
}; |
|
|
|
digitizer { |
|
pen_int_odl: pen-int-odl { |
|
rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; |
|
}; |
|
|
|
pen_reset_l: pen-reset-l { |
|
rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; |
|
}; |
|
}; |
|
|
|
discrete-regulators { |
|
display_rst_l: display-rst-l { |
|
rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_down>; |
|
}; |
|
|
|
ppvarp_lcd_en: ppvarp-lcd-en { |
|
rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; |
|
}; |
|
|
|
ppvarn_lcd_en: ppvarn-lcd-en { |
|
rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; |
|
}; |
|
}; |
|
|
|
dmic { |
|
dmic_en: dmic-en { |
|
rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; |
|
}; |
|
}; |
|
|
|
pen { |
|
pen_eject_odl: pen-eject-odl { |
|
rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; |
|
}; |
|
}; |
|
|
|
tpm { |
|
h1_int_od_l: h1-int-od-l { |
|
rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; |
|
}; |
|
}; |
|
}; |
|
|
|
&wifi { |
|
bt_en_1v8_l: bt-en-1v8-l { |
|
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; |
|
}; |
|
|
|
wlan_pd_1v8_l: wlan-pd-1v8-l { |
|
rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; |
|
}; |
|
|
|
/* Default pull-up, but just to be clear */ |
|
wlan_rf_kill_1v8_l: wlan-rf-kill-1v8-l { |
|
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; |
|
}; |
|
|
|
wifi_perst_l: wifi-perst-l { |
|
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; |
|
}; |
|
|
|
wlan_host_wake_l: wlan-host-wake-l { |
|
rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; |
|
}; |
|
};
|
|
|