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282 lines
4.7 KiB
282 lines
4.7 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Device Tree Source for the V3H Starter Kit board |
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* |
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* Copyright (C) 2018 Renesas Electronics Corp. |
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* Copyright (C) 2018 Cogent Embedded, Inc. |
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*/ |
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/dts-v1/; |
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#include "r8a77980.dtsi" |
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/ { |
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model = "Renesas V3H Starter Kit board"; |
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compatible = "renesas,v3hsk", "renesas,r8a77980"; |
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aliases { |
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serial0 = &scif0; |
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ethernet0 = &gether; |
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}; |
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chosen { |
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stdout-path = "serial0:115200n8"; |
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}; |
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hdmi-out { |
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compatible = "hdmi-connector"; |
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type = "a"; |
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port { |
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hdmi_con: endpoint { |
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remote-endpoint = <&adv7511_out>; |
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}; |
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}; |
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}; |
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lvds-decoder { |
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compatible = "thine,thc63lvd1024"; |
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vcc-supply = <&vcc3v3_d5>; |
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ports { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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port@0 { |
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reg = <0>; |
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thc63lvd1024_in: endpoint { |
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remote-endpoint = <&lvds0_out>; |
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}; |
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}; |
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port@2 { |
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reg = <2>; |
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thc63lvd1024_out: endpoint { |
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remote-endpoint = <&adv7511_in>; |
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}; |
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}; |
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}; |
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}; |
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memory@48000000 { |
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device_type = "memory"; |
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/* first 128MB is reserved for secure area. */ |
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reg = <0 0x48000000 0 0x78000000>; |
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}; |
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osc1_clk: osc1-clock { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <148500000>; |
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}; |
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vcc1v8_d4: regulator-0 { |
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compatible = "regulator-fixed"; |
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regulator-name = "VCC1V8_D4"; |
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regulator-min-microvolt = <1800000>; |
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regulator-max-microvolt = <1800000>; |
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regulator-boot-on; |
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regulator-always-on; |
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}; |
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vcc3v3_d5: regulator-1 { |
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compatible = "regulator-fixed"; |
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regulator-name = "VCC3V3_D5"; |
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regulator-min-microvolt = <3300000>; |
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regulator-max-microvolt = <3300000>; |
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regulator-boot-on; |
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regulator-always-on; |
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}; |
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}; |
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&du { |
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clocks = <&cpg CPG_MOD 724>, |
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<&osc1_clk>; |
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clock-names = "du.0", "dclkin.0"; |
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status = "okay"; |
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}; |
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&extal_clk { |
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clock-frequency = <16666666>; |
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}; |
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&extalr_clk { |
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clock-frequency = <32768>; |
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}; |
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&gether { |
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pinctrl-0 = <&gether_pins>; |
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pinctrl-names = "default"; |
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phy-mode = "rgmii"; |
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phy-handle = <&phy0>; |
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renesas,no-ether-link; |
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status = "okay"; |
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phy0: ethernet-phy@0 { |
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reg = <0>; |
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interrupt-parent = <&gpio4>; |
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interrupts = <23 IRQ_TYPE_LEVEL_LOW>; |
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}; |
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}; |
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&i2c0 { |
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pinctrl-0 = <&i2c0_pins>; |
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pinctrl-names = "default"; |
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status = "okay"; |
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clock-frequency = <400000>; |
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hdmi@39 { |
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compatible = "adi,adv7511w"; |
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#sound-dai-cells = <0>; |
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reg = <0x39>; |
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interrupt-parent = <&gpio1>; |
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interrupts = <20 IRQ_TYPE_LEVEL_LOW>; |
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avdd-supply = <&vcc1v8_d4>; |
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dvdd-supply = <&vcc1v8_d4>; |
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pvdd-supply = <&vcc1v8_d4>; |
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bgvdd-supply = <&vcc1v8_d4>; |
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dvdd-3v-supply = <&vcc3v3_d5>; |
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adi,input-depth = <8>; |
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adi,input-colorspace = "rgb"; |
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adi,input-clock = "1x"; |
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ports { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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port@0 { |
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reg = <0>; |
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adv7511_in: endpoint { |
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remote-endpoint = <&thc63lvd1024_out>; |
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}; |
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}; |
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port@1 { |
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reg = <1>; |
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adv7511_out: endpoint { |
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remote-endpoint = <&hdmi_con>; |
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}; |
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}; |
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}; |
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}; |
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}; |
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&lvds0 { |
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status = "okay"; |
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ports { |
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port@1 { |
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lvds0_out: endpoint { |
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remote-endpoint = <&thc63lvd1024_in>; |
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}; |
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}; |
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}; |
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}; |
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&pfc { |
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gether_pins: gether { |
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groups = "gether_mdio_a", "gether_rgmii", |
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"gether_txcrefclk", "gether_txcrefclk_mega"; |
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function = "gether"; |
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}; |
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i2c0_pins: i2c0 { |
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groups = "i2c0"; |
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function = "i2c0"; |
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}; |
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qspi0_pins: qspi0 { |
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groups = "qspi0_ctrl", "qspi0_data4"; |
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function = "qspi0"; |
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}; |
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scif0_pins: scif0 { |
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groups = "scif0_data"; |
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function = "scif0"; |
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}; |
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scif_clk_pins: scif_clk { |
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groups = "scif_clk_b"; |
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function = "scif_clk"; |
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}; |
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}; |
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&rpc { |
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pinctrl-0 = <&qspi0_pins>; |
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pinctrl-names = "default"; |
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status = "okay"; |
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flash@0 { |
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compatible = "spansion,s25fs512s", "jedec,spi-nor"; |
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reg = <0>; |
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spi-max-frequency = <50000000>; |
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spi-rx-bus-width = <4>; |
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partitions { |
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compatible = "fixed-partitions"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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bootparam@0 { |
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reg = <0x00000000 0x040000>; |
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read-only; |
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}; |
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cr7@40000 { |
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reg = <0x00040000 0x080000>; |
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read-only; |
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}; |
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cert_header_sa3@c0000 { |
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reg = <0x000c0000 0x080000>; |
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read-only; |
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}; |
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bl2@140000 { |
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reg = <0x00140000 0x040000>; |
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read-only; |
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}; |
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cert_header_sa6@180000 { |
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reg = <0x00180000 0x040000>; |
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read-only; |
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}; |
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bl31@1c0000 { |
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reg = <0x001c0000 0x460000>; |
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read-only; |
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}; |
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uboot@640000 { |
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reg = <0x00640000 0x0c0000>; |
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read-only; |
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}; |
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uboot-env@700000 { |
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reg = <0x00700000 0x040000>; |
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read-only; |
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}; |
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dtb@740000 { |
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reg = <0x00740000 0x080000>; |
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}; |
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kernel@7c0000 { |
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reg = <0x007c0000 0x1400000>; |
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}; |
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user@1bc0000 { |
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reg = <0x01bc0000 0x2440000>; |
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}; |
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}; |
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}; |
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}; |
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&rwdt { |
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timeout-sec = <60>; |
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status = "okay"; |
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}; |
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&scif0 { |
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pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>; |
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pinctrl-names = "default"; |
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status = "okay"; |
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}; |
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&scif_clk { |
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clock-frequency = <14745600>; |
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};
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