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693 lines
17 KiB
693 lines
17 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (c) 2017, The Linux Foundation. All rights reserved. |
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*/ |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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#include <dt-bindings/clock/qcom,gcc-ipq8074.h> |
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/ { |
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model = "Qualcomm Technologies, Inc. IPQ8074"; |
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compatible = "qcom,ipq8074"; |
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clocks { |
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sleep_clk: sleep_clk { |
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compatible = "fixed-clock"; |
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clock-frequency = <32000>; |
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#clock-cells = <0>; |
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}; |
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xo: xo { |
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compatible = "fixed-clock"; |
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clock-frequency = <19200000>; |
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#clock-cells = <0>; |
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}; |
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}; |
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cpus { |
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#address-cells = <0x1>; |
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#size-cells = <0x0>; |
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CPU0: cpu@0 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a53"; |
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reg = <0x0>; |
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next-level-cache = <&L2_0>; |
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enable-method = "psci"; |
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}; |
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CPU1: cpu@1 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a53"; |
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enable-method = "psci"; |
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reg = <0x1>; |
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next-level-cache = <&L2_0>; |
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}; |
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CPU2: cpu@2 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a53"; |
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enable-method = "psci"; |
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reg = <0x2>; |
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next-level-cache = <&L2_0>; |
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}; |
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CPU3: cpu@3 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a53"; |
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enable-method = "psci"; |
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reg = <0x3>; |
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next-level-cache = <&L2_0>; |
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}; |
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L2_0: l2-cache { |
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compatible = "cache"; |
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cache-level = <0x2>; |
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}; |
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}; |
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pmu { |
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compatible = "arm,cortex-a53-pmu"; |
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interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
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}; |
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psci { |
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compatible = "arm,psci-1.0"; |
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method = "smc"; |
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}; |
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soc: soc { |
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#address-cells = <0x1>; |
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#size-cells = <0x1>; |
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ranges = <0 0 0 0xffffffff>; |
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compatible = "simple-bus"; |
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ssphy_1: phy@58000 { |
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compatible = "qcom,ipq8074-qmp-usb3-phy"; |
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reg = <0x00058000 0x1c4>; |
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#clock-cells = <1>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges; |
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clocks = <&gcc GCC_USB1_AUX_CLK>, |
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<&gcc GCC_USB1_PHY_CFG_AHB_CLK>, |
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<&xo>; |
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clock-names = "aux", "cfg_ahb", "ref"; |
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resets = <&gcc GCC_USB1_PHY_BCR>, |
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<&gcc GCC_USB3PHY_1_PHY_BCR>; |
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reset-names = "phy","common"; |
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status = "disabled"; |
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usb1_ssphy: lane@58200 { |
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reg = <0x00058200 0x130>, /* Tx */ |
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<0x00058400 0x200>, /* Rx */ |
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<0x00058800 0x1f8>, /* PCS */ |
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<0x00058600 0x044>; /* PCS misc*/ |
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#phy-cells = <0>; |
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clocks = <&gcc GCC_USB1_PIPE_CLK>; |
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clock-names = "pipe0"; |
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clock-output-names = "gcc_usb1_pipe_clk_src"; |
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}; |
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}; |
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qusb_phy_1: phy@59000 { |
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compatible = "qcom,ipq8074-qusb2-phy"; |
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reg = <0x00059000 0x180>; |
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#phy-cells = <0>; |
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clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, |
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<&xo>; |
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clock-names = "cfg_ahb", "ref"; |
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resets = <&gcc GCC_QUSB2_1_PHY_BCR>; |
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status = "disabled"; |
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}; |
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ssphy_0: phy@78000 { |
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compatible = "qcom,ipq8074-qmp-usb3-phy"; |
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reg = <0x00078000 0x1c4>; |
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#clock-cells = <1>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges; |
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clocks = <&gcc GCC_USB0_AUX_CLK>, |
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<&gcc GCC_USB0_PHY_CFG_AHB_CLK>, |
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<&xo>; |
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clock-names = "aux", "cfg_ahb", "ref"; |
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resets = <&gcc GCC_USB0_PHY_BCR>, |
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<&gcc GCC_USB3PHY_0_PHY_BCR>; |
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reset-names = "phy","common"; |
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status = "disabled"; |
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usb0_ssphy: lane@78200 { |
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reg = <0x00078200 0x130>, /* Tx */ |
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<0x00078400 0x200>, /* Rx */ |
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<0x00078800 0x1f8>, /* PCS */ |
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<0x00078600 0x044>; /* PCS misc*/ |
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#phy-cells = <0>; |
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clocks = <&gcc GCC_USB0_PIPE_CLK>; |
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clock-names = "pipe0"; |
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clock-output-names = "gcc_usb0_pipe_clk_src"; |
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}; |
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}; |
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qusb_phy_0: phy@79000 { |
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compatible = "qcom,ipq8074-qusb2-phy"; |
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reg = <0x00079000 0x180>; |
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#phy-cells = <0>; |
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clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, |
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<&xo>; |
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clock-names = "cfg_ahb", "ref"; |
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resets = <&gcc GCC_QUSB2_0_PHY_BCR>; |
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}; |
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pcie_phy0: phy@86000 { |
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compatible = "qcom,ipq8074-qmp-pcie-phy"; |
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reg = <0x00086000 0x1000>; |
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#phy-cells = <0>; |
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clocks = <&gcc GCC_PCIE0_PIPE_CLK>; |
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clock-names = "pipe_clk"; |
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clock-output-names = "pcie20_phy0_pipe_clk"; |
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resets = <&gcc GCC_PCIE0_PHY_BCR>, |
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<&gcc GCC_PCIE0PHY_PHY_BCR>; |
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reset-names = "phy", |
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"common"; |
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status = "disabled"; |
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}; |
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pcie_phy1: phy@8e000 { |
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compatible = "qcom,ipq8074-qmp-pcie-phy"; |
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reg = <0x0008e000 0x1000>; |
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#phy-cells = <0>; |
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clocks = <&gcc GCC_PCIE1_PIPE_CLK>; |
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clock-names = "pipe_clk"; |
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clock-output-names = "pcie20_phy1_pipe_clk"; |
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resets = <&gcc GCC_PCIE1_PHY_BCR>, |
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<&gcc GCC_PCIE1PHY_PHY_BCR>; |
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reset-names = "phy", |
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"common"; |
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status = "disabled"; |
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}; |
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tlmm: pinctrl@1000000 { |
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compatible = "qcom,ipq8074-pinctrl"; |
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reg = <0x01000000 0x300000>; |
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; |
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gpio-controller; |
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gpio-ranges = <&tlmm 0 0 70>; |
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#gpio-cells = <0x2>; |
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interrupt-controller; |
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#interrupt-cells = <0x2>; |
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serial_4_pins: serial4-pinmux { |
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pins = "gpio23", "gpio24"; |
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function = "blsp4_uart1"; |
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drive-strength = <8>; |
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bias-disable; |
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}; |
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i2c_0_pins: i2c-0-pinmux { |
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pins = "gpio42", "gpio43"; |
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function = "blsp1_i2c"; |
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drive-strength = <8>; |
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bias-disable; |
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}; |
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spi_0_pins: spi-0-pins { |
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pins = "gpio38", "gpio39", "gpio40", "gpio41"; |
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function = "blsp0_spi"; |
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drive-strength = <8>; |
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bias-disable; |
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}; |
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hsuart_pins: hsuart-pins { |
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pins = "gpio46", "gpio47", "gpio48", "gpio49"; |
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function = "blsp2_uart"; |
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drive-strength = <8>; |
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bias-disable; |
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}; |
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qpic_pins: qpic-pins { |
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pins = "gpio1", "gpio3", "gpio4", |
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"gpio5", "gpio6", "gpio7", |
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"gpio8", "gpio10", "gpio11", |
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"gpio12", "gpio13", "gpio14", |
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"gpio15", "gpio16", "gpio17"; |
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function = "qpic"; |
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drive-strength = <8>; |
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bias-disable; |
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}; |
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}; |
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gcc: gcc@1800000 { |
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compatible = "qcom,gcc-ipq8074"; |
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reg = <0x01800000 0x80000>; |
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#clock-cells = <0x1>; |
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#reset-cells = <0x1>; |
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}; |
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sdhc_1: sdhci@7824900 { |
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compatible = "qcom,sdhci-msm-v4"; |
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reg = <0x7824900 0x500>, <0x7824000 0x800>; |
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reg-names = "hc_mem", "core_mem"; |
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interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; |
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interrupt-names = "hc_irq", "pwr_irq"; |
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clocks = <&xo>, |
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<&gcc GCC_SDCC1_AHB_CLK>, |
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<&gcc GCC_SDCC1_APPS_CLK>; |
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clock-names = "xo", "iface", "core"; |
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max-frequency = <384000000>; |
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mmc-ddr-1_8v; |
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mmc-hs200-1_8v; |
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mmc-hs400-1_8v; |
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bus-width = <8>; |
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status = "disabled"; |
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}; |
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blsp_dma: dma-controller@7884000 { |
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compatible = "qcom,bam-v1.7.0"; |
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reg = <0x07884000 0x2b000>; |
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interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&gcc GCC_BLSP1_AHB_CLK>; |
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clock-names = "bam_clk"; |
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#dma-cells = <1>; |
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qcom,ee = <0>; |
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}; |
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blsp1_uart1: serial@78af000 { |
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; |
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reg = <0x078af000 0x200>; |
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interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, |
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<&gcc GCC_BLSP1_AHB_CLK>; |
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clock-names = "core", "iface"; |
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status = "disabled"; |
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}; |
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blsp1_uart3: serial@78b1000 { |
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; |
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reg = <0x078b1000 0x200>; |
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interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, |
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<&gcc GCC_BLSP1_AHB_CLK>; |
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clock-names = "core", "iface"; |
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dmas = <&blsp_dma 4>, |
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<&blsp_dma 5>; |
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dma-names = "tx", "rx"; |
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pinctrl-0 = <&hsuart_pins>; |
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pinctrl-names = "default"; |
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status = "disabled"; |
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}; |
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blsp1_uart5: serial@78b3000 { |
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; |
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reg = <0x078b3000 0x200>; |
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interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, |
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<&gcc GCC_BLSP1_AHB_CLK>; |
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clock-names = "core", "iface"; |
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pinctrl-0 = <&serial_4_pins>; |
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pinctrl-names = "default"; |
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status = "disabled"; |
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}; |
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blsp1_spi1: spi@78b5000 { |
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compatible = "qcom,spi-qup-v2.2.1"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <0x078b5000 0x600>; |
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interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; |
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spi-max-frequency = <50000000>; |
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clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, |
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<&gcc GCC_BLSP1_AHB_CLK>; |
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clock-names = "core", "iface"; |
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dmas = <&blsp_dma 12>, <&blsp_dma 13>; |
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dma-names = "tx", "rx"; |
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pinctrl-0 = <&spi_0_pins>; |
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pinctrl-names = "default"; |
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status = "disabled"; |
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}; |
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blsp1_i2c2: i2c@78b6000 { |
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compatible = "qcom,i2c-qup-v2.2.1"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <0x078b6000 0x600>; |
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&gcc GCC_BLSP1_AHB_CLK>, |
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<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; |
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clock-names = "iface", "core"; |
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clock-frequency = <400000>; |
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dmas = <&blsp_dma 15>, <&blsp_dma 14>; |
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dma-names = "rx", "tx"; |
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pinctrl-0 = <&i2c_0_pins>; |
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pinctrl-names = "default"; |
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status = "disabled"; |
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}; |
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blsp1_i2c3: i2c@78b7000 { |
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compatible = "qcom,i2c-qup-v2.2.1"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <0x078b7000 0x600>; |
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&gcc GCC_BLSP1_AHB_CLK>, |
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<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; |
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clock-names = "iface", "core"; |
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clock-frequency = <100000>; |
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dmas = <&blsp_dma 17>, <&blsp_dma 16>; |
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dma-names = "rx", "tx"; |
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status = "disabled"; |
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}; |
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qpic_bam: dma-controller@7984000 { |
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compatible = "qcom,bam-v1.7.0"; |
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reg = <0x07984000 0x1a000>; |
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interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&gcc GCC_QPIC_AHB_CLK>; |
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clock-names = "bam_clk"; |
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#dma-cells = <1>; |
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qcom,ee = <0>; |
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status = "disabled"; |
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}; |
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qpic_nand: nand@79b0000 { |
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compatible = "qcom,ipq8074-nand"; |
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reg = <0x079b0000 0x10000>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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clocks = <&gcc GCC_QPIC_CLK>, |
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<&gcc GCC_QPIC_AHB_CLK>; |
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clock-names = "core", "aon"; |
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dmas = <&qpic_bam 0>, |
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<&qpic_bam 1>, |
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<&qpic_bam 2>; |
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dma-names = "tx", "rx", "cmd"; |
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pinctrl-0 = <&qpic_pins>; |
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pinctrl-names = "default"; |
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status = "disabled"; |
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}; |
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usb_0: usb@8af8800 { |
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compatible = "qcom,dwc3"; |
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reg = <0x08af8800 0x400>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges; |
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clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, |
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<&gcc GCC_USB0_MASTER_CLK>, |
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<&gcc GCC_USB0_SLEEP_CLK>, |
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<&gcc GCC_USB0_MOCK_UTMI_CLK>; |
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clock-names = "sys_noc_axi", |
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"master", |
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"sleep", |
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"mock_utmi"; |
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assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, |
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<&gcc GCC_USB0_MASTER_CLK>, |
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<&gcc GCC_USB0_MOCK_UTMI_CLK>; |
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assigned-clock-rates = <133330000>, |
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<133330000>, |
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<19200000>; |
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resets = <&gcc GCC_USB0_BCR>; |
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status = "disabled"; |
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dwc_0: dwc3@8a00000 { |
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compatible = "snps,dwc3"; |
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reg = <0x8a00000 0xcd00>; |
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interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; |
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phys = <&qusb_phy_0>, <&usb0_ssphy>; |
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phy-names = "usb2-phy", "usb3-phy"; |
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tx-fifo-resize; |
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snps,is-utmi-l1-suspend; |
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snps,hird-threshold = /bits/ 8 <0x0>; |
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snps,dis_u2_susphy_quirk; |
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snps,dis_u3_susphy_quirk; |
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dr_mode = "host"; |
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}; |
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}; |
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usb_1: usb@8cf8800 { |
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compatible = "qcom,dwc3"; |
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reg = <0x08cf8800 0x400>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges; |
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clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, |
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<&gcc GCC_USB1_MASTER_CLK>, |
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<&gcc GCC_USB1_SLEEP_CLK>, |
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<&gcc GCC_USB1_MOCK_UTMI_CLK>; |
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clock-names = "sys_noc_axi", |
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"master", |
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"sleep", |
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"mock_utmi"; |
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assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, |
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<&gcc GCC_USB1_MASTER_CLK>, |
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<&gcc GCC_USB1_MOCK_UTMI_CLK>; |
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assigned-clock-rates = <133330000>, |
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<133330000>, |
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<19200000>; |
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resets = <&gcc GCC_USB1_BCR>; |
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status = "disabled"; |
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dwc_1: dwc3@8c00000 { |
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compatible = "snps,dwc3"; |
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reg = <0x8c00000 0xcd00>; |
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interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; |
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phys = <&qusb_phy_1>, <&usb1_ssphy>; |
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phy-names = "usb2-phy", "usb3-phy"; |
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tx-fifo-resize; |
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snps,is-utmi-l1-suspend; |
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snps,hird-threshold = /bits/ 8 <0x0>; |
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snps,dis_u2_susphy_quirk; |
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snps,dis_u3_susphy_quirk; |
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dr_mode = "host"; |
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}; |
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}; |
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intc: interrupt-controller@b000000 { |
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compatible = "qcom,msm-qgic2"; |
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interrupt-controller; |
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#interrupt-cells = <0x3>; |
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reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; |
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}; |
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timer { |
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compatible = "arm,armv8-timer"; |
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interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
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<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
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<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
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<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
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}; |
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watchdog: watchdog@b017000 { |
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compatible = "qcom,kpss-wdt"; |
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reg = <0xb017000 0x1000>; |
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interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; |
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clocks = <&sleep_clk>; |
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timeout-sec = <30>; |
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}; |
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timer@b120000 { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges; |
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compatible = "arm,armv7-timer-mem"; |
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reg = <0x0b120000 0x1000>; |
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clock-frequency = <19200000>; |
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frame@b120000 { |
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frame-number = <0>; |
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
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reg = <0x0b121000 0x1000>, |
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<0x0b122000 0x1000>; |
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}; |
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frame@b123000 { |
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frame-number = <1>; |
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
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reg = <0x0b123000 0x1000>; |
|
status = "disabled"; |
|
}; |
|
|
|
frame@b124000 { |
|
frame-number = <2>; |
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
|
reg = <0x0b124000 0x1000>; |
|
status = "disabled"; |
|
}; |
|
|
|
frame@b125000 { |
|
frame-number = <3>; |
|
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
|
reg = <0x0b125000 0x1000>; |
|
status = "disabled"; |
|
}; |
|
|
|
frame@b126000 { |
|
frame-number = <4>; |
|
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; |
|
reg = <0x0b126000 0x1000>; |
|
status = "disabled"; |
|
}; |
|
|
|
frame@b127000 { |
|
frame-number = <5>; |
|
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; |
|
reg = <0x0b127000 0x1000>; |
|
status = "disabled"; |
|
}; |
|
|
|
frame@b128000 { |
|
frame-number = <6>; |
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
|
reg = <0x0b128000 0x1000>; |
|
status = "disabled"; |
|
}; |
|
}; |
|
|
|
pcie1: pci@10000000 { |
|
compatible = "qcom,pcie-ipq8074"; |
|
reg = <0x10000000 0xf1d |
|
0x10000f20 0xa8 |
|
0x00088000 0x2000 |
|
0x10100000 0x1000>; |
|
reg-names = "dbi", "elbi", "parf", "config"; |
|
device_type = "pci"; |
|
linux,pci-domain = <1>; |
|
bus-range = <0x00 0xff>; |
|
num-lanes = <1>; |
|
#address-cells = <3>; |
|
#size-cells = <2>; |
|
|
|
phys = <&pcie_phy1>; |
|
phy-names = "pciephy"; |
|
|
|
ranges = <0x81000000 0 0x10200000 0x10200000 |
|
0 0x100000 /* downstream I/O */ |
|
0x82000000 0 0x10300000 0x10300000 |
|
0 0xd00000>; /* non-prefetchable memory */ |
|
|
|
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
|
interrupt-names = "msi"; |
|
#interrupt-cells = <1>; |
|
interrupt-map-mask = <0 0 0 0x7>; |
|
interrupt-map = <0 0 0 1 &intc 0 142 |
|
IRQ_TYPE_LEVEL_HIGH>, /* int_a */ |
|
<0 0 0 2 &intc 0 143 |
|
IRQ_TYPE_LEVEL_HIGH>, /* int_b */ |
|
<0 0 0 3 &intc 0 144 |
|
IRQ_TYPE_LEVEL_HIGH>, /* int_c */ |
|
<0 0 0 4 &intc 0 145 |
|
IRQ_TYPE_LEVEL_HIGH>; /* int_d */ |
|
|
|
clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>, |
|
<&gcc GCC_PCIE1_AXI_M_CLK>, |
|
<&gcc GCC_PCIE1_AXI_S_CLK>, |
|
<&gcc GCC_PCIE1_AHB_CLK>, |
|
<&gcc GCC_PCIE1_AUX_CLK>; |
|
clock-names = "iface", |
|
"axi_m", |
|
"axi_s", |
|
"ahb", |
|
"aux"; |
|
resets = <&gcc GCC_PCIE1_PIPE_ARES>, |
|
<&gcc GCC_PCIE1_SLEEP_ARES>, |
|
<&gcc GCC_PCIE1_CORE_STICKY_ARES>, |
|
<&gcc GCC_PCIE1_AXI_MASTER_ARES>, |
|
<&gcc GCC_PCIE1_AXI_SLAVE_ARES>, |
|
<&gcc GCC_PCIE1_AHB_ARES>, |
|
<&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>; |
|
reset-names = "pipe", |
|
"sleep", |
|
"sticky", |
|
"axi_m", |
|
"axi_s", |
|
"ahb", |
|
"axi_m_sticky"; |
|
status = "disabled"; |
|
}; |
|
|
|
pcie0: pci@20000000 { |
|
compatible = "qcom,pcie-ipq8074"; |
|
reg = <0x20000000 0xf1d |
|
0x20000f20 0xa8 |
|
0x00080000 0x2000 |
|
0x20100000 0x1000>; |
|
reg-names = "dbi", "elbi", "parf", "config"; |
|
device_type = "pci"; |
|
linux,pci-domain = <0>; |
|
bus-range = <0x00 0xff>; |
|
num-lanes = <1>; |
|
#address-cells = <3>; |
|
#size-cells = <2>; |
|
|
|
phys = <&pcie_phy0>; |
|
phy-names = "pciephy"; |
|
|
|
ranges = <0x81000000 0 0x20200000 0x20200000 |
|
0 0x100000 /* downstream I/O */ |
|
0x82000000 0 0x20300000 0x20300000 |
|
0 0xd00000>; /* non-prefetchable memory */ |
|
|
|
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; |
|
interrupt-names = "msi"; |
|
#interrupt-cells = <1>; |
|
interrupt-map-mask = <0 0 0 0x7>; |
|
interrupt-map = <0 0 0 1 &intc 0 75 |
|
IRQ_TYPE_LEVEL_HIGH>, /* int_a */ |
|
<0 0 0 2 &intc 0 78 |
|
IRQ_TYPE_LEVEL_HIGH>, /* int_b */ |
|
<0 0 0 3 &intc 0 79 |
|
IRQ_TYPE_LEVEL_HIGH>, /* int_c */ |
|
<0 0 0 4 &intc 0 83 |
|
IRQ_TYPE_LEVEL_HIGH>; /* int_d */ |
|
|
|
clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, |
|
<&gcc GCC_PCIE0_AXI_M_CLK>, |
|
<&gcc GCC_PCIE0_AXI_S_CLK>, |
|
<&gcc GCC_PCIE0_AHB_CLK>, |
|
<&gcc GCC_PCIE0_AUX_CLK>; |
|
|
|
clock-names = "iface", |
|
"axi_m", |
|
"axi_s", |
|
"ahb", |
|
"aux"; |
|
resets = <&gcc GCC_PCIE0_PIPE_ARES>, |
|
<&gcc GCC_PCIE0_SLEEP_ARES>, |
|
<&gcc GCC_PCIE0_CORE_STICKY_ARES>, |
|
<&gcc GCC_PCIE0_AXI_MASTER_ARES>, |
|
<&gcc GCC_PCIE0_AXI_SLAVE_ARES>, |
|
<&gcc GCC_PCIE0_AHB_ARES>, |
|
<&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>; |
|
reset-names = "pipe", |
|
"sleep", |
|
"sticky", |
|
"axi_m", |
|
"axi_s", |
|
"ahb", |
|
"axi_m_sticky"; |
|
status = "disabled"; |
|
}; |
|
}; |
|
};
|
|
|