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542 lines
14 KiB
542 lines
14 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (c) 2019 MediaTek Inc. |
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* Copyright (c) 2019 BayLibre, SAS. |
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* Author: Fabien Parent <[email protected]> |
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*/ |
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#include <dt-bindings/clock/mt8516-clk.h> |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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#include <dt-bindings/interrupt-controller/irq.h> |
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#include <dt-bindings/phy/phy.h> |
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#include "mt8516-pinfunc.h" |
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/ { |
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compatible = "mediatek,mt8516"; |
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interrupt-parent = <&sysirq>; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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cluster0_opp: opp-table-0 { |
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compatible = "operating-points-v2"; |
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opp-shared; |
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opp-598000000 { |
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opp-hz = /bits/ 64 <598000000>; |
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opp-microvolt = <1150000>; |
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}; |
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opp-747500000 { |
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opp-hz = /bits/ 64 <747500000>; |
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opp-microvolt = <1150000>; |
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}; |
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opp-1040000000 { |
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opp-hz = /bits/ 64 <1040000000>; |
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opp-microvolt = <1200000>; |
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}; |
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opp-1196000000 { |
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opp-hz = /bits/ 64 <1196000000>; |
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opp-microvolt = <1250000>; |
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}; |
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opp-1300000000 { |
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opp-hz = /bits/ 64 <1300000000>; |
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opp-microvolt = <1300000>; |
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}; |
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}; |
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cpus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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cpu0: cpu@0 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a35"; |
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reg = <0x0>; |
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enable-method = "psci"; |
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cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>, |
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<&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>; |
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clocks = <&infracfg CLK_IFR_MUX1_SEL>, |
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<&topckgen CLK_TOP_MAINPLL_D2>; |
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clock-names = "cpu", "intermediate"; |
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operating-points-v2 = <&cluster0_opp>; |
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}; |
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cpu1: cpu@1 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a35"; |
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reg = <0x1>; |
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enable-method = "psci"; |
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cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>, |
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<&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>; |
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clocks = <&infracfg CLK_IFR_MUX1_SEL>, |
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<&topckgen CLK_TOP_MAINPLL_D2>; |
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clock-names = "cpu", "intermediate"; |
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operating-points-v2 = <&cluster0_opp>; |
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}; |
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cpu2: cpu@2 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a35"; |
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reg = <0x2>; |
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enable-method = "psci"; |
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cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>, |
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<&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>; |
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clocks = <&infracfg CLK_IFR_MUX1_SEL>, |
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<&topckgen CLK_TOP_MAINPLL_D2>; |
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clock-names = "cpu", "intermediate"; |
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operating-points-v2 = <&cluster0_opp>; |
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}; |
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cpu3: cpu@3 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a35"; |
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reg = <0x3>; |
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enable-method = "psci"; |
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cpu-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_0>, |
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<&CPU_SLEEP_0_0 &CPU_SLEEP_0_0 &CPU_SLEEP_0_0>; |
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clocks = <&infracfg CLK_IFR_MUX1_SEL>, |
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<&topckgen CLK_TOP_MAINPLL_D2>; |
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clock-names = "cpu", "intermediate", "armpll"; |
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operating-points-v2 = <&cluster0_opp>; |
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}; |
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idle-states { |
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entry-method = "psci"; |
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CPU_SLEEP_0_0: cpu-sleep-0-0 { |
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compatible = "arm,idle-state"; |
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entry-latency-us = <600>; |
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exit-latency-us = <600>; |
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min-residency-us = <1200>; |
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arm,psci-suspend-param = <0x0010000>; |
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}; |
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CLUSTER_SLEEP_0: cluster-sleep-0 { |
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compatible = "arm,idle-state"; |
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entry-latency-us = <800>; |
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exit-latency-us = <1000>; |
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min-residency-us = <2000>; |
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arm,psci-suspend-param = <0x2010000>; |
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}; |
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}; |
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}; |
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psci { |
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compatible = "arm,psci-1.0"; |
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method = "smc"; |
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}; |
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clk26m: clk26m { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <26000000>; |
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clock-output-names = "clk26m"; |
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}; |
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clk32k: clk32k { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <32000>; |
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clock-output-names = "clk32k"; |
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}; |
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reserved-memory { |
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#address-cells = <2>; |
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#size-cells = <2>; |
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ranges; |
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/* 128 KiB reserved for ARM Trusted Firmware (BL31) */ |
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bl31_secmon_reserved: secmon@43000000 { |
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no-map; |
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reg = <0 0x43000000 0 0x20000>; |
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}; |
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}; |
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timer { |
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compatible = "arm,armv8-timer"; |
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interrupt-parent = <&gic>; |
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interrupts = <GIC_PPI 13 |
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
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<GIC_PPI 14 |
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
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<GIC_PPI 11 |
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
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<GIC_PPI 10 |
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
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}; |
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pmu { |
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compatible = "arm,armv8-pmuv3"; |
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_LOW>, |
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<GIC_SPI 5 IRQ_TYPE_LEVEL_LOW>, |
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<GIC_SPI 6 IRQ_TYPE_LEVEL_LOW>, |
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<GIC_SPI 7 IRQ_TYPE_LEVEL_LOW>; |
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; |
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}; |
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soc { |
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#address-cells = <2>; |
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#size-cells = <2>; |
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compatible = "simple-bus"; |
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ranges; |
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topckgen: topckgen@10000000 { |
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compatible = "mediatek,mt8516-topckgen", "syscon"; |
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reg = <0 0x10000000 0 0x1000>; |
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#clock-cells = <1>; |
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}; |
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infracfg: infracfg@10001000 { |
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compatible = "mediatek,mt8516-infracfg", "syscon"; |
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reg = <0 0x10001000 0 0x1000>; |
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#clock-cells = <1>; |
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}; |
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pericfg: pericfg@10003050 { |
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compatible = "mediatek,mt8516-pericfg", "syscon"; |
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reg = <0 0x10003050 0 0x1000>; |
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}; |
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apmixedsys: apmixedsys@10018000 { |
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compatible = "mediatek,mt8516-apmixedsys", "syscon"; |
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reg = <0 0x10018000 0 0x710>; |
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#clock-cells = <1>; |
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}; |
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toprgu: toprgu@10007000 { |
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compatible = "mediatek,mt8516-wdt", |
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"mediatek,mt6589-wdt"; |
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reg = <0 0x10007000 0 0x1000>; |
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interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_FALLING>; |
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#reset-cells = <1>; |
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}; |
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timer: timer@10008000 { |
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compatible = "mediatek,mt8516-timer", |
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"mediatek,mt6577-timer"; |
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reg = <0 0x10008000 0 0x1000>; |
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interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; |
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clocks = <&topckgen CLK_TOP_CLK26M_D2>, |
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<&topckgen CLK_TOP_APXGPT>; |
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clock-names = "clk13m", "bus"; |
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}; |
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syscfg_pctl: syscfg-pctl@10005000 { |
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compatible = "syscon"; |
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reg = <0 0x10005000 0 0x1000>; |
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}; |
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pio: pinctrl@1000b000 { |
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compatible = "mediatek,mt8516-pinctrl"; |
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reg = <0 0x1000b000 0 0x1000>; |
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mediatek,pctl-regmap = <&syscfg_pctl>; |
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pins-are-numbered; |
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gpio-controller; |
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#gpio-cells = <2>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; |
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}; |
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efuse: efuse@10009000 { |
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compatible = "mediatek,mt8516-efuse", "mediatek,efuse"; |
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reg = <0 0x10009000 0 0x1000>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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}; |
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pwrap: pwrap@1000f000 { |
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compatible = "mediatek,mt8516-pwrap"; |
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reg = <0 0x1000f000 0 0x1000>; |
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reg-names = "pwrap"; |
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interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>; |
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clocks = <&topckgen CLK_TOP_PMICWRAP_26M>, |
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<&topckgen CLK_TOP_PMICWRAP_AP>; |
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clock-names = "spi", "wrap"; |
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}; |
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sysirq: interrupt-controller@10200620 { |
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compatible = "mediatek,mt8516-sysirq", |
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"mediatek,mt6577-sysirq"; |
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interrupt-controller; |
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#interrupt-cells = <3>; |
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interrupt-parent = <&gic>; |
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reg = <0 0x10200620 0 0x20>; |
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}; |
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gic: interrupt-controller@10310000 { |
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compatible = "arm,gic-400"; |
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#interrupt-cells = <3>; |
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interrupt-parent = <&gic>; |
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interrupt-controller; |
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reg = <0 0x10310000 0 0x1000>, |
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<0 0x10320000 0 0x1000>, |
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<0 0x10340000 0 0x2000>, |
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<0 0x10360000 0 0x2000>; |
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interrupts = <GIC_PPI 9 |
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
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}; |
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apdma: dma-controller@11000480 { |
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compatible = "mediatek,mt8516-uart-dma", |
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"mediatek,mt6577-uart-dma"; |
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reg = <0 0x11000480 0 0x80>, |
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<0 0x11000500 0 0x80>, |
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<0 0x11000580 0 0x80>, |
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<0 0x11000600 0 0x80>, |
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<0 0x11000980 0 0x80>, |
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<0 0x11000a00 0 0x80>; |
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>, |
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<GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>, |
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<GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>, |
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<GIC_SPI 99 IRQ_TYPE_LEVEL_LOW>, |
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<GIC_SPI 100 IRQ_TYPE_LEVEL_LOW>, |
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<GIC_SPI 101 IRQ_TYPE_LEVEL_LOW>; |
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dma-requests = <6>; |
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clocks = <&topckgen CLK_TOP_APDMA>; |
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clock-names = "apdma"; |
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#dma-cells = <1>; |
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}; |
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uart0: serial@11005000 { |
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compatible = "mediatek,mt8516-uart", |
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"mediatek,mt6577-uart"; |
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reg = <0 0x11005000 0 0x1000>; |
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; |
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clocks = <&topckgen CLK_TOP_UART0_SEL>, |
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<&topckgen CLK_TOP_UART0>; |
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clock-names = "baud", "bus"; |
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dmas = <&apdma 0 |
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&apdma 1>; |
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dma-names = "tx", "rx"; |
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status = "disabled"; |
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}; |
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uart1: serial@11006000 { |
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compatible = "mediatek,mt8516-uart", |
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"mediatek,mt6577-uart"; |
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reg = <0 0x11006000 0 0x1000>; |
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interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; |
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clocks = <&topckgen CLK_TOP_UART1_SEL>, |
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<&topckgen CLK_TOP_UART1>; |
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clock-names = "baud", "bus"; |
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dmas = <&apdma 2 |
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&apdma 3>; |
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dma-names = "tx", "rx"; |
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status = "disabled"; |
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}; |
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uart2: serial@11007000 { |
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compatible = "mediatek,mt8516-uart", |
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"mediatek,mt6577-uart"; |
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reg = <0 0x11007000 0 0x1000>; |
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interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_LOW>; |
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clocks = <&topckgen CLK_TOP_UART2_SEL>, |
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<&topckgen CLK_TOP_UART2>; |
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clock-names = "baud", "bus"; |
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dmas = <&apdma 4 |
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&apdma 5>; |
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dma-names = "tx", "rx"; |
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status = "disabled"; |
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}; |
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i2c0: i2c@11009000 { |
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compatible = "mediatek,mt8516-i2c", |
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"mediatek,mt2712-i2c"; |
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reg = <0 0x11009000 0 0x90>, |
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<0 0x11000180 0 0x80>; |
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interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; |
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clocks = <&topckgen CLK_TOP_AHB_INFRA_D2>, |
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<&infracfg CLK_IFR_I2C0_SEL>, |
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<&topckgen CLK_TOP_I2C0>, |
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<&topckgen CLK_TOP_APDMA>; |
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clock-names = "main-source", |
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"main-sel", |
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"main", |
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"dma"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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status = "disabled"; |
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}; |
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i2c1: i2c@1100a000 { |
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compatible = "mediatek,mt8516-i2c", |
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"mediatek,mt2712-i2c"; |
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reg = <0 0x1100a000 0 0x90>, |
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<0 0x11000200 0 0x80>; |
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interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; |
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clocks = <&topckgen CLK_TOP_AHB_INFRA_D2>, |
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<&infracfg CLK_IFR_I2C1_SEL>, |
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<&topckgen CLK_TOP_I2C1>, |
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<&topckgen CLK_TOP_APDMA>; |
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clock-names = "main-source", |
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"main-sel", |
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"main", |
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"dma"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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status = "disabled"; |
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}; |
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i2c2: i2c@1100b000 { |
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compatible = "mediatek,mt8516-i2c", |
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"mediatek,mt2712-i2c"; |
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reg = <0 0x1100b000 0 0x90>, |
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<0 0x11000280 0 0x80>; |
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; |
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clocks = <&topckgen CLK_TOP_AHB_INFRA_D2>, |
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<&infracfg CLK_IFR_I2C2_SEL>, |
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<&topckgen CLK_TOP_I2C2>, |
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<&topckgen CLK_TOP_APDMA>; |
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clock-names = "main-source", |
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"main-sel", |
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"main", |
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"dma"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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status = "disabled"; |
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}; |
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spi: spi@1100c000 { |
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compatible = "mediatek,mt8516-spi", |
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"mediatek,mt2712-spi"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <0 0x1100c000 0 0x1000>; |
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interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>; |
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clocks = <&topckgen CLK_TOP_UNIVPLL_D12>, |
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<&topckgen CLK_TOP_SPI_SEL>, |
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<&topckgen CLK_TOP_SPI>; |
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clock-names = "parent-clk", "sel-clk", "spi-clk"; |
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status = "disabled"; |
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}; |
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mmc0: mmc@11120000 { |
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compatible = "mediatek,mt8516-mmc"; |
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reg = <0 0x11120000 0 0x1000>; |
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; |
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clocks = <&topckgen CLK_TOP_MSDC0>, |
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<&topckgen CLK_TOP_AHB_INFRA_SEL>, |
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<&topckgen CLK_TOP_MSDC0_INFRA>; |
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clock-names = "source", "hclk", "source_cg"; |
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status = "disabled"; |
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}; |
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mmc1: mmc@11130000 { |
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compatible = "mediatek,mt8516-mmc"; |
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reg = <0 0x11130000 0 0x1000>; |
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interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; |
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clocks = <&topckgen CLK_TOP_MSDC1>, |
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<&topckgen CLK_TOP_AHB_INFRA_SEL>, |
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<&topckgen CLK_TOP_MSDC1_INFRA>; |
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clock-names = "source", "hclk", "source_cg"; |
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status = "disabled"; |
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}; |
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mmc2: mmc@11170000 { |
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compatible = "mediatek,mt8516-mmc"; |
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reg = <0 0x11170000 0 0x1000>; |
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interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>; |
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clocks = <&topckgen CLK_TOP_MSDC2>, |
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<&topckgen CLK_TOP_RG_MSDC2>, |
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<&topckgen CLK_TOP_MSDC2_INFRA>; |
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clock-names = "source", "hclk", "source_cg"; |
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status = "disabled"; |
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}; |
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ethernet: ethernet@11180000 { |
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compatible = "mediatek,mt8516-eth"; |
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reg = <0 0x11180000 0 0x1000>; |
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mediatek,pericfg = <&pericfg>; |
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interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>; |
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clocks = <&topckgen CLK_TOP_RG_ETH>, |
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<&topckgen CLK_TOP_66M_ETH>, |
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<&topckgen CLK_TOP_133M_ETH>; |
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clock-names = "core", "reg", "trans"; |
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status = "disabled"; |
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}; |
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rng: rng@1020c000 { |
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compatible = "mediatek,mt8516-rng", |
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"mediatek,mt7623-rng"; |
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reg = <0 0x1020c000 0 0x100>; |
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clocks = <&topckgen CLK_TOP_TRNG>; |
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clock-names = "rng"; |
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}; |
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pwm: pwm@11008000 { |
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compatible = "mediatek,mt8516-pwm"; |
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reg = <0 0x11008000 0 0x1000>; |
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#pwm-cells = <2>; |
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; |
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clocks = <&topckgen CLK_TOP_PWM>, |
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<&topckgen CLK_TOP_PWM_B>, |
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<&topckgen CLK_TOP_PWM1_FB>, |
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<&topckgen CLK_TOP_PWM2_FB>, |
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<&topckgen CLK_TOP_PWM3_FB>, |
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<&topckgen CLK_TOP_PWM4_FB>, |
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<&topckgen CLK_TOP_PWM5_FB>; |
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clock-names = "top", "main", "pwm1", "pwm2", "pwm3", |
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"pwm4", "pwm5"; |
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}; |
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usb0: usb@11100000 { |
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compatible = "mediatek,mtk-musb"; |
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reg = <0 0x11100000 0 0x1000>; |
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; |
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interrupt-names = "mc"; |
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phys = <&usb0_port PHY_TYPE_USB2>; |
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clocks = <&topckgen CLK_TOP_USB>, |
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<&topckgen CLK_TOP_USBIF>, |
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<&topckgen CLK_TOP_USB_1P>; |
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clock-names = "main","mcu","univpll"; |
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status = "disabled"; |
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}; |
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usb1: usb@11190000 { |
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compatible = "mediatek,mtk-musb"; |
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reg = <0 0x11190000 0 0x1000>; |
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interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_LOW>; |
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interrupt-names = "mc"; |
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phys = <&usb1_port PHY_TYPE_USB2>; |
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clocks = <&topckgen CLK_TOP_USB>, |
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<&topckgen CLK_TOP_USBIF>, |
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<&topckgen CLK_TOP_USB_1P>; |
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clock-names = "main","mcu","univpll"; |
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dr_mode = "host"; |
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status = "disabled"; |
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}; |
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usb_phy: usb@11110000 { |
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compatible = "mediatek,generic-tphy-v1"; |
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reg = <0 0x11110000 0 0x800>; |
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#address-cells = <2>; |
|
#size-cells = <2>; |
|
ranges; |
|
status = "disabled"; |
|
|
|
usb0_port: usb-phy@11110800 { |
|
reg = <0 0x11110800 0 0x100>; |
|
clocks = <&topckgen CLK_TOP_USB_PHY48M>; |
|
clock-names = "ref"; |
|
#phy-cells = <1>; |
|
}; |
|
|
|
usb1_port: usb-phy@11110900 { |
|
reg = <0 0x11110900 0 0x100>; |
|
clocks = <&topckgen CLK_TOP_USB_PHY48M>; |
|
clock-names = "ref"; |
|
#phy-cells = <1>; |
|
}; |
|
}; |
|
|
|
auxadc: adc@11003000 { |
|
compatible = "mediatek,mt8516-auxadc", |
|
"mediatek,mt8173-auxadc"; |
|
reg = <0 0x11003000 0 0x1000>; |
|
clocks = <&topckgen CLK_TOP_AUX_ADC>; |
|
clock-names = "main"; |
|
#io-channel-cells = <1>; |
|
status = "disabled"; |
|
}; |
|
}; |
|
};
|
|
|