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175 lines
3.9 KiB
175 lines
3.9 KiB
/* |
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* Copyright (c) 2015 MediaTek Inc. |
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* Author: Mars.C <[email protected]> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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*/ |
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#include <dt-bindings/interrupt-controller/irq.h> |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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/ { |
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compatible = "mediatek,mt6795"; |
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interrupt-parent = <&sysirq>; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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psci { |
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compatible = "arm,psci-0.2"; |
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method = "smc"; |
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}; |
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cpus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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cpu0: cpu@0 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a53"; |
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enable-method = "psci"; |
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reg = <0x000>; |
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}; |
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cpu1: cpu@1 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a53"; |
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enable-method = "psci"; |
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reg = <0x001>; |
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}; |
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cpu2: cpu@2 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a53"; |
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enable-method = "psci"; |
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reg = <0x002>; |
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}; |
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cpu3: cpu@3 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a53"; |
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enable-method = "psci"; |
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reg = <0x003>; |
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}; |
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cpu4: cpu@100 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a53"; |
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enable-method = "psci"; |
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reg = <0x100>; |
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}; |
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cpu5: cpu@101 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a53"; |
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enable-method = "psci"; |
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reg = <0x101>; |
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}; |
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cpu6: cpu@102 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a53"; |
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enable-method = "psci"; |
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reg = <0x102>; |
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}; |
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cpu7: cpu@103 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a53"; |
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enable-method = "psci"; |
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reg = <0x103>; |
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}; |
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}; |
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system_clk: dummy13m { |
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compatible = "fixed-clock"; |
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clock-frequency = <13000000>; |
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#clock-cells = <0>; |
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}; |
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rtc_clk: dummy32k { |
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compatible = "fixed-clock"; |
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clock-frequency = <32000>; |
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#clock-cells = <0>; |
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}; |
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uart_clk: dummy26m { |
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compatible = "fixed-clock"; |
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clock-frequency = <26000000>; |
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#clock-cells = <0>; |
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}; |
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timer { |
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compatible = "arm,armv8-timer"; |
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interrupt-parent = <&gic>; |
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interrupts = <GIC_PPI 13 |
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(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, |
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<GIC_PPI 14 |
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(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, |
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<GIC_PPI 11 |
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(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, |
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<GIC_PPI 10 |
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(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; |
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}; |
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sysirq: intpol-controller@10200620 { |
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compatible = "mediatek,mt6795-sysirq", |
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"mediatek,mt6577-sysirq"; |
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interrupt-controller; |
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#interrupt-cells = <3>; |
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interrupt-parent = <&gic>; |
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reg = <0 0x10200620 0 0x20>; |
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}; |
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gic: interrupt-controller@10221000 { |
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compatible = "arm,gic-400"; |
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#interrupt-cells = <3>; |
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interrupt-parent = <&gic>; |
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interrupt-controller; |
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reg = <0 0x10221000 0 0x1000>, |
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<0 0x10222000 0 0x2000>, |
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<0 0x10224000 0 0x2000>, |
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<0 0x10226000 0 0x2000>; |
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}; |
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uart0: serial@11002000 { |
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compatible = "mediatek,mt6795-uart", |
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"mediatek,mt6577-uart"; |
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reg = <0 0x11002000 0 0x400>; |
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interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; |
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clocks = <&uart_clk>; |
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status = "disabled"; |
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}; |
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uart1: serial@11003000 { |
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compatible = "mediatek,mt6795-uart", |
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"mediatek,mt6577-uart"; |
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reg = <0 0x11003000 0 0x400>; |
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interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; |
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clocks = <&uart_clk>; |
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status = "disabled"; |
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}; |
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uart2: serial@11004000 { |
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compatible = "mediatek,mt6795-uart", |
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"mediatek,mt6577-uart"; |
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reg = <0 0x11004000 0 0x400>; |
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interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; |
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clocks = <&uart_clk>; |
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status = "disabled"; |
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}; |
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uart3: serial@11005000 { |
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compatible = "mediatek,mt6795-uart", |
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"mediatek,mt6577-uart"; |
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reg = <0 0x11005000 0 0x400>; |
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interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>; |
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clocks = <&uart_clk>; |
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status = "disabled"; |
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}; |
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};
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