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123 lines
2.6 KiB
123 lines
2.6 KiB
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) |
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/* |
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* Copyright (C) 2020, Intel Corporation. |
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* |
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* Device tree describing Keem Bay SoC. |
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*/ |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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/ { |
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interrupt-parent = <&gic>; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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cpus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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cpu@0 { |
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compatible = "arm,cortex-a53"; |
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device_type = "cpu"; |
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reg = <0x0>; |
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enable-method = "psci"; |
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}; |
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cpu@1 { |
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compatible = "arm,cortex-a53"; |
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device_type = "cpu"; |
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reg = <0x1>; |
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enable-method = "psci"; |
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}; |
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cpu@2 { |
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compatible = "arm,cortex-a53"; |
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device_type = "cpu"; |
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reg = <0x2>; |
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enable-method = "psci"; |
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}; |
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cpu@3 { |
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compatible = "arm,cortex-a53"; |
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device_type = "cpu"; |
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reg = <0x3>; |
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enable-method = "psci"; |
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}; |
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}; |
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psci { |
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compatible = "arm,psci-0.2"; |
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method = "smc"; |
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}; |
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gic: interrupt-controller@20500000 { |
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compatible = "arm,gic-v3"; |
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interrupt-controller; |
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#interrupt-cells = <3>; |
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reg = <0x0 0x20500000 0x0 0x20000>, /* GICD */ |
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<0x0 0x20580000 0x0 0x80000>; /* GICR */ |
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/* VGIC maintenance interrupt */ |
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
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}; |
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timer { |
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compatible = "arm,armv8-timer"; |
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/* Secure, non-secure, virtual, and hypervisor */ |
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; |
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}; |
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pmu { |
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compatible = "arm,armv8-pmuv3"; |
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interrupts = <GIC_PPI 0x7 IRQ_TYPE_LEVEL_HIGH>; |
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}; |
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soc { |
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compatible = "simple-bus"; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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ranges; |
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uart0: serial@20150000 { |
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compatible = "snps,dw-apb-uart"; |
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reg = <0x0 0x20150000 0x0 0x100>; |
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interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; |
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clock-frequency = <24000000>; |
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reg-shift = <2>; |
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reg-io-width = <4>; |
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status = "disabled"; |
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}; |
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uart1: serial@20160000 { |
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compatible = "snps,dw-apb-uart"; |
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reg = <0x0 0x20160000 0x0 0x100>; |
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
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clock-frequency = <24000000>; |
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reg-shift = <2>; |
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reg-io-width = <4>; |
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status = "disabled"; |
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}; |
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uart2: serial@20170000 { |
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compatible = "snps,dw-apb-uart"; |
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reg = <0x0 0x20170000 0x0 0x100>; |
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interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; |
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clock-frequency = <24000000>; |
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reg-shift = <2>; |
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reg-io-width = <4>; |
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status = "disabled"; |
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}; |
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uart3: serial@20180000 { |
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compatible = "snps,dw-apb-uart"; |
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reg = <0x0 0x20180000 0x0 0x100>; |
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interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; |
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clock-frequency = <24000000>; |
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reg-shift = <2>; |
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reg-io-width = <4>; |
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status = "disabled"; |
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}; |
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}; |
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};
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