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632 lines
17 KiB
632 lines
17 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* Copyright (C) 2016 Freescale Semiconductor, Inc. |
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* Copyright 2017-2018 NXP |
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* Dong Aisheng <[email protected]> |
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*/ |
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#include <dt-bindings/clock/imx8-clock.h> |
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#include <dt-bindings/firmware/imx/rsrc.h> |
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#include <dt-bindings/gpio/gpio.h> |
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#include <dt-bindings/input/input.h> |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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#include <dt-bindings/pinctrl/pads-imx8qxp.h> |
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#include <dt-bindings/thermal/thermal.h> |
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/ { |
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interrupt-parent = <&gic>; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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aliases { |
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ethernet0 = &fec1; |
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ethernet1 = &fec2; |
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gpio0 = &lsio_gpio0; |
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gpio1 = &lsio_gpio1; |
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gpio2 = &lsio_gpio2; |
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gpio3 = &lsio_gpio3; |
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gpio4 = &lsio_gpio4; |
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gpio5 = &lsio_gpio5; |
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gpio6 = &lsio_gpio6; |
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gpio7 = &lsio_gpio7; |
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i2c0 = &adma_i2c0; |
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i2c1 = &adma_i2c1; |
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i2c2 = &adma_i2c2; |
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i2c3 = &adma_i2c3; |
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mmc0 = &usdhc1; |
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mmc1 = &usdhc2; |
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mmc2 = &usdhc3; |
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mu0 = &lsio_mu0; |
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mu1 = &lsio_mu1; |
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mu2 = &lsio_mu2; |
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mu3 = &lsio_mu3; |
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mu4 = &lsio_mu4; |
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serial0 = &adma_lpuart0; |
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serial1 = &adma_lpuart1; |
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serial2 = &adma_lpuart2; |
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serial3 = &adma_lpuart3; |
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}; |
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cpus { |
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#address-cells = <2>; |
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#size-cells = <0>; |
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/* We have 1 clusters with 4 Cortex-A35 cores */ |
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A35_0: cpu@0 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a35"; |
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reg = <0x0 0x0>; |
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enable-method = "psci"; |
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next-level-cache = <&A35_L2>; |
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clocks = <&clk IMX_A35_CLK>; |
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operating-points-v2 = <&a35_opp_table>; |
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#cooling-cells = <2>; |
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}; |
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A35_1: cpu@1 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a35"; |
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reg = <0x0 0x1>; |
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enable-method = "psci"; |
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next-level-cache = <&A35_L2>; |
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clocks = <&clk IMX_A35_CLK>; |
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operating-points-v2 = <&a35_opp_table>; |
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#cooling-cells = <2>; |
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}; |
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A35_2: cpu@2 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a35"; |
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reg = <0x0 0x2>; |
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enable-method = "psci"; |
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next-level-cache = <&A35_L2>; |
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clocks = <&clk IMX_A35_CLK>; |
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operating-points-v2 = <&a35_opp_table>; |
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#cooling-cells = <2>; |
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}; |
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A35_3: cpu@3 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a35"; |
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reg = <0x0 0x3>; |
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enable-method = "psci"; |
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next-level-cache = <&A35_L2>; |
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clocks = <&clk IMX_A35_CLK>; |
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operating-points-v2 = <&a35_opp_table>; |
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#cooling-cells = <2>; |
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}; |
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A35_L2: l2-cache0 { |
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compatible = "cache"; |
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}; |
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}; |
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a35_opp_table: opp-table { |
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compatible = "operating-points-v2"; |
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opp-shared; |
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opp-900000000 { |
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opp-hz = /bits/ 64 <900000000>; |
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opp-microvolt = <1000000>; |
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clock-latency-ns = <150000>; |
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}; |
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opp-1200000000 { |
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opp-hz = /bits/ 64 <1200000000>; |
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opp-microvolt = <1100000>; |
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clock-latency-ns = <150000>; |
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opp-suspend; |
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}; |
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}; |
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gic: interrupt-controller@51a00000 { |
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compatible = "arm,gic-v3"; |
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reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ |
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<0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ |
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#interrupt-cells = <3>; |
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interrupt-controller; |
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
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}; |
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reserved-memory { |
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#address-cells = <2>; |
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#size-cells = <2>; |
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ranges; |
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dsp_reserved: dsp@92400000 { |
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reg = <0 0x92400000 0 0x2000000>; |
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no-map; |
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}; |
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}; |
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pmu { |
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compatible = "arm,armv8-pmuv3"; |
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; |
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}; |
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psci { |
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compatible = "arm,psci-1.0"; |
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method = "smc"; |
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}; |
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scu { |
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compatible = "fsl,imx-scu"; |
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mbox-names = "tx0", |
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"rx0", |
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"gip3"; |
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mboxes = <&lsio_mu1 0 0 |
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&lsio_mu1 1 0 |
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&lsio_mu1 3 3>; |
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clk: clock-controller { |
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compatible = "fsl,imx8qxp-clk"; |
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#clock-cells = <1>; |
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clocks = <&xtal32k &xtal24m>; |
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clock-names = "xtal_32KHz", "xtal_24Mhz"; |
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}; |
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iomuxc: pinctrl { |
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compatible = "fsl,imx8qxp-iomuxc"; |
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}; |
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ocotp: imx8qx-ocotp { |
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compatible = "fsl,imx8qxp-scu-ocotp"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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}; |
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pd: imx8qx-pd { |
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compatible = "fsl,imx8qxp-scu-pd"; |
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#power-domain-cells = <1>; |
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}; |
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scu_key: scu-key { |
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compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key"; |
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linux,keycodes = <KEY_POWER>; |
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status = "disabled"; |
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}; |
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rtc: rtc { |
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compatible = "fsl,imx8qxp-sc-rtc"; |
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}; |
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watchdog { |
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compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; |
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timeout-sec = <60>; |
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}; |
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tsens: thermal-sensor { |
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compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal"; |
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#thermal-sensor-cells = <1>; |
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}; |
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}; |
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timer { |
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compatible = "arm,armv8-timer"; |
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ |
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ |
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ |
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ |
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}; |
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xtal32k: clock-xtal32k { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <32768>; |
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clock-output-names = "xtal_32KHz"; |
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}; |
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xtal24m: clock-xtal24m { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <24000000>; |
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clock-output-names = "xtal_24MHz"; |
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}; |
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adma_subsys: bus@59000000 { |
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compatible = "simple-bus"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges = <0x59000000 0x0 0x59000000 0x2000000>; |
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adma_lpcg: clock-controller@59000000 { |
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compatible = "fsl,imx8qxp-lpcg-adma"; |
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reg = <0x59000000 0x2000000>; |
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#clock-cells = <1>; |
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}; |
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adma_dsp: dsp@596e8000 { |
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compatible = "fsl,imx8qxp-dsp"; |
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reg = <0x596e8000 0x88000>; |
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clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>, |
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<&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>, |
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<&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>; |
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clock-names = "ipg", "ocram", "core"; |
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power-domains = <&pd IMX_SC_R_MU_13A>, |
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<&pd IMX_SC_R_MU_13B>, |
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<&pd IMX_SC_R_DSP>, |
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<&pd IMX_SC_R_DSP_RAM>; |
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mbox-names = "txdb0", "txdb1", |
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"rxdb0", "rxdb1"; |
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mboxes = <&lsio_mu13 2 0>, |
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<&lsio_mu13 2 1>, |
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<&lsio_mu13 3 0>, |
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<&lsio_mu13 3 1>; |
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memory-region = <&dsp_reserved>; |
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status = "disabled"; |
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}; |
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adma_lpuart0: serial@5a060000 { |
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compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; |
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reg = <0x5a060000 0x1000>; |
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interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_IPG_CLK>, |
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<&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>; |
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clock-names = "ipg", "baud"; |
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power-domains = <&pd IMX_SC_R_UART_0>; |
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status = "disabled"; |
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}; |
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adma_lpuart1: serial@5a070000 { |
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compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; |
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reg = <0x5a070000 0x1000>; |
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interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_IPG_CLK>, |
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<&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>; |
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clock-names = "ipg", "baud"; |
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power-domains = <&pd IMX_SC_R_UART_1>; |
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status = "disabled"; |
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}; |
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adma_lpuart2: serial@5a080000 { |
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compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; |
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reg = <0x5a080000 0x1000>; |
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interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_IPG_CLK>, |
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<&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>; |
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clock-names = "ipg", "baud"; |
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power-domains = <&pd IMX_SC_R_UART_2>; |
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status = "disabled"; |
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}; |
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adma_lpuart3: serial@5a090000 { |
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compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; |
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reg = <0x5a090000 0x1000>; |
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interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_IPG_CLK>, |
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<&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>; |
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clock-names = "ipg", "baud"; |
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power-domains = <&pd IMX_SC_R_UART_3>; |
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status = "disabled"; |
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}; |
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adma_i2c0: i2c@5a800000 { |
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compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; |
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reg = <0x5a800000 0x4000>; |
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interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>; |
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clock-names = "per"; |
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assigned-clocks = <&clk IMX_ADMA_I2C0_CLK>; |
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assigned-clock-rates = <24000000>; |
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power-domains = <&pd IMX_SC_R_I2C_0>; |
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status = "disabled"; |
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}; |
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adma_i2c1: i2c@5a810000 { |
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compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; |
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reg = <0x5a810000 0x4000>; |
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interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>; |
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clock-names = "per"; |
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assigned-clocks = <&clk IMX_ADMA_I2C1_CLK>; |
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assigned-clock-rates = <24000000>; |
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power-domains = <&pd IMX_SC_R_I2C_1>; |
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status = "disabled"; |
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}; |
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adma_i2c2: i2c@5a820000 { |
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compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; |
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reg = <0x5a820000 0x4000>; |
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interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>; |
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clock-names = "per"; |
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assigned-clocks = <&clk IMX_ADMA_I2C2_CLK>; |
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assigned-clock-rates = <24000000>; |
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power-domains = <&pd IMX_SC_R_I2C_2>; |
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status = "disabled"; |
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}; |
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adma_i2c3: i2c@5a830000 { |
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compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; |
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reg = <0x5a830000 0x4000>; |
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interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>; |
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clock-names = "per"; |
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assigned-clocks = <&clk IMX_ADMA_I2C3_CLK>; |
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assigned-clock-rates = <24000000>; |
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power-domains = <&pd IMX_SC_R_I2C_3>; |
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status = "disabled"; |
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}; |
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}; |
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conn_subsys: bus@5b000000 { |
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compatible = "simple-bus"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges = <0x5b000000 0x0 0x5b000000 0x1000000>; |
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conn_lpcg: clock-controller@5b200000 { |
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compatible = "fsl,imx8qxp-lpcg-conn"; |
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reg = <0x5b200000 0xb0000>; |
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#clock-cells = <1>; |
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}; |
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usdhc1: mmc@5b010000 { |
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compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; |
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interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; |
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reg = <0x5b010000 0x10000>; |
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clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>, |
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<&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>, |
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<&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>; |
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clock-names = "ipg", "per", "ahb"; |
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power-domains = <&pd IMX_SC_R_SDHC_0>; |
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status = "disabled"; |
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}; |
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usdhc2: mmc@5b020000 { |
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compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; |
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interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; |
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reg = <0x5b020000 0x10000>; |
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clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>, |
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<&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>, |
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<&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>; |
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clock-names = "ipg", "per", "ahb"; |
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power-domains = <&pd IMX_SC_R_SDHC_1>; |
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fsl,tuning-start-tap = <20>; |
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fsl,tuning-step= <2>; |
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status = "disabled"; |
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}; |
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usdhc3: mmc@5b030000 { |
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compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; |
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interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; |
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reg = <0x5b030000 0x10000>; |
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clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>, |
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<&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>, |
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<&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>; |
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clock-names = "ipg", "per", "ahb"; |
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power-domains = <&pd IMX_SC_R_SDHC_2>; |
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status = "disabled"; |
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}; |
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fec1: ethernet@5b040000 { |
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compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; |
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reg = <0x5b040000 0x10000>; |
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interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>, |
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<&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>, |
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<&conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK>, |
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<&conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK>; |
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clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; |
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fsl,num-tx-queues=<3>; |
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fsl,num-rx-queues=<3>; |
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power-domains = <&pd IMX_SC_R_ENET_0>; |
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status = "disabled"; |
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}; |
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fec2: ethernet@5b050000 { |
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compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; |
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reg = <0x5b050000 0x10000>; |
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interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>, |
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<&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>, |
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<&conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK>, |
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<&conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK>; |
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clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; |
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fsl,num-tx-queues=<3>; |
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fsl,num-rx-queues=<3>; |
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power-domains = <&pd IMX_SC_R_ENET_1>; |
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status = "disabled"; |
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}; |
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}; |
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ddr_subsyss: bus@5c000000 { |
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compatible = "simple-bus"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges = <0x5c000000 0x0 0x5c000000 0x1000000>; |
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ddr-pmu@5c020000 { |
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compatible = "fsl,imx8-ddr-pmu"; |
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reg = <0x5c020000 0x10000>; |
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interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; |
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}; |
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}; |
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lsio_subsys: bus@5d000000 { |
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compatible = "simple-bus"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges = <0x5d000000 0x0 0x5d000000 0x1000000>; |
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lsio_gpio0: gpio@5d080000 { |
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compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; |
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reg = <0x5d080000 0x10000>; |
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interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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power-domains = <&pd IMX_SC_R_GPIO_0>; |
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}; |
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lsio_gpio1: gpio@5d090000 { |
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compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; |
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reg = <0x5d090000 0x10000>; |
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interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; |
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gpio-controller; |
|
#gpio-cells = <2>; |
|
interrupt-controller; |
|
#interrupt-cells = <2>; |
|
power-domains = <&pd IMX_SC_R_GPIO_1>; |
|
}; |
|
|
|
lsio_gpio2: gpio@5d0a0000 { |
|
compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; |
|
reg = <0x5d0a0000 0x10000>; |
|
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; |
|
gpio-controller; |
|
#gpio-cells = <2>; |
|
interrupt-controller; |
|
#interrupt-cells = <2>; |
|
power-domains = <&pd IMX_SC_R_GPIO_2>; |
|
}; |
|
|
|
lsio_gpio3: gpio@5d0b0000 { |
|
compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; |
|
reg = <0x5d0b0000 0x10000>; |
|
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; |
|
gpio-controller; |
|
#gpio-cells = <2>; |
|
interrupt-controller; |
|
#interrupt-cells = <2>; |
|
power-domains = <&pd IMX_SC_R_GPIO_3>; |
|
}; |
|
|
|
lsio_gpio4: gpio@5d0c0000 { |
|
compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; |
|
reg = <0x5d0c0000 0x10000>; |
|
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; |
|
gpio-controller; |
|
#gpio-cells = <2>; |
|
interrupt-controller; |
|
#interrupt-cells = <2>; |
|
power-domains = <&pd IMX_SC_R_GPIO_4>; |
|
}; |
|
|
|
lsio_gpio5: gpio@5d0d0000 { |
|
compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; |
|
reg = <0x5d0d0000 0x10000>; |
|
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; |
|
gpio-controller; |
|
#gpio-cells = <2>; |
|
interrupt-controller; |
|
#interrupt-cells = <2>; |
|
power-domains = <&pd IMX_SC_R_GPIO_5>; |
|
}; |
|
|
|
lsio_gpio6: gpio@5d0e0000 { |
|
compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; |
|
reg = <0x5d0e0000 0x10000>; |
|
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; |
|
gpio-controller; |
|
#gpio-cells = <2>; |
|
interrupt-controller; |
|
#interrupt-cells = <2>; |
|
power-domains = <&pd IMX_SC_R_GPIO_6>; |
|
}; |
|
|
|
lsio_gpio7: gpio@5d0f0000 { |
|
compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; |
|
reg = <0x5d0f0000 0x10000>; |
|
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; |
|
gpio-controller; |
|
#gpio-cells = <2>; |
|
interrupt-controller; |
|
#interrupt-cells = <2>; |
|
power-domains = <&pd IMX_SC_R_GPIO_7>; |
|
}; |
|
|
|
lsio_mu0: mailbox@5d1b0000 { |
|
compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; |
|
reg = <0x5d1b0000 0x10000>; |
|
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; |
|
#mbox-cells = <2>; |
|
status = "disabled"; |
|
}; |
|
|
|
lsio_mu1: mailbox@5d1c0000 { |
|
compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; |
|
reg = <0x5d1c0000 0x10000>; |
|
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; |
|
#mbox-cells = <2>; |
|
}; |
|
|
|
lsio_mu2: mailbox@5d1d0000 { |
|
compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; |
|
reg = <0x5d1d0000 0x10000>; |
|
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; |
|
#mbox-cells = <2>; |
|
status = "disabled"; |
|
}; |
|
|
|
lsio_mu3: mailbox@5d1e0000 { |
|
compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; |
|
reg = <0x5d1e0000 0x10000>; |
|
interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; |
|
#mbox-cells = <2>; |
|
status = "disabled"; |
|
}; |
|
|
|
lsio_mu4: mailbox@5d1f0000 { |
|
compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; |
|
reg = <0x5d1f0000 0x10000>; |
|
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; |
|
#mbox-cells = <2>; |
|
status = "disabled"; |
|
}; |
|
|
|
lsio_mu13: mailbox@5d280000 { |
|
compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; |
|
reg = <0x5d280000 0x10000>; |
|
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; |
|
#mbox-cells = <2>; |
|
power-domains = <&pd IMX_SC_R_MU_13A>; |
|
}; |
|
|
|
lsio_lpcg: clock-controller@5d400000 { |
|
compatible = "fsl,imx8qxp-lpcg-lsio"; |
|
reg = <0x5d400000 0x400000>; |
|
#clock-cells = <1>; |
|
}; |
|
}; |
|
|
|
thermal_zones: thermal-zones { |
|
cpu-thermal0 { |
|
polling-delay-passive = <250>; |
|
polling-delay = <2000>; |
|
thermal-sensors = <&tsens IMX_SC_R_SYSTEM>; |
|
|
|
trips { |
|
cpu_alert0: trip0 { |
|
temperature = <107000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu_crit0: trip1 { |
|
temperature = <127000>; |
|
hysteresis = <2000>; |
|
type = "critical"; |
|
}; |
|
}; |
|
|
|
cooling-maps { |
|
map0 { |
|
trip = <&cpu_alert0>; |
|
cooling-device = |
|
<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
};
|
|
|