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128 lines
3.6 KiB
128 lines
3.6 KiB
// SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
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/* |
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* Copyright 2019-2020 NXP |
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*/ |
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/dts-v1/; |
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#include <dt-bindings/usb/pd.h> |
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#include "imx8mm-evk.dtsi" |
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/ { |
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model = "FSL i.MX8MM EVK board"; |
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compatible = "fsl,imx8mm-evk", "fsl,imx8mm"; |
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aliases { |
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spi0 = &flexspi; |
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}; |
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}; |
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&ddrc { |
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operating-points-v2 = <&ddrc_opp_table>; |
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ddrc_opp_table: opp-table { |
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compatible = "operating-points-v2"; |
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opp-25M { |
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opp-hz = /bits/ 64 <25000000>; |
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}; |
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opp-100M { |
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opp-hz = /bits/ 64 <100000000>; |
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}; |
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opp-750M { |
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opp-hz = /bits/ 64 <750000000>; |
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}; |
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}; |
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}; |
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&flexspi { |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_flexspi>; |
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status = "okay"; |
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flash@0 { |
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reg = <0>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "jedec,spi-nor"; |
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spi-max-frequency = <80000000>; |
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spi-tx-bus-width = <4>; |
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spi-rx-bus-width = <4>; |
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}; |
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}; |
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&usdhc3 { |
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assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; |
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assigned-clock-rates = <400000000>; |
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pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
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pinctrl-0 = <&pinctrl_usdhc3>; |
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pinctrl-1 = <&pinctrl_usdhc3_100mhz>; |
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pinctrl-2 = <&pinctrl_usdhc3_200mhz>; |
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bus-width = <8>; |
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non-removable; |
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status = "okay"; |
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}; |
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&iomuxc { |
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pinctrl_flexspi: flexspigrp { |
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fsl,pins = < |
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MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 |
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MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 |
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MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 |
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MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 |
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MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 |
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MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 |
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>; |
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}; |
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pinctrl_usdhc3: usdhc3grp { |
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fsl,pins = < |
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MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 |
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MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 |
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MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 |
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MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 |
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MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 |
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MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 |
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MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 |
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MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 |
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MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 |
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MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 |
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MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 |
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MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 |
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>; |
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}; |
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pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { |
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fsl,pins = < |
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MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 |
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MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 |
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MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 |
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MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 |
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MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 |
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MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 |
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MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 |
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MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 |
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MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 |
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MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 |
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MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 |
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>; |
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}; |
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pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { |
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fsl,pins = < |
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MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 |
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MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 |
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MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 |
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MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 |
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MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 |
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MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 |
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MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 |
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MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 |
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MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 |
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MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 |
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MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 |
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>; |
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}; |
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};
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