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569 lines
15 KiB
569 lines
15 KiB
// SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
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/* |
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* Device Tree Include file for NXP Layerscape-1012A family SoC. |
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* |
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* Copyright 2016 Freescale Semiconductor, Inc. |
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* Copyright 2019-2020 NXP |
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* |
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*/ |
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#include <dt-bindings/clock/fsl,qoriq-clockgen.h> |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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#include <dt-bindings/thermal/thermal.h> |
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/ { |
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compatible = "fsl,ls1012a"; |
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interrupt-parent = <&gic>; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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aliases { |
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crypto = &crypto; |
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rtc1 = &ftm_alarm0; |
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rtic-a = &rtic_a; |
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rtic-b = &rtic_b; |
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rtic-c = &rtic_c; |
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rtic-d = &rtic_d; |
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sec-mon = &sec_mon; |
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}; |
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cpus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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cpu0: cpu@0 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a53"; |
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reg = <0x0>; |
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clocks = <&clockgen QORIQ_CLK_CMUX 0>; |
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#cooling-cells = <2>; |
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cpu-idle-states = <&CPU_PH20>; |
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}; |
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}; |
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idle-states { |
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/* |
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* PSCI node is not added default, U-boot will add missing |
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* parts if it determines to use PSCI. |
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*/ |
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entry-method = "psci"; |
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CPU_PH20: cpu-ph20 { |
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compatible = "arm,idle-state"; |
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idle-state-name = "PH20"; |
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arm,psci-suspend-param = <0x0>; |
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entry-latency-us = <1000>; |
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exit-latency-us = <1000>; |
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min-residency-us = <3000>; |
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}; |
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}; |
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sysclk: sysclk { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <125000000>; |
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clock-output-names = "sysclk"; |
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}; |
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coreclk: coreclk { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <100000000>; |
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clock-output-names = "coreclk"; |
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}; |
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timer { |
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compatible = "arm,armv8-timer"; |
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interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */ |
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<1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */ |
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<1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */ |
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<1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */ |
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}; |
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pmu { |
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compatible = "arm,armv8-pmuv3"; |
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interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; |
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}; |
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gic: interrupt-controller@1400000 { |
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compatible = "arm,gic-400"; |
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#interrupt-cells = <3>; |
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interrupt-controller; |
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reg = <0x0 0x1401000 0 0x1000>, /* GICD */ |
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<0x0 0x1402000 0 0x2000>, /* GICC */ |
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<0x0 0x1404000 0 0x2000>, /* GICH */ |
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<0x0 0x1406000 0 0x2000>; /* GICV */ |
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interrupts = <1 9 IRQ_TYPE_LEVEL_LOW>; |
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}; |
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reboot { |
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compatible = "syscon-reboot"; |
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regmap = <&dcfg>; |
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offset = <0xb0>; |
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mask = <0x02>; |
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}; |
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thermal-zones { |
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cpu_thermal: cpu-thermal { |
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polling-delay-passive = <1000>; |
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polling-delay = <5000>; |
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thermal-sensors = <&tmu 0>; |
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trips { |
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cpu_alert: cpu-alert { |
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temperature = <85000>; |
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hysteresis = <2000>; |
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type = "passive"; |
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}; |
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cpu_crit: cpu-crit { |
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temperature = <95000>; |
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hysteresis = <2000>; |
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type = "critical"; |
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}; |
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}; |
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cooling-maps { |
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map0 { |
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trip = <&cpu_alert>; |
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cooling-device = |
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<&cpu0 THERMAL_NO_LIMIT |
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THERMAL_NO_LIMIT>; |
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}; |
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}; |
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}; |
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}; |
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soc { |
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compatible = "simple-bus"; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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ranges; |
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qspi: spi@1550000 { |
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compatible = "fsl,ls1021a-qspi"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <0x0 0x1550000 0x0 0x10000>, |
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<0x0 0x40000000 0x0 0x10000000>; |
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reg-names = "QuadSPI", "QuadSPI-memory"; |
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interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; |
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clock-names = "qspi_en", "qspi"; |
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clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
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QORIQ_CLK_PLL_DIV(1)>, |
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<&clockgen QORIQ_CLK_PLATFORM_PLL |
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QORIQ_CLK_PLL_DIV(1)>; |
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status = "disabled"; |
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}; |
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esdhc0: esdhc@1560000 { |
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compatible = "fsl,ls1012a-esdhc", "fsl,esdhc"; |
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reg = <0x0 0x1560000 0x0 0x10000>; |
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interrupts = <0 62 0x4>; |
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clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
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QORIQ_CLK_PLL_DIV(1)>; |
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voltage-ranges = <1800 1800 3300 3300>; |
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sdhci,auto-cmd12; |
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big-endian; |
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bus-width = <4>; |
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status = "disabled"; |
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}; |
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scfg: scfg@1570000 { |
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compatible = "fsl,ls1012a-scfg", "syscon"; |
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reg = <0x0 0x1570000 0x0 0x10000>; |
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big-endian; |
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}; |
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esdhc1: esdhc@1580000 { |
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compatible = "fsl,ls1012a-esdhc", "fsl,esdhc"; |
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reg = <0x0 0x1580000 0x0 0x10000>; |
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interrupts = <0 65 0x4>; |
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clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
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QORIQ_CLK_PLL_DIV(1)>; |
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voltage-ranges = <1800 1800 3300 3300>; |
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sdhci,auto-cmd12; |
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big-endian; |
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broken-cd; |
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bus-width = <4>; |
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status = "disabled"; |
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}; |
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crypto: crypto@1700000 { |
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compatible = "fsl,sec-v5.4", "fsl,sec-v5.0", |
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"fsl,sec-v4.0"; |
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fsl,sec-era = <8>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges = <0x0 0x00 0x1700000 0x100000>; |
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reg = <0x00 0x1700000 0x0 0x100000>; |
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
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dma-coherent; |
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sec_jr0: jr@10000 { |
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compatible = "fsl,sec-v5.4-job-ring", |
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"fsl,sec-v5.0-job-ring", |
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"fsl,sec-v4.0-job-ring"; |
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reg = <0x10000 0x10000>; |
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interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; |
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}; |
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sec_jr1: jr@20000 { |
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compatible = "fsl,sec-v5.4-job-ring", |
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"fsl,sec-v5.0-job-ring", |
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"fsl,sec-v4.0-job-ring"; |
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reg = <0x20000 0x10000>; |
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
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}; |
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sec_jr2: jr@30000 { |
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compatible = "fsl,sec-v5.4-job-ring", |
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"fsl,sec-v5.0-job-ring", |
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"fsl,sec-v4.0-job-ring"; |
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reg = <0x30000 0x10000>; |
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interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
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}; |
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sec_jr3: jr@40000 { |
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compatible = "fsl,sec-v5.4-job-ring", |
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"fsl,sec-v5.0-job-ring", |
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"fsl,sec-v4.0-job-ring"; |
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reg = <0x40000 0x10000>; |
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
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}; |
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rtic@60000 { |
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compatible = "fsl,sec-v5.4-rtic", |
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"fsl,sec-v5.0-rtic", |
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"fsl,sec-v4.0-rtic"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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reg = <0x60000 0x100 0x60e00 0x18>; |
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ranges = <0x0 0x60100 0x500>; |
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rtic_a: rtic-a@0 { |
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compatible = "fsl,sec-v5.4-rtic-memory", |
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"fsl,sec-v5.0-rtic-memory", |
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"fsl,sec-v4.0-rtic-memory"; |
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reg = <0x00 0x20 0x100 0x100>; |
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}; |
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rtic_b: rtic-b@20 { |
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compatible = "fsl,sec-v5.4-rtic-memory", |
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"fsl,sec-v5.0-rtic-memory", |
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"fsl,sec-v4.0-rtic-memory"; |
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reg = <0x20 0x20 0x200 0x100>; |
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}; |
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rtic_c: rtic-c@40 { |
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compatible = "fsl,sec-v5.4-rtic-memory", |
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"fsl,sec-v5.0-rtic-memory", |
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"fsl,sec-v4.0-rtic-memory"; |
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reg = <0x40 0x20 0x300 0x100>; |
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}; |
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rtic_d: rtic-d@60 { |
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compatible = "fsl,sec-v5.4-rtic-memory", |
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"fsl,sec-v5.0-rtic-memory", |
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"fsl,sec-v4.0-rtic-memory"; |
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reg = <0x60 0x20 0x400 0x100>; |
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}; |
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}; |
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}; |
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sec_mon: sec_mon@1e90000 { |
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compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon", |
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"fsl,sec-v4.0-mon"; |
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reg = <0x0 0x1e90000 0x0 0x10000>; |
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; |
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}; |
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dcfg: dcfg@1ee0000 { |
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compatible = "fsl,ls1012a-dcfg", |
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"syscon"; |
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reg = <0x0 0x1ee0000 0x0 0x10000>; |
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big-endian; |
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}; |
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clockgen: clocking@1ee1000 { |
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compatible = "fsl,ls1012a-clockgen"; |
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reg = <0x0 0x1ee1000 0x0 0x1000>; |
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#clock-cells = <2>; |
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clocks = <&sysclk &coreclk>; |
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clock-names = "sysclk", "coreclk"; |
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}; |
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tmu: tmu@1f00000 { |
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compatible = "fsl,qoriq-tmu"; |
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reg = <0x0 0x1f00000 0x0 0x10000>; |
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interrupts = <0 33 0x4>; |
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fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x60062>; |
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fsl,tmu-calibration = <0x00000000 0x00000025 |
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0x00000001 0x0000002c |
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0x00000002 0x00000032 |
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0x00000003 0x00000039 |
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0x00000004 0x0000003f |
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0x00000005 0x00000046 |
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0x00000006 0x0000004c |
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0x00000007 0x00000053 |
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0x00000008 0x00000059 |
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0x00000009 0x0000005f |
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0x0000000a 0x00000066 |
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0x0000000b 0x0000006c |
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0x00010000 0x00000026 |
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0x00010001 0x0000002d |
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0x00010002 0x00000035 |
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0x00010003 0x0000003d |
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0x00010004 0x00000045 |
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0x00010005 0x0000004d |
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0x00010006 0x00000055 |
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0x00010007 0x0000005d |
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0x00010008 0x00000065 |
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0x00010009 0x0000006d |
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0x00020000 0x00000026 |
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0x00020001 0x00000030 |
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0x00020002 0x0000003a |
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0x00020003 0x00000044 |
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0x00020004 0x0000004e |
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0x00020005 0x00000059 |
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0x00020006 0x00000063 |
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0x00030000 0x00000014 |
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0x00030001 0x00000021 |
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0x00030002 0x0000002e |
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0x00030003 0x0000003a |
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0x00030004 0x00000047 |
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0x00030005 0x00000053 |
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0x00030006 0x00000060>; |
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big-endian; |
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#thermal-sensor-cells = <1>; |
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}; |
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i2c0: i2c@2180000 { |
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compatible = "fsl,vf610-i2c"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <0x0 0x2180000 0x0 0x10000>; |
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interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
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QORIQ_CLK_PLL_DIV(4)>; |
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status = "disabled"; |
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}; |
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i2c1: i2c@2190000 { |
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compatible = "fsl,vf610-i2c"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <0x0 0x2190000 0x0 0x10000>; |
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interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
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QORIQ_CLK_PLL_DIV(4)>; |
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status = "disabled"; |
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}; |
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dspi: spi@2100000 { |
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compatible = "fsl,ls1012a-dspi", "fsl,ls1021a-v1.0-dspi"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <0x0 0x2100000 0x0 0x10000>; |
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interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>; |
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clock-names = "dspi"; |
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clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
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QORIQ_CLK_PLL_DIV(1)>; |
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spi-num-chipselects = <5>; |
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big-endian; |
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status = "disabled"; |
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}; |
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duart0: serial@21c0500 { |
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compatible = "fsl,ns16550", "ns16550a"; |
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reg = <0x00 0x21c0500 0x0 0x100>; |
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interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
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QORIQ_CLK_PLL_DIV(1)>; |
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status = "disabled"; |
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}; |
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duart1: serial@21c0600 { |
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compatible = "fsl,ns16550", "ns16550a"; |
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reg = <0x00 0x21c0600 0x0 0x100>; |
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interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
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QORIQ_CLK_PLL_DIV(1)>; |
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status = "disabled"; |
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}; |
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gpio0: gpio@2300000 { |
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compatible = "fsl,qoriq-gpio"; |
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reg = <0x0 0x2300000 0x0 0x10000>; |
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interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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}; |
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gpio1: gpio@2310000 { |
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compatible = "fsl,qoriq-gpio"; |
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reg = <0x0 0x2310000 0x0 0x10000>; |
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interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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}; |
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wdog0: watchdog@2ad0000 { |
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compatible = "fsl,ls1012a-wdt", |
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"fsl,imx21-wdt"; |
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reg = <0x0 0x2ad0000 0x0 0x10000>; |
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interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(1)>; |
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big-endian; |
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}; |
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sai1: sai@2b50000 { |
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#sound-dai-cells = <0>; |
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compatible = "fsl,vf610-sai"; |
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reg = <0x0 0x2b50000 0x0 0x10000>; |
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interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
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QORIQ_CLK_PLL_DIV(4)>, |
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<&clockgen QORIQ_CLK_PLATFORM_PLL |
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QORIQ_CLK_PLL_DIV(4)>, |
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<&clockgen QORIQ_CLK_PLATFORM_PLL |
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QORIQ_CLK_PLL_DIV(4)>, |
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<&clockgen QORIQ_CLK_PLATFORM_PLL |
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QORIQ_CLK_PLL_DIV(4)>; |
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clock-names = "bus", "mclk1", "mclk2", "mclk3"; |
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dma-names = "tx", "rx"; |
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dmas = <&edma0 1 47>, |
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<&edma0 1 46>; |
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status = "disabled"; |
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}; |
|
|
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sai2: sai@2b60000 { |
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#sound-dai-cells = <0>; |
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compatible = "fsl,vf610-sai"; |
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reg = <0x0 0x2b60000 0x0 0x10000>; |
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interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
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QORIQ_CLK_PLL_DIV(4)>, |
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<&clockgen QORIQ_CLK_PLATFORM_PLL |
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QORIQ_CLK_PLL_DIV(4)>, |
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<&clockgen QORIQ_CLK_PLATFORM_PLL |
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QORIQ_CLK_PLL_DIV(4)>, |
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<&clockgen QORIQ_CLK_PLATFORM_PLL |
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QORIQ_CLK_PLL_DIV(4)>; |
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clock-names = "bus", "mclk1", "mclk2", "mclk3"; |
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dma-names = "tx", "rx"; |
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dmas = <&edma0 1 45>, |
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<&edma0 1 44>; |
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status = "disabled"; |
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}; |
|
|
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edma0: edma@2c00000 { |
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#dma-cells = <2>; |
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compatible = "fsl,vf610-edma"; |
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reg = <0x0 0x2c00000 0x0 0x10000>, |
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<0x0 0x2c10000 0x0 0x10000>, |
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<0x0 0x2c20000 0x0 0x10000>; |
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interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>, |
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<0 103 IRQ_TYPE_LEVEL_HIGH>; |
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interrupt-names = "edma-tx", "edma-err"; |
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dma-channels = <32>; |
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big-endian; |
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clock-names = "dmamux0", "dmamux1"; |
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clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
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QORIQ_CLK_PLL_DIV(4)>, |
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<&clockgen QORIQ_CLK_PLATFORM_PLL |
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QORIQ_CLK_PLL_DIV(4)>; |
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}; |
|
|
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usb0: usb@2f00000 { |
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compatible = "snps,dwc3"; |
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reg = <0x0 0x2f00000 0x0 0x10000>; |
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interrupts = <0 60 0x4>; |
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dr_mode = "host"; |
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snps,quirk-frame-length-adjustment = <0x20>; |
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snps,dis_rxdet_inp3_quirk; |
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snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; |
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}; |
|
|
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sata: sata@3200000 { |
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compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci"; |
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reg = <0x0 0x3200000 0x0 0x10000>, |
|
<0x0 0x20140520 0x0 0x4>; |
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reg-names = "ahci", "sata-ecc"; |
|
interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |
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QORIQ_CLK_PLL_DIV(1)>; |
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dma-coherent; |
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status = "disabled"; |
|
}; |
|
|
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usb1: usb@8600000 { |
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compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; |
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reg = <0x0 0x8600000 0x0 0x1000>; |
|
interrupts = <0 139 0x4>; |
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dr_mode = "host"; |
|
phy_type = "ulpi"; |
|
}; |
|
|
|
msi: msi-controller1@1572000 { |
|
compatible = "fsl,ls1012a-msi"; |
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reg = <0x0 0x1572000 0x0 0x8>; |
|
msi-controller; |
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interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; |
|
}; |
|
|
|
pcie1: pcie@3400000 { |
|
compatible = "fsl,ls1012a-pcie"; |
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reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ |
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0x40 0x00000000 0x0 0x00002000>; /* configuration space */ |
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reg-names = "regs", "config"; |
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interrupts = <0 118 0x4>, /* controller interrupt */ |
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<0 117 0x4>; /* PME interrupt */ |
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interrupt-names = "aer", "pme"; |
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#address-cells = <3>; |
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#size-cells = <2>; |
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device_type = "pci"; |
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num-viewport = <2>; |
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bus-range = <0x0 0xff>; |
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ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ |
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0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ |
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msi-parent = <&msi>; |
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#interrupt-cells = <1>; |
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interrupt-map-mask = <0 0 0 7>; |
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interrupt-map = <0000 0 0 1 &gic 0 110 IRQ_TYPE_LEVEL_HIGH>, |
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<0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>, |
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<0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>, |
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<0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>; |
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status = "disabled"; |
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}; |
|
|
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rcpm: power-controller@1ee2140 { |
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compatible = "fsl,ls1012a-rcpm", "fsl,qoriq-rcpm-2.1+"; |
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reg = <0x0 0x1ee2140 0x0 0x4>; |
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#fsl,rcpm-wakeup-cells = <1>; |
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}; |
|
|
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ftm_alarm0: timer@29d0000 { |
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compatible = "fsl,ls1012a-ftm-alarm"; |
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reg = <0x0 0x29d0000 0x0 0x10000>; |
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fsl,rcpm-wakeup = <&rcpm 0x20000>; |
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interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
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big-endian; |
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}; |
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}; |
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|
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firmware { |
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optee { |
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compatible = "linaro,optee-tz"; |
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method = "smc"; |
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}; |
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}; |
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};
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