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145 lines
3.4 KiB
145 lines
3.4 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* dtsi file for Cavium ThunderX2 CN99XX processor |
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* |
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* Copyright (c) 2017 Cavium Inc. |
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* Copyright (c) 2013-2016 Broadcom |
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* Author: Zi Shen Lim <[email protected]> |
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*/ |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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/ { |
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model = "Cavium ThunderX2 CN99XX"; |
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compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; |
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interrupt-parent = <&gic>; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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/* just 4 cpus now, 128 needed in full config */ |
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cpus { |
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#address-cells = <0x2>; |
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#size-cells = <0x0>; |
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cpu@0 { |
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device_type = "cpu"; |
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compatible = "cavium,thunder2", "brcm,vulcan"; |
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reg = <0x0 0x0>; |
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enable-method = "psci"; |
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}; |
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cpu@1 { |
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device_type = "cpu"; |
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compatible = "cavium,thunder2", "brcm,vulcan"; |
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reg = <0x0 0x1>; |
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enable-method = "psci"; |
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}; |
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cpu@2 { |
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device_type = "cpu"; |
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compatible = "cavium,thunder2", "brcm,vulcan"; |
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reg = <0x0 0x2>; |
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enable-method = "psci"; |
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}; |
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cpu@3 { |
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device_type = "cpu"; |
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compatible = "cavium,thunder2", "brcm,vulcan"; |
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reg = <0x0 0x3>; |
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enable-method = "psci"; |
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}; |
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}; |
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psci { |
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compatible = "arm,psci-0.2"; |
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method = "smc"; |
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}; |
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gic: interrupt-controller@400080000 { |
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compatible = "arm,gic-v3"; |
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#interrupt-cells = <3>; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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ranges; |
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interrupt-controller; |
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#redistributor-regions = <1>; |
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reg = <0x04 0x00080000 0x0 0x20000>, /* GICD */ |
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<0x04 0x01000000 0x0 0x1000000>; /* GICR */ |
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
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gicits: gic-its@40010000 { |
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compatible = "arm,gic-v3-its"; |
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msi-controller; |
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reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */ |
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}; |
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}; |
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timer { |
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compatible = "arm,armv8-timer"; |
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; |
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}; |
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pmu { |
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compatible = "brcm,vulcan-pmu", "arm,armv8-pmuv3"; |
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; /* PMU overflow */ |
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}; |
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clk125mhz: uart_clk125mhz { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <125000000>; |
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clock-output-names = "clk125mhz"; |
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}; |
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pcie@30000000 { |
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compatible = "pci-host-ecam-generic"; |
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device_type = "pci"; |
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#interrupt-cells = <1>; |
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#address-cells = <3>; |
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#size-cells = <2>; |
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/* ECAM at 0x3000_0000 - 0x4000_0000 */ |
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reg = <0x0 0x30000000 0x0 0x10000000>; |
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reg-names = "PCI ECAM"; |
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/* |
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* PCI ranges: |
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* IO no supported |
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* MEM 0x4000_0000 - 0x6000_0000 |
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* MEM64 pref 0x40_0000_0000 - 0x60_0000_0000 |
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*/ |
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ranges = |
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<0x02000000 0 0x40000000 0 0x40000000 0 0x20000000 |
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0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>; |
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bus-range = <0 0xff>; |
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interrupt-map-mask = <0 0 0 7>; |
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interrupt-map = |
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/* addr pin ic icaddr icintr */ |
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<0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH |
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0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH |
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0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH |
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0 0 0 4 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; |
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msi-parent = <&gicits>; |
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dma-coherent; |
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}; |
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soc { |
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compatible = "simple-bus"; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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ranges; |
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uart0: serial@402020000 { |
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compatible = "arm,pl011", "arm,primecell"; |
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reg = <0x04 0x02020000 0x0 0x1000>; |
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interrupt-parent = <&gic>; |
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interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&clk125mhz>; |
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clock-names = "apb_pclk"; |
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}; |
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}; |
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};
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