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715 lines
18 KiB
715 lines
18 KiB
/* |
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* BSD LICENSE |
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* |
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* Copyright(c) 2015-2017 Broadcom. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions |
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* are met: |
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* |
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* * Redistributions of source code must retain the above copyright |
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* notice, this list of conditions and the following disclaimer. |
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* * Redistributions in binary form must reproduce the above copyright |
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* notice, this list of conditions and the following disclaimer in |
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* the documentation and/or other materials provided with the |
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* distribution. |
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* * Neither the name of Broadcom nor the names of its |
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* contributors may be used to endorse or promote products derived |
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* from this software without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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*/ |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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/ { |
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compatible = "brcm,stingray"; |
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interrupt-parent = <&gic>; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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cpus { |
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#address-cells = <2>; |
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#size-cells = <0>; |
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cpu@0 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a72"; |
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reg = <0x0 0x0>; |
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enable-method = "psci"; |
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next-level-cache = <&CLUSTER0_L2>; |
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}; |
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cpu@1 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a72"; |
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reg = <0x0 0x1>; |
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enable-method = "psci"; |
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next-level-cache = <&CLUSTER0_L2>; |
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}; |
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cpu@100 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a72"; |
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reg = <0x0 0x100>; |
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enable-method = "psci"; |
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next-level-cache = <&CLUSTER1_L2>; |
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}; |
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cpu@101 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a72"; |
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reg = <0x0 0x101>; |
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enable-method = "psci"; |
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next-level-cache = <&CLUSTER1_L2>; |
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}; |
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cpu@200 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a72"; |
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reg = <0x0 0x200>; |
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enable-method = "psci"; |
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next-level-cache = <&CLUSTER2_L2>; |
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}; |
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cpu@201 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a72"; |
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reg = <0x0 0x201>; |
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enable-method = "psci"; |
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next-level-cache = <&CLUSTER2_L2>; |
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}; |
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cpu@300 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a72"; |
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reg = <0x0 0x300>; |
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enable-method = "psci"; |
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next-level-cache = <&CLUSTER3_L2>; |
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}; |
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cpu@301 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a72"; |
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reg = <0x0 0x301>; |
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enable-method = "psci"; |
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next-level-cache = <&CLUSTER3_L2>; |
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}; |
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CLUSTER0_L2: l2-cache@0 { |
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compatible = "cache"; |
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}; |
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CLUSTER1_L2: l2-cache@100 { |
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compatible = "cache"; |
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}; |
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CLUSTER2_L2: l2-cache@200 { |
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compatible = "cache"; |
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}; |
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CLUSTER3_L2: l2-cache@300 { |
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compatible = "cache"; |
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}; |
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}; |
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memory: memory@80000000 { |
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device_type = "memory"; |
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reg = <0x00000000 0x80000000 0 0x40000000>; |
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}; |
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psci { |
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compatible = "arm,psci-0.2"; |
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method = "smc"; |
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}; |
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pmu { |
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compatible = "arm,armv8-pmuv3"; |
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; |
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}; |
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timer { |
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compatible = "arm,armv8-timer"; |
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, |
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, |
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, |
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; |
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}; |
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mhb: syscon@60401000 { |
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compatible = "brcm,sr-mhb", "syscon"; |
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reg = <0 0x60401000 0 0x38c>; |
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}; |
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scr { |
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compatible = "simple-bus"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges = <0x0 0x0 0x61000000 0x05000000>; |
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ccn: ccn@0 { |
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compatible = "arm,ccn-502"; |
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reg = <0x00000000 0x900000>; |
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interrupts = <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>; |
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}; |
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gic: interrupt-controller@2c00000 { |
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compatible = "arm,gic-v3"; |
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#interrupt-cells = <3>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges; |
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interrupt-controller; |
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reg = <0x02c00000 0x010000>, /* GICD */ |
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<0x02e00000 0x600000>; /* GICR */ |
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
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gic_its: gic-its@63c20000 { |
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compatible = "arm,gic-v3-its"; |
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msi-controller; |
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#msi-cells = <1>; |
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reg = <0x02c20000 0x10000>; |
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}; |
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}; |
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smmu: mmu@3000000 { |
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compatible = "arm,mmu-500"; |
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reg = <0x03000000 0x80000>; |
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#global-interrupts = <1>; |
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interrupts = <GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 717 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 718 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 719 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 720 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 721 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 722 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 726 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 727 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 728 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 729 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 730 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 731 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 732 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 733 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 734 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 741 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 742 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 744 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 746 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 748 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 749 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 751 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 763 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>; |
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#iommu-cells = <2>; |
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}; |
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}; |
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crmu: crmu { |
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compatible = "simple-bus"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges = <0x0 0x0 0x66400000 0x100000>; |
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#include "stingray-clock.dtsi" |
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otp: otp@1c400 { |
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compatible = "brcm,ocotp-v2"; |
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reg = <0x0001c400 0x68>; |
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brcm,ocotp-size = <2048>; |
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status = "okay"; |
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}; |
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cdru: syscon@1d000 { |
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compatible = "brcm,sr-cdru", "syscon"; |
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reg = <0x0001d000 0x400>; |
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}; |
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gpio_crmu: gpio@24800 { |
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compatible = "brcm,iproc-gpio"; |
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reg = <0x00024800 0x4c>; |
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ngpios = <6>; |
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#gpio-cells = <2>; |
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gpio-controller; |
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}; |
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}; |
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#include "stingray-fs4.dtsi" |
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#include "stingray-pcie.dtsi" |
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#include "stingray-usb.dtsi" |
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hsls { |
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compatible = "simple-bus"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges = <0x0 0x0 0x68900000 0x17700000>; |
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#include "stingray-pinctrl.dtsi" |
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mdio_mux_iproc: mdio-mux@20000 { |
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compatible = "brcm,mdio-mux-iproc"; |
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reg = <0x00020000 0x250>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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mdio@0 { /* PCIe serdes */ |
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reg = <0x0>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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}; |
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mdio@3 { /* USB */ |
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reg = <0x3>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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}; |
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mdio@10 { /* RGMII */ |
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reg = <0x10>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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}; |
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}; |
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pwm: pwm@10000 { |
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compatible = "brcm,iproc-pwm"; |
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reg = <0x00010000 0x1000>; |
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clocks = <&crmu_ref25m>; |
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#pwm-cells = <3>; |
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status = "disabled"; |
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}; |
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timer0: timer@30000 { |
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compatible = "arm,sp804", "arm,primecell"; |
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reg = <0x00030000 0x1000>; |
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interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&hsls_25m_div2_clk>, |
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<&hsls_25m_div2_clk>, |
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<&hsls_div4_clk>; |
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clock-names = "timer1", "timer2", "apb_pclk"; |
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status = "disabled"; |
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}; |
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timer1: timer@40000 { |
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compatible = "arm,sp804", "arm,primecell"; |
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reg = <0x00040000 0x1000>; |
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interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&hsls_25m_div2_clk>, |
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<&hsls_25m_div2_clk>, |
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<&hsls_div4_clk>; |
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clock-names = "timer1", "timer2", "apb_pclk"; |
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}; |
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timer2: timer@50000 { |
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compatible = "arm,sp804", "arm,primecell"; |
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reg = <0x00050000 0x1000>; |
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interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&hsls_25m_div2_clk>, |
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<&hsls_25m_div2_clk>, |
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<&hsls_div4_clk>; |
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clock-names = "timer1", "timer2", "apb_pclk"; |
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status = "disabled"; |
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}; |
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timer3: timer@60000 { |
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compatible = "arm,sp804", "arm,primecell"; |
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reg = <0x00060000 0x1000>; |
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interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&hsls_25m_div2_clk>, |
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<&hsls_25m_div2_clk>, |
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<&hsls_div4_clk>; |
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clock-names = "timer1", "timer2", "apb_pclk"; |
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status = "disabled"; |
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}; |
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timer4: timer@70000 { |
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compatible = "arm,sp804", "arm,primecell"; |
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reg = <0x00070000 0x1000>; |
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interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&hsls_25m_div2_clk>, |
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<&hsls_25m_div2_clk>, |
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<&hsls_div4_clk>; |
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clock-names = "timer1", "timer2", "apb_pclk"; |
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status = "disabled"; |
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}; |
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timer5: timer@80000 { |
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compatible = "arm,sp804", "arm,primecell"; |
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reg = <0x00080000 0x1000>; |
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&hsls_25m_div2_clk>, |
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<&hsls_25m_div2_clk>, |
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<&hsls_div4_clk>; |
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clock-names = "timer1", "timer2", "apb_pclk"; |
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status = "disabled"; |
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}; |
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timer6: timer@90000 { |
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compatible = "arm,sp804", "arm,primecell"; |
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reg = <0x00090000 0x1000>; |
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interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&hsls_25m_div2_clk>, |
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<&hsls_25m_div2_clk>, |
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<&hsls_div4_clk>; |
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clock-names = "timer1", "timer2", "apb_pclk"; |
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status = "disabled"; |
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}; |
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timer7: timer@a0000 { |
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compatible = "arm,sp804", "arm,primecell"; |
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reg = <0x000a0000 0x1000>; |
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interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&hsls_25m_div2_clk>, |
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<&hsls_25m_div2_clk>, |
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<&hsls_div4_clk>; |
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clock-names = "timer1", "timer2", "apb_pclk"; |
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status = "disabled"; |
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}; |
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i2c0: i2c@b0000 { |
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compatible = "brcm,iproc-i2c"; |
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reg = <0x000b0000 0x100>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; |
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clock-frequency = <100000>; |
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status = "disabled"; |
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}; |
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wdt0: watchdog@c0000 { |
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compatible = "arm,sp805", "arm,primecell"; |
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reg = <0x000c0000 0x1000>; |
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interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&hsls_25m_div2_clk>, <&hsls_div4_clk>; |
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clock-names = "wdog_clk", "apb_pclk"; |
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timeout-sec = <60>; |
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}; |
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gpio_hsls: gpio@d0000 { |
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compatible = "brcm,iproc-gpio"; |
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reg = <0x000d0000 0x864>; |
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ngpios = <151>; |
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#gpio-cells = <2>; |
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gpio-controller; |
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interrupt-controller; |
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interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; |
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gpio-ranges = <&pinmux 0 0 16>, |
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<&pinmux 16 71 2>, |
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<&pinmux 18 131 8>, |
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<&pinmux 26 83 6>, |
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<&pinmux 32 123 4>, |
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<&pinmux 36 43 24>, |
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<&pinmux 60 89 2>, |
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<&pinmux 62 73 4>, |
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<&pinmux 66 95 28>, |
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<&pinmux 94 127 4>, |
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<&pinmux 98 139 10>, |
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<&pinmux 108 16 27>, |
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<&pinmux 135 77 6>, |
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<&pinmux 141 67 4>, |
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<&pinmux 145 149 6>; |
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}; |
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i2c1: i2c@e0000 { |
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compatible = "brcm,iproc-i2c"; |
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reg = <0x000e0000 0x100>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; |
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clock-frequency = <100000>; |
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status = "disabled"; |
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}; |
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uart0: uart@100000 { |
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device_type = "serial"; |
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compatible = "snps,dw-apb-uart"; |
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reg = <0x00100000 0x1000>; |
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reg-shift = <2>; |
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clock-frequency = <25000000>; |
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interrupt-parent = <&gic>; |
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interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; |
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status = "disabled"; |
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}; |
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uart1: uart@110000 { |
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device_type = "serial"; |
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compatible = "snps,dw-apb-uart"; |
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reg = <0x00110000 0x1000>; |
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reg-shift = <2>; |
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clock-frequency = <25000000>; |
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interrupt-parent = <&gic>; |
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interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; |
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status = "disabled"; |
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}; |
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uart2: uart@120000 { |
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device_type = "serial"; |
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compatible = "snps,dw-apb-uart"; |
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reg = <0x00120000 0x1000>; |
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reg-shift = <2>; |
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clock-frequency = <25000000>; |
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interrupt-parent = <&gic>; |
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interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; |
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status = "disabled"; |
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}; |
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uart3: uart@130000 { |
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device_type = "serial"; |
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compatible = "snps,dw-apb-uart"; |
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reg = <0x00130000 0x1000>; |
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reg-shift = <2>; |
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clock-frequency = <25000000>; |
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interrupt-parent = <&gic>; |
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interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; |
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status = "disabled"; |
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}; |
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ssp0: spi@180000 { |
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compatible = "arm,pl022", "arm,primecell"; |
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reg = <0x00180000 0x1000>; |
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interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&hsls_div2_clk>, <&hsls_div2_clk>; |
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clock-names = "spiclk", "apb_pclk"; |
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num-cs = <1>; |
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#address-cells = <1>; |
|
#size-cells = <0>; |
|
status = "disabled"; |
|
}; |
|
|
|
ssp1: spi@190000 { |
|
compatible = "arm,pl022", "arm,primecell"; |
|
reg = <0x00190000 0x1000>; |
|
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; |
|
clocks = <&hsls_div2_clk>, <&hsls_div2_clk>; |
|
clock-names = "spiclk", "apb_pclk"; |
|
num-cs = <1>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
status = "disabled"; |
|
}; |
|
|
|
hwrng: hwrng@220000 { |
|
compatible = "brcm,iproc-rng200"; |
|
reg = <0x00220000 0x28>; |
|
}; |
|
|
|
dma0: dma@310000 { |
|
compatible = "arm,pl330", "arm,primecell"; |
|
reg = <0x00310000 0x1000>; |
|
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; |
|
#dma-cells = <1>; |
|
#dma-channels = <8>; |
|
#dma-requests = <32>; |
|
clocks = <&hsls_div2_clk>; |
|
clock-names = "apb_pclk"; |
|
iommus = <&smmu 0x6000 0x0000>; |
|
}; |
|
|
|
enet: ethernet@340000{ |
|
compatible = "brcm,amac"; |
|
reg = <0x00340000 0x1000>; |
|
reg-names = "amac_base"; |
|
dma-coherent; |
|
interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; |
|
status= "disabled"; |
|
}; |
|
|
|
nand: nand@360000 { |
|
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; |
|
reg = <0x00360000 0x600>, |
|
<0x0050a408 0x600>, |
|
<0x00360f00 0x20>; |
|
reg-names = "nand", "iproc-idm", "iproc-ext"; |
|
interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
brcm,nand-has-wp; |
|
status = "disabled"; |
|
}; |
|
|
|
sdio0: sdhci@3f1000 { |
|
compatible = "brcm,sdhci-iproc"; |
|
reg = <0x003f1000 0x100>; |
|
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; |
|
bus-width = <8>; |
|
clocks = <&sdio0_clk>; |
|
iommus = <&smmu 0x6002 0x0000>; |
|
status = "disabled"; |
|
}; |
|
|
|
sdio1: sdhci@3f2000 { |
|
compatible = "brcm,sdhci-iproc"; |
|
reg = <0x003f2000 0x100>; |
|
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; |
|
bus-width = <8>; |
|
clocks = <&sdio1_clk>; |
|
iommus = <&smmu 0x6003 0x0000>; |
|
status = "disabled"; |
|
}; |
|
}; |
|
|
|
tmons { |
|
compatible = "simple-bus"; |
|
#address-cells = <1>; |
|
#size-cells = <1>; |
|
ranges = <0x0 0x0 0x8f100000 0x100>; |
|
|
|
tmon: tmon@0 { |
|
compatible = "brcm,sr-thermal"; |
|
reg = <0x0 0x40>; |
|
brcm,tmon-mask = <0x3f>; |
|
#thermal-sensor-cells = <1>; |
|
}; |
|
}; |
|
|
|
thermal-zones { |
|
ihost0_thermal: ihost0-thermal { |
|
polling-delay-passive = <0>; |
|
polling-delay = <1000>; |
|
thermal-sensors = <&tmon 0>; |
|
trips { |
|
cpu-crit { |
|
temperature = <105000>; |
|
hysteresis = <0>; |
|
type = "critical"; |
|
}; |
|
}; |
|
}; |
|
ihost1_thermal: ihost1-thermal { |
|
polling-delay-passive = <0>; |
|
polling-delay = <1000>; |
|
thermal-sensors = <&tmon 1>; |
|
trips { |
|
cpu-crit { |
|
temperature = <105000>; |
|
hysteresis = <0>; |
|
type = "critical"; |
|
}; |
|
}; |
|
}; |
|
ihost2_thermal: ihost2-thermal { |
|
polling-delay-passive = <0>; |
|
polling-delay = <1000>; |
|
thermal-sensors = <&tmon 2>; |
|
trips { |
|
cpu-crit { |
|
temperature = <105000>; |
|
hysteresis = <0>; |
|
type = "critical"; |
|
}; |
|
}; |
|
}; |
|
ihost3_thermal: ihost3-thermal { |
|
polling-delay-passive = <0>; |
|
polling-delay = <1000>; |
|
thermal-sensors = <&tmon 3>; |
|
trips { |
|
cpu-crit { |
|
temperature = <105000>; |
|
hysteresis = <0>; |
|
type = "critical"; |
|
}; |
|
}; |
|
}; |
|
crmu_thermal: crmu-thermal { |
|
polling-delay-passive = <0>; |
|
polling-delay = <1000>; |
|
thermal-sensors = <&tmon 4>; |
|
trips { |
|
cpu-crit { |
|
temperature = <105000>; |
|
hysteresis = <0>; |
|
type = "critical"; |
|
}; |
|
}; |
|
}; |
|
nitro_thermal: nitro-thermal { |
|
polling-delay-passive = <0>; |
|
polling-delay = <1000>; |
|
thermal-sensors = <&tmon 5>; |
|
trips { |
|
cpu-crit { |
|
temperature = <105000>; |
|
hysteresis = <0>; |
|
type = "critical"; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
nic-hsls { |
|
compatible = "simple-bus"; |
|
#address-cells = <1>; |
|
#size-cells = <1>; |
|
ranges = <0x0 0x0 0x0 0x7fffffff>; |
|
|
|
nic_i2c0: i2c@60826100 { |
|
compatible = "brcm,iproc-nic-i2c"; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
reg = <0x60826100 0x100>, |
|
<0x60e00408 0x1000>; |
|
brcm,ape-hsls-addr-mask = <0x03400000>; |
|
clock-frequency = <100000>; |
|
status = "disabled"; |
|
}; |
|
}; |
|
};
|
|
|