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226 lines
5.1 KiB
226 lines
5.1 KiB
// SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
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/* |
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* Copyright (c) 2019 Linaro Ltd. |
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* Author: Manivannan Sadhasivam <[email protected]> |
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*/ |
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#include <dt-bindings/clock/bm1880-clock.h> |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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#include <dt-bindings/reset/bitmain,bm1880-reset.h> |
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/ { |
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compatible = "bitmain,bm1880"; |
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interrupt-parent = <&gic>; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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cpus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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cpu0: cpu@0 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a53"; |
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reg = <0x0>; |
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enable-method = "psci"; |
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}; |
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cpu1: cpu@1 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a53"; |
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reg = <0x1>; |
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enable-method = "psci"; |
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}; |
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}; |
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reserved-memory { |
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#address-cells = <2>; |
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#size-cells = <2>; |
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ranges; |
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secmon@100000000 { |
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reg = <0x1 0x00000000 0x0 0x20000>; |
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no-map; |
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}; |
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jpu@130000000 { |
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reg = <0x1 0x30000000 0x0 0x08000000>; // 128M |
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no-map; |
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}; |
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vpu@138000000 { |
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reg = <0x1 0x38000000 0x0 0x08000000>; // 128M |
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no-map; |
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}; |
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}; |
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psci { |
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compatible = "arm,psci-0.2"; |
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method = "smc"; |
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}; |
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timer { |
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compatible = "arm,armv8-timer"; |
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, |
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, |
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, |
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; |
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}; |
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osc: osc { |
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compatible = "fixed-clock"; |
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clock-frequency = <25000000>; |
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#clock-cells = <0>; |
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}; |
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soc { |
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compatible = "simple-bus"; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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ranges; |
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gic: interrupt-controller@50001000 { |
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compatible = "arm,gic-400"; |
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reg = <0x0 0x50001000 0x0 0x1000>, |
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<0x0 0x50002000 0x0 0x2000>; |
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; |
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interrupt-controller; |
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#interrupt-cells = <3>; |
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}; |
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sctrl: system-controller@50010000 { |
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compatible = "bitmain,bm1880-sctrl", "syscon", |
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"simple-mfd"; |
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reg = <0x0 0x50010000 0x0 0x1000>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges = <0x0 0x0 0x50010000 0x1000>; |
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pinctrl: pinctrl@400 { |
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compatible = "bitmain,bm1880-pinctrl"; |
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reg = <0x400 0x120>; |
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}; |
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clk: clock-controller@e8 { |
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compatible = "bitmain,bm1880-clk"; |
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reg = <0xe8 0x0c>, <0x800 0xb0>; |
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reg-names = "pll", "sys"; |
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clocks = <&osc>; |
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clock-names = "osc"; |
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#clock-cells = <1>; |
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}; |
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rst: reset-controller@c00 { |
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compatible = "bitmain,bm1880-reset"; |
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reg = <0xc00 0x8>; |
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#reset-cells = <1>; |
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}; |
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}; |
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gpio0: gpio@50027000 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "snps,dw-apb-gpio"; |
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reg = <0x0 0x50027000 0x0 0x400>; |
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porta: gpio-controller@0 { |
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compatible = "snps,dw-apb-gpio-port"; |
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gpio-controller; |
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#gpio-cells = <2>; |
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ngpios = <32>; |
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reg = <0>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; |
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}; |
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}; |
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gpio1: gpio@50027400 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "snps,dw-apb-gpio"; |
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reg = <0x0 0x50027400 0x0 0x400>; |
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portb: gpio-controller@0 { |
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compatible = "snps,dw-apb-gpio-port"; |
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gpio-controller; |
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#gpio-cells = <2>; |
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ngpios = <32>; |
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reg = <0>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; |
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}; |
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}; |
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gpio2: gpio@50027800 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "snps,dw-apb-gpio"; |
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reg = <0x0 0x50027800 0x0 0x400>; |
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portc: gpio-controller@0 { |
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compatible = "snps,dw-apb-gpio-port"; |
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gpio-controller; |
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#gpio-cells = <2>; |
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ngpios = <8>; |
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reg = <0>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; |
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}; |
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}; |
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uart0: serial@58018000 { |
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compatible = "snps,dw-apb-uart"; |
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reg = <0x0 0x58018000 0x0 0x2000>; |
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clocks = <&clk BM1880_CLK_UART_500M>, |
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<&clk BM1880_CLK_APB_UART>; |
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clock-names = "baudclk", "apb_pclk"; |
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
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reg-shift = <2>; |
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reg-io-width = <4>; |
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resets = <&rst BM1880_RST_UART0_1_CLK>; |
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status = "disabled"; |
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}; |
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uart1: serial@5801A000 { |
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compatible = "snps,dw-apb-uart"; |
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reg = <0x0 0x5801a000 0x0 0x2000>; |
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clocks = <&clk BM1880_CLK_UART_500M>, |
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<&clk BM1880_CLK_APB_UART>; |
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clock-names = "baudclk", "apb_pclk"; |
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; |
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reg-shift = <2>; |
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reg-io-width = <4>; |
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resets = <&rst BM1880_RST_UART0_1_ACLK>; |
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status = "disabled"; |
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}; |
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uart2: serial@5801C000 { |
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compatible = "snps,dw-apb-uart"; |
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reg = <0x0 0x5801c000 0x0 0x2000>; |
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clocks = <&clk BM1880_CLK_UART_500M>, |
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<&clk BM1880_CLK_APB_UART>; |
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clock-names = "baudclk", "apb_pclk"; |
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
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reg-shift = <2>; |
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reg-io-width = <4>; |
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resets = <&rst BM1880_RST_UART2_3_CLK>; |
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status = "disabled"; |
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}; |
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uart3: serial@5801E000 { |
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compatible = "snps,dw-apb-uart"; |
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reg = <0x0 0x5801e000 0x0 0x2000>; |
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clocks = <&clk BM1880_CLK_UART_500M>, |
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<&clk BM1880_CLK_APB_UART>; |
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clock-names = "baudclk", "apb_pclk"; |
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; |
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reg-shift = <2>; |
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reg-io-width = <4>; |
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resets = <&rst BM1880_RST_UART2_3_ACLK>; |
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status = "disabled"; |
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}; |
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}; |
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};
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