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311 lines
5.6 KiB
311 lines
5.6 KiB
/* |
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* ARM Ltd. Juno Platform |
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* |
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* Copyright (c) 2015 ARM Ltd. |
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* |
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* This file is licensed under a dual GPLv2 or BSD license. |
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*/ |
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/dts-v1/; |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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#include "juno-base.dtsi" |
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#include "juno-cs-r1r2.dtsi" |
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/ { |
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model = "ARM Juno development board (r1)"; |
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compatible = "arm,juno-r1", "arm,juno", "arm,vexpress"; |
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interrupt-parent = <&gic>; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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aliases { |
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serial0 = &soc_uart0; |
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}; |
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chosen { |
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stdout-path = "serial0:115200n8"; |
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}; |
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psci { |
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compatible = "arm,psci-0.2"; |
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method = "smc"; |
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}; |
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cpus { |
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#address-cells = <2>; |
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#size-cells = <0>; |
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cpu-map { |
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cluster0 { |
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core0 { |
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cpu = <&A57_0>; |
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}; |
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core1 { |
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cpu = <&A57_1>; |
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}; |
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}; |
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cluster1 { |
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core0 { |
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cpu = <&A53_0>; |
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}; |
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core1 { |
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cpu = <&A53_1>; |
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}; |
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core2 { |
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cpu = <&A53_2>; |
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}; |
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core3 { |
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cpu = <&A53_3>; |
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}; |
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}; |
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}; |
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idle-states { |
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entry-method = "psci"; |
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CPU_SLEEP_0: cpu-sleep-0 { |
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compatible = "arm,idle-state"; |
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arm,psci-suspend-param = <0x0010000>; |
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local-timer-stop; |
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entry-latency-us = <300>; |
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exit-latency-us = <1200>; |
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min-residency-us = <2000>; |
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}; |
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CLUSTER_SLEEP_0: cluster-sleep-0 { |
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compatible = "arm,idle-state"; |
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arm,psci-suspend-param = <0x1010000>; |
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local-timer-stop; |
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entry-latency-us = <400>; |
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exit-latency-us = <1200>; |
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min-residency-us = <2500>; |
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}; |
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}; |
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A57_0: cpu@0 { |
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compatible = "arm,cortex-a57"; |
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reg = <0x0 0x0>; |
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device_type = "cpu"; |
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enable-method = "psci"; |
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i-cache-size = <0xc000>; |
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i-cache-line-size = <64>; |
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i-cache-sets = <256>; |
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d-cache-size = <0x8000>; |
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d-cache-line-size = <64>; |
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d-cache-sets = <256>; |
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next-level-cache = <&A57_L2>; |
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clocks = <&scpi_dvfs 0>; |
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
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capacity-dmips-mhz = <1024>; |
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}; |
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A57_1: cpu@1 { |
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compatible = "arm,cortex-a57"; |
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reg = <0x0 0x1>; |
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device_type = "cpu"; |
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enable-method = "psci"; |
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i-cache-size = <0xc000>; |
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i-cache-line-size = <64>; |
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i-cache-sets = <256>; |
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d-cache-size = <0x8000>; |
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d-cache-line-size = <64>; |
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d-cache-sets = <256>; |
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next-level-cache = <&A57_L2>; |
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clocks = <&scpi_dvfs 0>; |
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
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capacity-dmips-mhz = <1024>; |
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}; |
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A53_0: cpu@100 { |
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compatible = "arm,cortex-a53"; |
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reg = <0x0 0x100>; |
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device_type = "cpu"; |
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enable-method = "psci"; |
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i-cache-size = <0x8000>; |
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i-cache-line-size = <64>; |
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i-cache-sets = <256>; |
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d-cache-size = <0x8000>; |
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d-cache-line-size = <64>; |
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d-cache-sets = <128>; |
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next-level-cache = <&A53_L2>; |
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clocks = <&scpi_dvfs 1>; |
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
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capacity-dmips-mhz = <578>; |
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}; |
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A53_1: cpu@101 { |
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compatible = "arm,cortex-a53"; |
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reg = <0x0 0x101>; |
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device_type = "cpu"; |
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enable-method = "psci"; |
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i-cache-size = <0x8000>; |
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i-cache-line-size = <64>; |
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i-cache-sets = <256>; |
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d-cache-size = <0x8000>; |
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d-cache-line-size = <64>; |
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d-cache-sets = <128>; |
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next-level-cache = <&A53_L2>; |
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clocks = <&scpi_dvfs 1>; |
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
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capacity-dmips-mhz = <578>; |
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}; |
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A53_2: cpu@102 { |
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compatible = "arm,cortex-a53"; |
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reg = <0x0 0x102>; |
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device_type = "cpu"; |
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enable-method = "psci"; |
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i-cache-size = <0x8000>; |
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i-cache-line-size = <64>; |
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i-cache-sets = <256>; |
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d-cache-size = <0x8000>; |
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d-cache-line-size = <64>; |
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d-cache-sets = <128>; |
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next-level-cache = <&A53_L2>; |
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clocks = <&scpi_dvfs 1>; |
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
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capacity-dmips-mhz = <578>; |
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}; |
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A53_3: cpu@103 { |
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compatible = "arm,cortex-a53"; |
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reg = <0x0 0x103>; |
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device_type = "cpu"; |
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enable-method = "psci"; |
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i-cache-size = <0x8000>; |
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i-cache-line-size = <64>; |
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i-cache-sets = <256>; |
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d-cache-size = <0x8000>; |
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d-cache-line-size = <64>; |
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d-cache-sets = <128>; |
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next-level-cache = <&A53_L2>; |
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clocks = <&scpi_dvfs 1>; |
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
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capacity-dmips-mhz = <578>; |
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}; |
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A57_L2: l2-cache0 { |
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compatible = "cache"; |
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cache-size = <0x200000>; |
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cache-line-size = <64>; |
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cache-sets = <2048>; |
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}; |
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A53_L2: l2-cache1 { |
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compatible = "cache"; |
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cache-size = <0x100000>; |
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cache-line-size = <64>; |
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cache-sets = <1024>; |
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}; |
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}; |
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pmu-a57 { |
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compatible = "arm,cortex-a57-pmu"; |
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interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>; |
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interrupt-affinity = <&A57_0>, |
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<&A57_1>; |
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}; |
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pmu-a53 { |
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compatible = "arm,cortex-a53-pmu"; |
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, |
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<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
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interrupt-affinity = <&A53_0>, |
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<&A53_1>, |
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<&A53_2>, |
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<&A53_3>; |
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}; |
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}; |
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&memtimer { |
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status = "okay"; |
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}; |
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&pcie_ctlr { |
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status = "okay"; |
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}; |
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&etm0 { |
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cpu = <&A57_0>; |
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}; |
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&etm1 { |
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cpu = <&A57_1>; |
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}; |
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&etm2 { |
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cpu = <&A53_0>; |
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}; |
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&etm3 { |
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cpu = <&A53_1>; |
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}; |
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&etm4 { |
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cpu = <&A53_2>; |
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}; |
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&etm5 { |
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cpu = <&A53_3>; |
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}; |
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&big_cluster_thermal_zone { |
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status = "okay"; |
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}; |
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&little_cluster_thermal_zone { |
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status = "okay"; |
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}; |
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&gpu0_thermal_zone { |
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status = "okay"; |
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}; |
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&gpu1_thermal_zone { |
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status = "okay"; |
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}; |
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&etf0_out_port { |
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remote-endpoint = <&csys2_funnel_in_port0>; |
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}; |
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&replicator_in_port0 { |
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remote-endpoint = <&csys2_funnel_out_port>; |
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}; |
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&csys1_funnel_in_port0 { |
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remote-endpoint = <&stm_out_port>; |
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}; |
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&stm_out_port { |
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remote-endpoint = <&csys1_funnel_in_port0>; |
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}; |
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&cpu_debug0 { |
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cpu = <&A57_0>; |
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}; |
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&cpu_debug1 { |
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cpu = <&A57_1>; |
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}; |
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&cpu_debug2 { |
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cpu = <&A53_0>; |
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}; |
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&cpu_debug3 { |
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cpu = <&A53_1>; |
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}; |
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&cpu_debug4 { |
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cpu = <&A53_2>; |
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}; |
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&cpu_debug5 { |
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cpu = <&A53_3>; |
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};
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