mirror of https://github.com/Qortal/Brooklyn
You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
1098 lines
29 KiB
1098 lines
29 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
|
/* |
|
* dts file for AppliedMicro (APM) X-Gene Storm SOC |
|
* |
|
* Copyright (C) 2013, Applied Micro Circuits Corporation |
|
*/ |
|
|
|
/ { |
|
compatible = "apm,xgene-storm"; |
|
interrupt-parent = <&gic>; |
|
#address-cells = <2>; |
|
#size-cells = <2>; |
|
|
|
cpus { |
|
#address-cells = <2>; |
|
#size-cells = <0>; |
|
|
|
cpu@0 { |
|
device_type = "cpu"; |
|
compatible = "apm,potenza"; |
|
reg = <0x0 0x000>; |
|
enable-method = "spin-table"; |
|
cpu-release-addr = <0x1 0x0000fff8>; |
|
next-level-cache = <&xgene_L2_0>; |
|
}; |
|
cpu@1 { |
|
device_type = "cpu"; |
|
compatible = "apm,potenza"; |
|
reg = <0x0 0x001>; |
|
enable-method = "spin-table"; |
|
cpu-release-addr = <0x1 0x0000fff8>; |
|
next-level-cache = <&xgene_L2_0>; |
|
}; |
|
cpu@100 { |
|
device_type = "cpu"; |
|
compatible = "apm,potenza"; |
|
reg = <0x0 0x100>; |
|
enable-method = "spin-table"; |
|
cpu-release-addr = <0x1 0x0000fff8>; |
|
next-level-cache = <&xgene_L2_1>; |
|
}; |
|
cpu@101 { |
|
device_type = "cpu"; |
|
compatible = "apm,potenza"; |
|
reg = <0x0 0x101>; |
|
enable-method = "spin-table"; |
|
cpu-release-addr = <0x1 0x0000fff8>; |
|
next-level-cache = <&xgene_L2_1>; |
|
}; |
|
cpu@200 { |
|
device_type = "cpu"; |
|
compatible = "apm,potenza"; |
|
reg = <0x0 0x200>; |
|
enable-method = "spin-table"; |
|
cpu-release-addr = <0x1 0x0000fff8>; |
|
next-level-cache = <&xgene_L2_2>; |
|
}; |
|
cpu@201 { |
|
device_type = "cpu"; |
|
compatible = "apm,potenza"; |
|
reg = <0x0 0x201>; |
|
enable-method = "spin-table"; |
|
cpu-release-addr = <0x1 0x0000fff8>; |
|
next-level-cache = <&xgene_L2_2>; |
|
}; |
|
cpu@300 { |
|
device_type = "cpu"; |
|
compatible = "apm,potenza"; |
|
reg = <0x0 0x300>; |
|
enable-method = "spin-table"; |
|
cpu-release-addr = <0x1 0x0000fff8>; |
|
next-level-cache = <&xgene_L2_3>; |
|
}; |
|
cpu@301 { |
|
device_type = "cpu"; |
|
compatible = "apm,potenza"; |
|
reg = <0x0 0x301>; |
|
enable-method = "spin-table"; |
|
cpu-release-addr = <0x1 0x0000fff8>; |
|
next-level-cache = <&xgene_L2_3>; |
|
}; |
|
xgene_L2_0: l2-cache-0 { |
|
compatible = "cache"; |
|
}; |
|
xgene_L2_1: l2-cache-1 { |
|
compatible = "cache"; |
|
}; |
|
xgene_L2_2: l2-cache-2 { |
|
compatible = "cache"; |
|
}; |
|
xgene_L2_3: l2-cache-3 { |
|
compatible = "cache"; |
|
}; |
|
}; |
|
|
|
gic: interrupt-controller@78010000 { |
|
compatible = "arm,cortex-a15-gic"; |
|
#interrupt-cells = <3>; |
|
interrupt-controller; |
|
reg = <0x0 0x78010000 0x0 0x1000>, /* GIC Dist */ |
|
<0x0 0x78020000 0x0 0x1000>, /* GIC CPU */ |
|
<0x0 0x78040000 0x0 0x2000>, /* GIC VCPU Control */ |
|
<0x0 0x78060000 0x0 0x2000>; /* GIC VCPU */ |
|
interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */ |
|
}; |
|
|
|
timer { |
|
compatible = "arm,armv8-timer"; |
|
interrupts = <1 0 0xff08>, /* Secure Phys IRQ */ |
|
<1 13 0xff08>, /* Non-secure Phys IRQ */ |
|
<1 14 0xff08>, /* Virt IRQ */ |
|
<1 15 0xff08>; /* Hyp IRQ */ |
|
clock-frequency = <50000000>; |
|
}; |
|
|
|
pmu { |
|
compatible = "apm,potenza-pmu", "arm,armv8-pmuv3"; |
|
interrupts = <1 12 0xff04>; |
|
}; |
|
|
|
soc { |
|
compatible = "simple-bus"; |
|
#address-cells = <2>; |
|
#size-cells = <2>; |
|
ranges; |
|
dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>; |
|
|
|
clocks { |
|
#address-cells = <2>; |
|
#size-cells = <2>; |
|
ranges; |
|
refclk: refclk { |
|
compatible = "fixed-clock"; |
|
#clock-cells = <1>; |
|
clock-frequency = <100000000>; |
|
clock-output-names = "refclk"; |
|
}; |
|
|
|
pcppll: pcppll@17000100 { |
|
compatible = "apm,xgene-pcppll-clock"; |
|
#clock-cells = <1>; |
|
clocks = <&refclk 0>; |
|
clock-names = "pcppll"; |
|
reg = <0x0 0x17000100 0x0 0x1000>; |
|
clock-output-names = "pcppll"; |
|
type = <0>; |
|
}; |
|
|
|
socpll: socpll@17000120 { |
|
compatible = "apm,xgene-socpll-clock"; |
|
#clock-cells = <1>; |
|
clocks = <&refclk 0>; |
|
clock-names = "socpll"; |
|
reg = <0x0 0x17000120 0x0 0x1000>; |
|
clock-output-names = "socpll"; |
|
type = <1>; |
|
}; |
|
|
|
socplldiv2: socplldiv2 { |
|
compatible = "fixed-factor-clock"; |
|
#clock-cells = <1>; |
|
clocks = <&socpll 0>; |
|
clock-names = "socplldiv2"; |
|
clock-mult = <1>; |
|
clock-div = <2>; |
|
clock-output-names = "socplldiv2"; |
|
}; |
|
|
|
ahbclk: ahbclk@17000000 { |
|
compatible = "apm,xgene-device-clock"; |
|
#clock-cells = <1>; |
|
clocks = <&socplldiv2 0>; |
|
reg = <0x0 0x17000000 0x0 0x2000>; |
|
reg-names = "div-reg"; |
|
divider-offset = <0x164>; |
|
divider-width = <0x5>; |
|
divider-shift = <0x0>; |
|
clock-output-names = "ahbclk"; |
|
}; |
|
|
|
sdioclk: sdioclk@1f2ac000 { |
|
compatible = "apm,xgene-device-clock"; |
|
#clock-cells = <1>; |
|
clocks = <&socplldiv2 0>; |
|
reg = <0x0 0x1f2ac000 0x0 0x1000 |
|
0x0 0x17000000 0x0 0x2000>; |
|
reg-names = "csr-reg", "div-reg"; |
|
csr-offset = <0x0>; |
|
csr-mask = <0x2>; |
|
enable-offset = <0x8>; |
|
enable-mask = <0x2>; |
|
divider-offset = <0x178>; |
|
divider-width = <0x8>; |
|
divider-shift = <0x0>; |
|
clock-output-names = "sdioclk"; |
|
}; |
|
|
|
ethclk: ethclk { |
|
compatible = "apm,xgene-device-clock"; |
|
#clock-cells = <1>; |
|
clocks = <&socplldiv2 0>; |
|
clock-names = "ethclk"; |
|
reg = <0x0 0x17000000 0x0 0x1000>; |
|
reg-names = "div-reg"; |
|
divider-offset = <0x238>; |
|
divider-width = <0x9>; |
|
divider-shift = <0x0>; |
|
clock-output-names = "ethclk"; |
|
}; |
|
|
|
menetclk: menetclk { |
|
compatible = "apm,xgene-device-clock"; |
|
#clock-cells = <1>; |
|
clocks = <ðclk 0>; |
|
reg = <0x0 0x1702c000 0x0 0x1000>; |
|
reg-names = "csr-reg"; |
|
clock-output-names = "menetclk"; |
|
}; |
|
|
|
sge0clk: sge0clk@1f21c000 { |
|
compatible = "apm,xgene-device-clock"; |
|
#clock-cells = <1>; |
|
clocks = <&socplldiv2 0>; |
|
reg = <0x0 0x1f21c000 0x0 0x1000>; |
|
reg-names = "csr-reg"; |
|
csr-mask = <0xa>; |
|
enable-mask = <0xf>; |
|
clock-output-names = "sge0clk"; |
|
}; |
|
|
|
xge0clk: xge0clk@1f61c000 { |
|
compatible = "apm,xgene-device-clock"; |
|
#clock-cells = <1>; |
|
clocks = <&socplldiv2 0>; |
|
reg = <0x0 0x1f61c000 0x0 0x1000>; |
|
reg-names = "csr-reg"; |
|
csr-mask = <0x3>; |
|
clock-output-names = "xge0clk"; |
|
}; |
|
|
|
xge1clk: xge1clk@1f62c000 { |
|
compatible = "apm,xgene-device-clock"; |
|
status = "disabled"; |
|
#clock-cells = <1>; |
|
clocks = <&socplldiv2 0>; |
|
reg = <0x0 0x1f62c000 0x0 0x1000>; |
|
reg-names = "csr-reg"; |
|
csr-mask = <0x3>; |
|
clock-output-names = "xge1clk"; |
|
}; |
|
|
|
sataphy1clk: sataphy1clk@1f21c000 { |
|
compatible = "apm,xgene-device-clock"; |
|
#clock-cells = <1>; |
|
clocks = <&socplldiv2 0>; |
|
reg = <0x0 0x1f21c000 0x0 0x1000>; |
|
reg-names = "csr-reg"; |
|
clock-output-names = "sataphy1clk"; |
|
status = "disabled"; |
|
csr-offset = <0x4>; |
|
csr-mask = <0x00>; |
|
enable-offset = <0x0>; |
|
enable-mask = <0x06>; |
|
}; |
|
|
|
sataphy2clk: sataphy1clk@1f22c000 { |
|
compatible = "apm,xgene-device-clock"; |
|
#clock-cells = <1>; |
|
clocks = <&socplldiv2 0>; |
|
reg = <0x0 0x1f22c000 0x0 0x1000>; |
|
reg-names = "csr-reg"; |
|
clock-output-names = "sataphy2clk"; |
|
status = "ok"; |
|
csr-offset = <0x4>; |
|
csr-mask = <0x3a>; |
|
enable-offset = <0x0>; |
|
enable-mask = <0x06>; |
|
}; |
|
|
|
sataphy3clk: sataphy1clk@1f23c000 { |
|
compatible = "apm,xgene-device-clock"; |
|
#clock-cells = <1>; |
|
clocks = <&socplldiv2 0>; |
|
reg = <0x0 0x1f23c000 0x0 0x1000>; |
|
reg-names = "csr-reg"; |
|
clock-output-names = "sataphy3clk"; |
|
status = "ok"; |
|
csr-offset = <0x4>; |
|
csr-mask = <0x3a>; |
|
enable-offset = <0x0>; |
|
enable-mask = <0x06>; |
|
}; |
|
|
|
sata01clk: sata01clk@1f21c000 { |
|
compatible = "apm,xgene-device-clock"; |
|
#clock-cells = <1>; |
|
clocks = <&socplldiv2 0>; |
|
reg = <0x0 0x1f21c000 0x0 0x1000>; |
|
reg-names = "csr-reg"; |
|
clock-output-names = "sata01clk"; |
|
csr-offset = <0x4>; |
|
csr-mask = <0x05>; |
|
enable-offset = <0x0>; |
|
enable-mask = <0x39>; |
|
}; |
|
|
|
sata23clk: sata23clk@1f22c000 { |
|
compatible = "apm,xgene-device-clock"; |
|
#clock-cells = <1>; |
|
clocks = <&socplldiv2 0>; |
|
reg = <0x0 0x1f22c000 0x0 0x1000>; |
|
reg-names = "csr-reg"; |
|
clock-output-names = "sata23clk"; |
|
csr-offset = <0x4>; |
|
csr-mask = <0x05>; |
|
enable-offset = <0x0>; |
|
enable-mask = <0x39>; |
|
}; |
|
|
|
sata45clk: sata45clk@1f23c000 { |
|
compatible = "apm,xgene-device-clock"; |
|
#clock-cells = <1>; |
|
clocks = <&socplldiv2 0>; |
|
reg = <0x0 0x1f23c000 0x0 0x1000>; |
|
reg-names = "csr-reg"; |
|
clock-output-names = "sata45clk"; |
|
csr-offset = <0x4>; |
|
csr-mask = <0x05>; |
|
enable-offset = <0x0>; |
|
enable-mask = <0x39>; |
|
}; |
|
|
|
rtcclk: rtcclk@17000000 { |
|
compatible = "apm,xgene-device-clock"; |
|
#clock-cells = <1>; |
|
clocks = <&socplldiv2 0>; |
|
reg = <0x0 0x17000000 0x0 0x2000>; |
|
reg-names = "csr-reg"; |
|
csr-offset = <0xc>; |
|
csr-mask = <0x2>; |
|
enable-offset = <0x10>; |
|
enable-mask = <0x2>; |
|
clock-output-names = "rtcclk"; |
|
}; |
|
|
|
rngpkaclk: rngpkaclk@17000000 { |
|
compatible = "apm,xgene-device-clock"; |
|
#clock-cells = <1>; |
|
clocks = <&socplldiv2 0>; |
|
reg = <0x0 0x17000000 0x0 0x2000>; |
|
reg-names = "csr-reg"; |
|
csr-offset = <0xc>; |
|
csr-mask = <0x10>; |
|
enable-offset = <0x10>; |
|
enable-mask = <0x10>; |
|
clock-output-names = "rngpkaclk"; |
|
}; |
|
|
|
pcie0clk: pcie0clk@1f2bc000 { |
|
status = "disabled"; |
|
compatible = "apm,xgene-device-clock"; |
|
#clock-cells = <1>; |
|
clocks = <&socplldiv2 0>; |
|
reg = <0x0 0x1f2bc000 0x0 0x1000>; |
|
reg-names = "csr-reg"; |
|
clock-output-names = "pcie0clk"; |
|
}; |
|
|
|
pcie1clk: pcie1clk@1f2cc000 { |
|
status = "disabled"; |
|
compatible = "apm,xgene-device-clock"; |
|
#clock-cells = <1>; |
|
clocks = <&socplldiv2 0>; |
|
reg = <0x0 0x1f2cc000 0x0 0x1000>; |
|
reg-names = "csr-reg"; |
|
clock-output-names = "pcie1clk"; |
|
}; |
|
|
|
pcie2clk: pcie2clk@1f2dc000 { |
|
status = "disabled"; |
|
compatible = "apm,xgene-device-clock"; |
|
#clock-cells = <1>; |
|
clocks = <&socplldiv2 0>; |
|
reg = <0x0 0x1f2dc000 0x0 0x1000>; |
|
reg-names = "csr-reg"; |
|
clock-output-names = "pcie2clk"; |
|
}; |
|
|
|
pcie3clk: pcie3clk@1f50c000 { |
|
status = "disabled"; |
|
compatible = "apm,xgene-device-clock"; |
|
#clock-cells = <1>; |
|
clocks = <&socplldiv2 0>; |
|
reg = <0x0 0x1f50c000 0x0 0x1000>; |
|
reg-names = "csr-reg"; |
|
clock-output-names = "pcie3clk"; |
|
}; |
|
|
|
pcie4clk: pcie4clk@1f51c000 { |
|
status = "disabled"; |
|
compatible = "apm,xgene-device-clock"; |
|
#clock-cells = <1>; |
|
clocks = <&socplldiv2 0>; |
|
reg = <0x0 0x1f51c000 0x0 0x1000>; |
|
reg-names = "csr-reg"; |
|
clock-output-names = "pcie4clk"; |
|
}; |
|
|
|
dmaclk: dmaclk@1f27c000 { |
|
compatible = "apm,xgene-device-clock"; |
|
#clock-cells = <1>; |
|
clocks = <&socplldiv2 0>; |
|
reg = <0x0 0x1f27c000 0x0 0x1000>; |
|
reg-names = "csr-reg"; |
|
clock-output-names = "dmaclk"; |
|
}; |
|
}; |
|
|
|
msi: msi@79000000 { |
|
compatible = "apm,xgene1-msi"; |
|
msi-controller; |
|
reg = <0x00 0x79000000 0x0 0x900000>; |
|
interrupts = < 0x0 0x10 0x4 |
|
0x0 0x11 0x4 |
|
0x0 0x12 0x4 |
|
0x0 0x13 0x4 |
|
0x0 0x14 0x4 |
|
0x0 0x15 0x4 |
|
0x0 0x16 0x4 |
|
0x0 0x17 0x4 |
|
0x0 0x18 0x4 |
|
0x0 0x19 0x4 |
|
0x0 0x1a 0x4 |
|
0x0 0x1b 0x4 |
|
0x0 0x1c 0x4 |
|
0x0 0x1d 0x4 |
|
0x0 0x1e 0x4 |
|
0x0 0x1f 0x4>; |
|
}; |
|
|
|
scu: system-clk-controller@17000000 { |
|
compatible = "apm,xgene-scu","syscon"; |
|
reg = <0x0 0x17000000 0x0 0x400>; |
|
}; |
|
|
|
reboot: reboot@17000014 { |
|
compatible = "syscon-reboot"; |
|
regmap = <&scu>; |
|
offset = <0x14>; |
|
mask = <0x1>; |
|
}; |
|
|
|
csw: csw@7e200000 { |
|
compatible = "apm,xgene-csw", "syscon"; |
|
reg = <0x0 0x7e200000 0x0 0x1000>; |
|
}; |
|
|
|
mcba: mcba@7e700000 { |
|
compatible = "apm,xgene-mcb", "syscon"; |
|
reg = <0x0 0x7e700000 0x0 0x1000>; |
|
}; |
|
|
|
mcbb: mcbb@7e720000 { |
|
compatible = "apm,xgene-mcb", "syscon"; |
|
reg = <0x0 0x7e720000 0x0 0x1000>; |
|
}; |
|
|
|
efuse: efuse@1054a000 { |
|
compatible = "apm,xgene-efuse", "syscon"; |
|
reg = <0x0 0x1054a000 0x0 0x20>; |
|
}; |
|
|
|
rb: rb@7e000000 { |
|
compatible = "apm,xgene-rb", "syscon"; |
|
reg = <0x0 0x7e000000 0x0 0x10>; |
|
}; |
|
|
|
edac@78800000 { |
|
compatible = "apm,xgene-edac"; |
|
#address-cells = <2>; |
|
#size-cells = <2>; |
|
ranges; |
|
regmap-csw = <&csw>; |
|
regmap-mcba = <&mcba>; |
|
regmap-mcbb = <&mcbb>; |
|
regmap-efuse = <&efuse>; |
|
regmap-rb = <&rb>; |
|
reg = <0x0 0x78800000 0x0 0x100>; |
|
interrupts = <0x0 0x20 0x4>, |
|
<0x0 0x21 0x4>, |
|
<0x0 0x27 0x4>; |
|
|
|
edacmc@7e800000 { |
|
compatible = "apm,xgene-edac-mc"; |
|
reg = <0x0 0x7e800000 0x0 0x1000>; |
|
memory-controller = <0>; |
|
}; |
|
|
|
edacmc@7e840000 { |
|
compatible = "apm,xgene-edac-mc"; |
|
reg = <0x0 0x7e840000 0x0 0x1000>; |
|
memory-controller = <1>; |
|
}; |
|
|
|
edacmc@7e880000 { |
|
compatible = "apm,xgene-edac-mc"; |
|
reg = <0x0 0x7e880000 0x0 0x1000>; |
|
memory-controller = <2>; |
|
}; |
|
|
|
edacmc@7e8c0000 { |
|
compatible = "apm,xgene-edac-mc"; |
|
reg = <0x0 0x7e8c0000 0x0 0x1000>; |
|
memory-controller = <3>; |
|
}; |
|
|
|
edacpmd@7c000000 { |
|
compatible = "apm,xgene-edac-pmd"; |
|
reg = <0x0 0x7c000000 0x0 0x200000>; |
|
pmd-controller = <0>; |
|
}; |
|
|
|
edacpmd@7c200000 { |
|
compatible = "apm,xgene-edac-pmd"; |
|
reg = <0x0 0x7c200000 0x0 0x200000>; |
|
pmd-controller = <1>; |
|
}; |
|
|
|
edacpmd@7c400000 { |
|
compatible = "apm,xgene-edac-pmd"; |
|
reg = <0x0 0x7c400000 0x0 0x200000>; |
|
pmd-controller = <2>; |
|
}; |
|
|
|
edacpmd@7c600000 { |
|
compatible = "apm,xgene-edac-pmd"; |
|
reg = <0x0 0x7c600000 0x0 0x200000>; |
|
pmd-controller = <3>; |
|
}; |
|
|
|
edacl3@7e600000 { |
|
compatible = "apm,xgene-edac-l3"; |
|
reg = <0x0 0x7e600000 0x0 0x1000>; |
|
}; |
|
|
|
edacsoc@7e930000 { |
|
compatible = "apm,xgene-edac-soc-v1"; |
|
reg = <0x0 0x7e930000 0x0 0x1000>; |
|
}; |
|
}; |
|
|
|
pmu: pmu@78810000 { |
|
compatible = "apm,xgene-pmu-v2"; |
|
#address-cells = <2>; |
|
#size-cells = <2>; |
|
ranges; |
|
regmap-csw = <&csw>; |
|
regmap-mcba = <&mcba>; |
|
regmap-mcbb = <&mcbb>; |
|
reg = <0x0 0x78810000 0x0 0x1000>; |
|
interrupts = <0x0 0x22 0x4>; |
|
|
|
pmul3c@7e610000 { |
|
compatible = "apm,xgene-pmu-l3c"; |
|
reg = <0x0 0x7e610000 0x0 0x1000>; |
|
}; |
|
|
|
pmuiob@7e940000 { |
|
compatible = "apm,xgene-pmu-iob"; |
|
reg = <0x0 0x7e940000 0x0 0x1000>; |
|
}; |
|
|
|
pmucmcb@7e710000 { |
|
compatible = "apm,xgene-pmu-mcb"; |
|
reg = <0x0 0x7e710000 0x0 0x1000>; |
|
enable-bit-index = <0>; |
|
}; |
|
|
|
pmucmcb@7e730000 { |
|
compatible = "apm,xgene-pmu-mcb"; |
|
reg = <0x0 0x7e730000 0x0 0x1000>; |
|
enable-bit-index = <1>; |
|
}; |
|
|
|
pmucmc@7e810000 { |
|
compatible = "apm,xgene-pmu-mc"; |
|
reg = <0x0 0x7e810000 0x0 0x1000>; |
|
enable-bit-index = <0>; |
|
}; |
|
|
|
pmucmc@7e850000 { |
|
compatible = "apm,xgene-pmu-mc"; |
|
reg = <0x0 0x7e850000 0x0 0x1000>; |
|
enable-bit-index = <1>; |
|
}; |
|
|
|
pmucmc@7e890000 { |
|
compatible = "apm,xgene-pmu-mc"; |
|
reg = <0x0 0x7e890000 0x0 0x1000>; |
|
enable-bit-index = <2>; |
|
}; |
|
|
|
pmucmc@7e8d0000 { |
|
compatible = "apm,xgene-pmu-mc"; |
|
reg = <0x0 0x7e8d0000 0x0 0x1000>; |
|
enable-bit-index = <3>; |
|
}; |
|
}; |
|
|
|
pcie0: pcie@1f2b0000 { |
|
status = "disabled"; |
|
device_type = "pci"; |
|
compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; |
|
#interrupt-cells = <1>; |
|
#size-cells = <2>; |
|
#address-cells = <3>; |
|
reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */ |
|
0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */ |
|
reg-names = "csr", "cfg"; |
|
ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */ |
|
0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000 /* mem */ |
|
0x43000000 0xf0 0x00000000 0xf0 0x00000000 0x10 0x00000000>; /* mem */ |
|
dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 |
|
0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; |
|
bus-range = <0x00 0xff>; |
|
interrupt-map-mask = <0x0 0x0 0x0 0x7>; |
|
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x4 |
|
0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x4 |
|
0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x4 |
|
0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x4>; |
|
dma-coherent; |
|
clocks = <&pcie0clk 0>; |
|
msi-parent = <&msi>; |
|
}; |
|
|
|
pcie1: pcie@1f2c0000 { |
|
status = "disabled"; |
|
device_type = "pci"; |
|
compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; |
|
#interrupt-cells = <1>; |
|
#size-cells = <2>; |
|
#address-cells = <3>; |
|
reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */ |
|
0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */ |
|
reg-names = "csr", "cfg"; |
|
ranges = <0x01000000 0x00 0x00000000 0xd0 0x10000000 0x00 0x00010000 /* io */ |
|
0x02000000 0x00 0x80000000 0xd1 0x80000000 0x00 0x80000000 /* mem */ |
|
0x43000000 0xd8 0x00000000 0xd8 0x00000000 0x08 0x00000000>; /* mem */ |
|
dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 |
|
0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; |
|
bus-range = <0x00 0xff>; |
|
interrupt-map-mask = <0x0 0x0 0x0 0x7>; |
|
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x4 |
|
0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x4 |
|
0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x4 |
|
0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x4>; |
|
dma-coherent; |
|
clocks = <&pcie1clk 0>; |
|
msi-parent = <&msi>; |
|
}; |
|
|
|
pcie2: pcie@1f2d0000 { |
|
status = "disabled"; |
|
device_type = "pci"; |
|
compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; |
|
#interrupt-cells = <1>; |
|
#size-cells = <2>; |
|
#address-cells = <3>; |
|
reg = < 0x00 0x1f2d0000 0x0 0x00010000 /* Controller registers */ |
|
0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */ |
|
reg-names = "csr", "cfg"; |
|
ranges = <0x01000000 0x00 0x00000000 0x90 0x10000000 0x00 0x00010000 /* io */ |
|
0x02000000 0x00 0x80000000 0x91 0x80000000 0x00 0x80000000 /* mem */ |
|
0x43000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* mem */ |
|
dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 |
|
0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; |
|
bus-range = <0x00 0xff>; |
|
interrupt-map-mask = <0x0 0x0 0x0 0x7>; |
|
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x4 |
|
0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x4 |
|
0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x4 |
|
0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x4>; |
|
dma-coherent; |
|
clocks = <&pcie2clk 0>; |
|
msi-parent = <&msi>; |
|
}; |
|
|
|
pcie3: pcie@1f500000 { |
|
status = "disabled"; |
|
device_type = "pci"; |
|
compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; |
|
#interrupt-cells = <1>; |
|
#size-cells = <2>; |
|
#address-cells = <3>; |
|
reg = < 0x00 0x1f500000 0x0 0x00010000 /* Controller registers */ |
|
0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */ |
|
reg-names = "csr", "cfg"; |
|
ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000 /* io */ |
|
0x02000000 0x00 0x80000000 0xa1 0x80000000 0x00 0x80000000 /* mem */ |
|
0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */ |
|
dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 |
|
0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; |
|
bus-range = <0x00 0xff>; |
|
interrupt-map-mask = <0x0 0x0 0x0 0x7>; |
|
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x4 |
|
0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x4 |
|
0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x4 |
|
0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x4>; |
|
dma-coherent; |
|
clocks = <&pcie3clk 0>; |
|
msi-parent = <&msi>; |
|
}; |
|
|
|
pcie4: pcie@1f510000 { |
|
status = "disabled"; |
|
device_type = "pci"; |
|
compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; |
|
#interrupt-cells = <1>; |
|
#size-cells = <2>; |
|
#address-cells = <3>; |
|
reg = < 0x00 0x1f510000 0x0 0x00010000 /* Controller registers */ |
|
0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */ |
|
reg-names = "csr", "cfg"; |
|
ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000 /* io */ |
|
0x02000000 0x00 0x80000000 0xc1 0x80000000 0x00 0x80000000 /* mem */ |
|
0x43000000 0xc8 0x00000000 0xc8 0x00000000 0x08 0x00000000>; /* mem */ |
|
dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 |
|
0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; |
|
bus-range = <0x00 0xff>; |
|
interrupt-map-mask = <0x0 0x0 0x0 0x7>; |
|
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x4 |
|
0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x4 |
|
0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x4 |
|
0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x4>; |
|
dma-coherent; |
|
clocks = <&pcie4clk 0>; |
|
msi-parent = <&msi>; |
|
}; |
|
|
|
mailbox: mailbox@10540000 { |
|
compatible = "apm,xgene-slimpro-mbox"; |
|
reg = <0x0 0x10540000 0x0 0xa000>; |
|
#mbox-cells = <1>; |
|
interrupts = <0x0 0x0 0x4>, |
|
<0x0 0x1 0x4>, |
|
<0x0 0x2 0x4>, |
|
<0x0 0x3 0x4>, |
|
<0x0 0x4 0x4>, |
|
<0x0 0x5 0x4>, |
|
<0x0 0x6 0x4>, |
|
<0x0 0x7 0x4>; |
|
}; |
|
|
|
i2cslimpro { |
|
compatible = "apm,xgene-slimpro-i2c"; |
|
mboxes = <&mailbox 0>; |
|
}; |
|
|
|
hwmonslimpro { |
|
compatible = "apm,xgene-slimpro-hwmon"; |
|
mboxes = <&mailbox 7>; |
|
}; |
|
|
|
serial0: serial@1c020000 { |
|
status = "disabled"; |
|
device_type = "serial"; |
|
compatible = "ns16550a"; |
|
reg = <0 0x1c020000 0x0 0x1000>; |
|
reg-shift = <2>; |
|
clock-frequency = <10000000>; /* Updated by bootloader */ |
|
interrupt-parent = <&gic>; |
|
interrupts = <0x0 0x4c 0x4>; |
|
}; |
|
|
|
serial1: serial@1c021000 { |
|
status = "disabled"; |
|
device_type = "serial"; |
|
compatible = "ns16550a"; |
|
reg = <0 0x1c021000 0x0 0x1000>; |
|
reg-shift = <2>; |
|
clock-frequency = <10000000>; /* Updated by bootloader */ |
|
interrupt-parent = <&gic>; |
|
interrupts = <0x0 0x4d 0x4>; |
|
}; |
|
|
|
serial2: serial@1c022000 { |
|
status = "disabled"; |
|
device_type = "serial"; |
|
compatible = "ns16550a"; |
|
reg = <0 0x1c022000 0x0 0x1000>; |
|
reg-shift = <2>; |
|
clock-frequency = <10000000>; /* Updated by bootloader */ |
|
interrupt-parent = <&gic>; |
|
interrupts = <0x0 0x4e 0x4>; |
|
}; |
|
|
|
serial3: serial@1c023000 { |
|
status = "disabled"; |
|
device_type = "serial"; |
|
compatible = "ns16550a"; |
|
reg = <0 0x1c023000 0x0 0x1000>; |
|
reg-shift = <2>; |
|
clock-frequency = <10000000>; /* Updated by bootloader */ |
|
interrupt-parent = <&gic>; |
|
interrupts = <0x0 0x4f 0x4>; |
|
}; |
|
|
|
mmc0: mmc@1c000000 { |
|
compatible = "arasan,sdhci-4.9a"; |
|
reg = <0x0 0x1c000000 0x0 0x100>; |
|
interrupts = <0x0 0x49 0x4>; |
|
dma-coherent; |
|
no-1-8-v; |
|
clock-names = "clk_xin", "clk_ahb"; |
|
clocks = <&sdioclk 0>, <&ahbclk 0>; |
|
}; |
|
|
|
gfcgpio: gpio0@1701c000 { |
|
compatible = "apm,xgene-gpio"; |
|
reg = <0x0 0x1701c000 0x0 0x40>; |
|
gpio-controller; |
|
#gpio-cells = <2>; |
|
}; |
|
|
|
dwgpio: gpio@1c024000 { |
|
compatible = "snps,dw-apb-gpio"; |
|
reg = <0x0 0x1c024000 0x0 0x1000>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
|
|
porta: gpio-controller@0 { |
|
compatible = "snps,dw-apb-gpio-port"; |
|
gpio-controller; |
|
#gpio-cells = <2>; |
|
snps,nr-gpios = <32>; |
|
reg = <0>; |
|
}; |
|
}; |
|
|
|
i2c0: i2c@10512000 { |
|
status = "disabled"; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
compatible = "snps,designware-i2c"; |
|
reg = <0x0 0x10512000 0x0 0x1000>; |
|
interrupts = <0 0x44 0x4>; |
|
#clock-cells = <1>; |
|
clocks = <&ahbclk 0>; |
|
bus_num = <0>; |
|
}; |
|
|
|
phy1: phy@1f21a000 { |
|
compatible = "apm,xgene-phy"; |
|
reg = <0x0 0x1f21a000 0x0 0x100>; |
|
#phy-cells = <1>; |
|
clocks = <&sataphy1clk 0>; |
|
status = "disabled"; |
|
apm,tx-boost-gain = <30 30 30 30 30 30>; |
|
apm,tx-eye-tuning = <2 10 10 2 10 10>; |
|
}; |
|
|
|
phy2: phy@1f22a000 { |
|
compatible = "apm,xgene-phy"; |
|
reg = <0x0 0x1f22a000 0x0 0x100>; |
|
#phy-cells = <1>; |
|
clocks = <&sataphy2clk 0>; |
|
status = "ok"; |
|
apm,tx-boost-gain = <30 30 30 30 30 30>; |
|
apm,tx-eye-tuning = <1 10 10 2 10 10>; |
|
}; |
|
|
|
phy3: phy@1f23a000 { |
|
compatible = "apm,xgene-phy"; |
|
reg = <0x0 0x1f23a000 0x0 0x100>; |
|
#phy-cells = <1>; |
|
clocks = <&sataphy3clk 0>; |
|
status = "ok"; |
|
apm,tx-boost-gain = <31 31 31 31 31 31>; |
|
apm,tx-eye-tuning = <2 10 10 2 10 10>; |
|
}; |
|
|
|
sata1: sata@1a000000 { |
|
compatible = "apm,xgene-ahci"; |
|
reg = <0x0 0x1a000000 0x0 0x1000>, |
|
<0x0 0x1f210000 0x0 0x1000>, |
|
<0x0 0x1f21d000 0x0 0x1000>, |
|
<0x0 0x1f21e000 0x0 0x1000>, |
|
<0x0 0x1f217000 0x0 0x1000>; |
|
interrupts = <0x0 0x86 0x4>; |
|
dma-coherent; |
|
status = "disabled"; |
|
clocks = <&sata01clk 0>; |
|
phys = <&phy1 0>; |
|
phy-names = "sata-phy"; |
|
}; |
|
|
|
sata2: sata@1a400000 { |
|
compatible = "apm,xgene-ahci"; |
|
reg = <0x0 0x1a400000 0x0 0x1000>, |
|
<0x0 0x1f220000 0x0 0x1000>, |
|
<0x0 0x1f22d000 0x0 0x1000>, |
|
<0x0 0x1f22e000 0x0 0x1000>, |
|
<0x0 0x1f227000 0x0 0x1000>; |
|
interrupts = <0x0 0x87 0x4>; |
|
dma-coherent; |
|
status = "ok"; |
|
clocks = <&sata23clk 0>; |
|
phys = <&phy2 0>; |
|
phy-names = "sata-phy"; |
|
}; |
|
|
|
sata3: sata@1a800000 { |
|
compatible = "apm,xgene-ahci"; |
|
reg = <0x0 0x1a800000 0x0 0x1000>, |
|
<0x0 0x1f230000 0x0 0x1000>, |
|
<0x0 0x1f23d000 0x0 0x1000>, |
|
<0x0 0x1f23e000 0x0 0x1000>; |
|
interrupts = <0x0 0x88 0x4>; |
|
dma-coherent; |
|
status = "ok"; |
|
clocks = <&sata45clk 0>; |
|
phys = <&phy3 0>; |
|
phy-names = "sata-phy"; |
|
}; |
|
|
|
/* Do not change dwusb name, coded for backward compatibility */ |
|
usb0: dwusb@19000000 { |
|
status = "disabled"; |
|
compatible = "snps,dwc3"; |
|
reg = <0x0 0x19000000 0x0 0x100000>; |
|
interrupts = <0x0 0x89 0x4>; |
|
dma-coherent; |
|
dr_mode = "host"; |
|
}; |
|
|
|
usb1: dwusb@19800000 { |
|
status = "disabled"; |
|
compatible = "snps,dwc3"; |
|
reg = <0x0 0x19800000 0x0 0x100000>; |
|
interrupts = <0x0 0x8a 0x4>; |
|
dma-coherent; |
|
dr_mode = "host"; |
|
}; |
|
|
|
sbgpio: gpio@17001000{ |
|
compatible = "apm,xgene-gpio-sb"; |
|
reg = <0x0 0x17001000 0x0 0x400>; |
|
#gpio-cells = <2>; |
|
gpio-controller; |
|
interrupts = <0x0 0x28 0x1>, |
|
<0x0 0x29 0x1>, |
|
<0x0 0x2a 0x1>, |
|
<0x0 0x2b 0x1>, |
|
<0x0 0x2c 0x1>, |
|
<0x0 0x2d 0x1>; |
|
interrupt-parent = <&gic>; |
|
#interrupt-cells = <2>; |
|
interrupt-controller; |
|
}; |
|
|
|
rtc: rtc@10510000 { |
|
compatible = "apm,xgene-rtc"; |
|
reg = <0x0 0x10510000 0x0 0x400>; |
|
interrupts = <0x0 0x46 0x4>; |
|
#clock-cells = <1>; |
|
clocks = <&rtcclk 0>; |
|
}; |
|
|
|
mdio: mdio@17020000 { |
|
compatible = "apm,xgene-mdio-rgmii"; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
reg = <0x0 0x17020000 0x0 0xd100>; |
|
clocks = <&menetclk 0>; |
|
}; |
|
|
|
menet: ethernet@17020000 { |
|
compatible = "apm,xgene-enet"; |
|
status = "disabled"; |
|
reg = <0x0 0x17020000 0x0 0xd100>, |
|
<0x0 0x17030000 0x0 0xc300>, |
|
<0x0 0x10000000 0x0 0x200>; |
|
reg-names = "enet_csr", "ring_csr", "ring_cmd"; |
|
interrupts = <0x0 0x3c 0x4>; |
|
dma-coherent; |
|
clocks = <&menetclk 0>; |
|
/* mac address will be overwritten by the bootloader */ |
|
local-mac-address = [00 00 00 00 00 00]; |
|
phy-connection-type = "rgmii"; |
|
phy-handle = <&menetphy>,<&menet0phy>; |
|
mdio { |
|
compatible = "apm,xgene-mdio"; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
menetphy: menetphy@3 { |
|
compatible = "ethernet-phy-id001c.c915"; |
|
reg = <0x3>; |
|
}; |
|
|
|
}; |
|
}; |
|
|
|
sgenet0: ethernet@1f210000 { |
|
compatible = "apm,xgene1-sgenet"; |
|
status = "disabled"; |
|
reg = <0x0 0x1f210000 0x0 0xd100>, |
|
<0x0 0x1f200000 0x0 0xc300>, |
|
<0x0 0x1b000000 0x0 0x200>; |
|
reg-names = "enet_csr", "ring_csr", "ring_cmd"; |
|
interrupts = <0x0 0xa0 0x4>, |
|
<0x0 0xa1 0x4>; |
|
dma-coherent; |
|
clocks = <&sge0clk 0>; |
|
local-mac-address = [00 00 00 00 00 00]; |
|
phy-connection-type = "sgmii"; |
|
phy-handle = <&sgenet0phy>; |
|
}; |
|
|
|
sgenet1: ethernet@1f210030 { |
|
compatible = "apm,xgene1-sgenet"; |
|
status = "disabled"; |
|
reg = <0x0 0x1f210030 0x0 0xd100>, |
|
<0x0 0x1f200000 0x0 0xc300>, |
|
<0x0 0x1b000000 0x0 0x8000>; |
|
reg-names = "enet_csr", "ring_csr", "ring_cmd"; |
|
interrupts = <0x0 0xac 0x4>, |
|
<0x0 0xad 0x4>; |
|
port-id = <1>; |
|
dma-coherent; |
|
local-mac-address = [00 00 00 00 00 00]; |
|
phy-connection-type = "sgmii"; |
|
phy-handle = <&sgenet1phy>; |
|
}; |
|
|
|
xgenet: ethernet@1f610000 { |
|
compatible = "apm,xgene1-xgenet"; |
|
status = "disabled"; |
|
reg = <0x0 0x1f610000 0x0 0xd100>, |
|
<0x0 0x1f600000 0x0 0xc300>, |
|
<0x0 0x18000000 0x0 0x200>; |
|
reg-names = "enet_csr", "ring_csr", "ring_cmd"; |
|
interrupts = <0x0 0x60 0x4>, |
|
<0x0 0x61 0x4>, |
|
<0x0 0x62 0x4>, |
|
<0x0 0x63 0x4>, |
|
<0x0 0x64 0x4>, |
|
<0x0 0x65 0x4>, |
|
<0x0 0x66 0x4>, |
|
<0x0 0x67 0x4>; |
|
channel = <0>; |
|
dma-coherent; |
|
clocks = <&xge0clk 0>; |
|
/* mac address will be overwritten by the bootloader */ |
|
local-mac-address = [00 00 00 00 00 00]; |
|
phy-connection-type = "xgmii"; |
|
}; |
|
|
|
xgenet1: ethernet@1f620000 { |
|
compatible = "apm,xgene1-xgenet"; |
|
status = "disabled"; |
|
reg = <0x0 0x1f620000 0x0 0xd100>, |
|
<0x0 0x1f600000 0x0 0xc300>, |
|
<0x0 0x18000000 0x0 0x8000>; |
|
reg-names = "enet_csr", "ring_csr", "ring_cmd"; |
|
interrupts = <0x0 0x6c 0x4>, |
|
<0x0 0x6d 0x4>; |
|
port-id = <1>; |
|
dma-coherent; |
|
clocks = <&xge1clk 0>; |
|
/* mac address will be overwritten by the bootloader */ |
|
local-mac-address = [00 00 00 00 00 00]; |
|
phy-connection-type = "xgmii"; |
|
}; |
|
|
|
rng: rng@10520000 { |
|
compatible = "apm,xgene-rng"; |
|
reg = <0x0 0x10520000 0x0 0x100>; |
|
interrupts = <0x0 0x41 0x4>; |
|
clocks = <&rngpkaclk 0>; |
|
}; |
|
|
|
dma: dma@1f270000 { |
|
compatible = "apm,xgene-storm-dma"; |
|
device_type = "dma"; |
|
reg = <0x0 0x1f270000 0x0 0x10000>, |
|
<0x0 0x1f200000 0x0 0x10000>, |
|
<0x0 0x1b000000 0x0 0x400000>, |
|
<0x0 0x1054a000 0x0 0x100>; |
|
interrupts = <0x0 0x82 0x4>, |
|
<0x0 0xb8 0x4>, |
|
<0x0 0xb9 0x4>, |
|
<0x0 0xba 0x4>, |
|
<0x0 0xbb 0x4>; |
|
dma-coherent; |
|
clocks = <&dmaclk 0>; |
|
}; |
|
}; |
|
};
|
|
|