mirror of https://github.com/Qortal/Brooklyn
You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
141 lines
2.7 KiB
141 lines
2.7 KiB
// SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
|
/* |
|
* Copyright (c) 2019 BayLibre, SAS |
|
* Author: Neil Armstrong <[email protected]> |
|
*/ |
|
|
|
#include "meson-g12.dtsi" |
|
|
|
/ { |
|
compatible = "amlogic,g12b"; |
|
|
|
cpus { |
|
#address-cells = <0x2>; |
|
#size-cells = <0x0>; |
|
|
|
cpu-map { |
|
cluster0 { |
|
core0 { |
|
cpu = <&cpu0>; |
|
}; |
|
|
|
core1 { |
|
cpu = <&cpu1>; |
|
}; |
|
}; |
|
|
|
cluster1 { |
|
core0 { |
|
cpu = <&cpu100>; |
|
}; |
|
|
|
core1 { |
|
cpu = <&cpu101>; |
|
}; |
|
|
|
core2 { |
|
cpu = <&cpu102>; |
|
}; |
|
|
|
core3 { |
|
cpu = <&cpu103>; |
|
}; |
|
}; |
|
}; |
|
|
|
cpu0: cpu@0 { |
|
device_type = "cpu"; |
|
compatible = "arm,cortex-a53"; |
|
reg = <0x0 0x0>; |
|
enable-method = "psci"; |
|
capacity-dmips-mhz = <592>; |
|
next-level-cache = <&l2>; |
|
#cooling-cells = <2>; |
|
}; |
|
|
|
cpu1: cpu@1 { |
|
device_type = "cpu"; |
|
compatible = "arm,cortex-a53"; |
|
reg = <0x0 0x1>; |
|
enable-method = "psci"; |
|
capacity-dmips-mhz = <592>; |
|
next-level-cache = <&l2>; |
|
#cooling-cells = <2>; |
|
}; |
|
|
|
cpu100: cpu@100 { |
|
device_type = "cpu"; |
|
compatible = "arm,cortex-a73"; |
|
reg = <0x0 0x100>; |
|
enable-method = "psci"; |
|
capacity-dmips-mhz = <1024>; |
|
next-level-cache = <&l2>; |
|
#cooling-cells = <2>; |
|
}; |
|
|
|
cpu101: cpu@101 { |
|
device_type = "cpu"; |
|
compatible = "arm,cortex-a73"; |
|
reg = <0x0 0x101>; |
|
enable-method = "psci"; |
|
capacity-dmips-mhz = <1024>; |
|
next-level-cache = <&l2>; |
|
#cooling-cells = <2>; |
|
}; |
|
|
|
cpu102: cpu@102 { |
|
device_type = "cpu"; |
|
compatible = "arm,cortex-a73"; |
|
reg = <0x0 0x102>; |
|
enable-method = "psci"; |
|
capacity-dmips-mhz = <1024>; |
|
next-level-cache = <&l2>; |
|
#cooling-cells = <2>; |
|
}; |
|
|
|
cpu103: cpu@103 { |
|
device_type = "cpu"; |
|
compatible = "arm,cortex-a73"; |
|
reg = <0x0 0x103>; |
|
enable-method = "psci"; |
|
capacity-dmips-mhz = <1024>; |
|
next-level-cache = <&l2>; |
|
#cooling-cells = <2>; |
|
}; |
|
|
|
l2: l2-cache0 { |
|
compatible = "cache"; |
|
}; |
|
}; |
|
}; |
|
|
|
&clkc { |
|
compatible = "amlogic,g12b-clkc"; |
|
}; |
|
|
|
&cpu_thermal { |
|
cooling-maps { |
|
map0 { |
|
trip = <&cpu_passive>; |
|
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
map1 { |
|
trip = <&cpu_hot>; |
|
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
}; |
|
}; |
|
|
|
&mali { |
|
dma-coherent; |
|
};
|
|
|