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433 lines
11 KiB
433 lines
11 KiB
/**************************************************************************** |
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Copyright Echo Digital Audio Corporation (c) 1998 - 2004 |
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All rights reserved |
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www.echoaudio.com |
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This file is part of Echo Digital Audio's generic driver library. |
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Echo Digital Audio's generic driver library is free software; |
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you can redistribute it and/or modify it under the terms of |
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the GNU General Public License as published by the Free Software |
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Foundation. |
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This program is distributed in the hope that it will be useful, |
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but WITHOUT ANY WARRANTY; without even the implied warranty of |
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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GNU General Public License for more details. |
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You should have received a copy of the GNU General Public License |
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along with this program; if not, write to the Free Software |
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, |
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MA 02111-1307, USA. |
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************************************************************************* |
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Translation from C++ and adaptation for use in ALSA-Driver |
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were made by Giuliano Pochini <[email protected]> |
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****************************************************************************/ |
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/* These functions are common for all "3G" cards */ |
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static int check_asic_status(struct echoaudio *chip) |
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{ |
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u32 box_status; |
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if (wait_handshake(chip)) |
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return -EIO; |
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chip->comm_page->ext_box_status = cpu_to_le32(E3G_ASIC_NOT_LOADED); |
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chip->asic_loaded = false; |
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clear_handshake(chip); |
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send_vector(chip, DSP_VC_TEST_ASIC); |
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if (wait_handshake(chip)) { |
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chip->dsp_code = NULL; |
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return -EIO; |
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} |
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box_status = le32_to_cpu(chip->comm_page->ext_box_status); |
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dev_dbg(chip->card->dev, "box_status=%x\n", box_status); |
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if (box_status == E3G_ASIC_NOT_LOADED) |
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return -ENODEV; |
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chip->asic_loaded = true; |
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return box_status & E3G_BOX_TYPE_MASK; |
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} |
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static inline u32 get_frq_reg(struct echoaudio *chip) |
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{ |
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return le32_to_cpu(chip->comm_page->e3g_frq_register); |
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} |
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/* Most configuration of 3G cards is accomplished by writing the control |
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register. write_control_reg sends the new control register value to the DSP. */ |
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static int write_control_reg(struct echoaudio *chip, u32 ctl, u32 frq, |
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char force) |
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{ |
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__le32 ctl_reg, frq_reg; |
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if (wait_handshake(chip)) |
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return -EIO; |
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dev_dbg(chip->card->dev, |
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"WriteControlReg: Setting 0x%x, 0x%x\n", ctl, frq); |
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ctl_reg = cpu_to_le32(ctl); |
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frq_reg = cpu_to_le32(frq); |
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if (ctl_reg != chip->comm_page->control_register || |
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frq_reg != chip->comm_page->e3g_frq_register || force) { |
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chip->comm_page->e3g_frq_register = frq_reg; |
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chip->comm_page->control_register = ctl_reg; |
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clear_handshake(chip); |
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return send_vector(chip, DSP_VC_WRITE_CONTROL_REG); |
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} |
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dev_dbg(chip->card->dev, "WriteControlReg: not written, no change\n"); |
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return 0; |
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} |
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/* Set the digital mode - currently for Gina24, Layla24, Mona, 3G */ |
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static int set_digital_mode(struct echoaudio *chip, u8 mode) |
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{ |
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u8 previous_mode; |
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int err, i, o; |
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/* All audio channels must be closed before changing the digital mode */ |
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if (snd_BUG_ON(chip->pipe_alloc_mask)) |
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return -EAGAIN; |
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if (snd_BUG_ON(!(chip->digital_modes & (1 << mode)))) |
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return -EINVAL; |
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previous_mode = chip->digital_mode; |
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err = dsp_set_digital_mode(chip, mode); |
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/* If we successfully changed the digital mode from or to ADAT, |
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* then make sure all output, input and monitor levels are |
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* updated by the DSP comm object. */ |
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if (err >= 0 && previous_mode != mode && |
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(previous_mode == DIGITAL_MODE_ADAT || mode == DIGITAL_MODE_ADAT)) { |
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spin_lock_irq(&chip->lock); |
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for (o = 0; o < num_busses_out(chip); o++) |
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for (i = 0; i < num_busses_in(chip); i++) |
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set_monitor_gain(chip, o, i, |
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chip->monitor_gain[o][i]); |
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#ifdef ECHOCARD_HAS_INPUT_GAIN |
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for (i = 0; i < num_busses_in(chip); i++) |
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set_input_gain(chip, i, chip->input_gain[i]); |
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update_input_line_level(chip); |
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#endif |
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for (o = 0; o < num_busses_out(chip); o++) |
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set_output_gain(chip, o, chip->output_gain[o]); |
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update_output_line_level(chip); |
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spin_unlock_irq(&chip->lock); |
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} |
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return err; |
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} |
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static u32 set_spdif_bits(struct echoaudio *chip, u32 control_reg, u32 rate) |
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{ |
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control_reg &= E3G_SPDIF_FORMAT_CLEAR_MASK; |
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switch (rate) { |
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case 32000 : |
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control_reg |= E3G_SPDIF_SAMPLE_RATE0 | E3G_SPDIF_SAMPLE_RATE1; |
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break; |
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case 44100 : |
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if (chip->professional_spdif) |
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control_reg |= E3G_SPDIF_SAMPLE_RATE0; |
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break; |
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case 48000 : |
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control_reg |= E3G_SPDIF_SAMPLE_RATE1; |
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break; |
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} |
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if (chip->professional_spdif) |
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control_reg |= E3G_SPDIF_PRO_MODE; |
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if (chip->non_audio_spdif) |
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control_reg |= E3G_SPDIF_NOT_AUDIO; |
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control_reg |= E3G_SPDIF_24_BIT | E3G_SPDIF_TWO_CHANNEL | |
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E3G_SPDIF_COPY_PERMIT; |
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return control_reg; |
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} |
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/* Set the S/PDIF output format */ |
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static int set_professional_spdif(struct echoaudio *chip, char prof) |
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{ |
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u32 control_reg; |
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control_reg = le32_to_cpu(chip->comm_page->control_register); |
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chip->professional_spdif = prof; |
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control_reg = set_spdif_bits(chip, control_reg, chip->sample_rate); |
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return write_control_reg(chip, control_reg, get_frq_reg(chip), 0); |
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} |
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/* detect_input_clocks() returns a bitmask consisting of all the input clocks |
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currently connected to the hardware; this changes as the user connects and |
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disconnects clock inputs. You should use this information to determine which |
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clocks the user is allowed to select. */ |
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static u32 detect_input_clocks(const struct echoaudio *chip) |
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{ |
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u32 clocks_from_dsp, clock_bits; |
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/* Map the DSP clock detect bits to the generic driver clock |
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* detect bits */ |
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clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks); |
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clock_bits = ECHO_CLOCK_BIT_INTERNAL; |
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if (clocks_from_dsp & E3G_CLOCK_DETECT_BIT_WORD) |
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clock_bits |= ECHO_CLOCK_BIT_WORD; |
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switch(chip->digital_mode) { |
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case DIGITAL_MODE_SPDIF_RCA: |
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case DIGITAL_MODE_SPDIF_OPTICAL: |
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if (clocks_from_dsp & E3G_CLOCK_DETECT_BIT_SPDIF) |
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clock_bits |= ECHO_CLOCK_BIT_SPDIF; |
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break; |
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case DIGITAL_MODE_ADAT: |
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if (clocks_from_dsp & E3G_CLOCK_DETECT_BIT_ADAT) |
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clock_bits |= ECHO_CLOCK_BIT_ADAT; |
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break; |
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} |
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return clock_bits; |
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} |
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static int load_asic(struct echoaudio *chip) |
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{ |
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int box_type, err; |
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if (chip->asic_loaded) |
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return 0; |
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/* Give the DSP a few milliseconds to settle down */ |
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mdelay(2); |
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err = load_asic_generic(chip, DSP_FNC_LOAD_3G_ASIC, FW_3G_ASIC); |
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if (err < 0) |
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return err; |
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chip->asic_code = FW_3G_ASIC; |
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/* Now give the new ASIC some time to set up */ |
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msleep(1000); |
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/* See if it worked */ |
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box_type = check_asic_status(chip); |
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/* Set up the control register if the load succeeded - |
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* 48 kHz, internal clock, S/PDIF RCA mode */ |
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if (box_type >= 0) { |
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err = write_control_reg(chip, E3G_48KHZ, |
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E3G_FREQ_REG_DEFAULT, true); |
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if (err < 0) |
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return err; |
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} |
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return box_type; |
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} |
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static int set_sample_rate(struct echoaudio *chip, u32 rate) |
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{ |
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u32 control_reg, clock, base_rate, frq_reg; |
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/* Only set the clock for internal mode. */ |
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if (chip->input_clock != ECHO_CLOCK_INTERNAL) { |
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dev_warn(chip->card->dev, |
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"Cannot set sample rate - clock not set to CLK_CLOCKININTERNAL\n"); |
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/* Save the rate anyhow */ |
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chip->comm_page->sample_rate = cpu_to_le32(rate); |
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chip->sample_rate = rate; |
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set_input_clock(chip, chip->input_clock); |
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return 0; |
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} |
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if (snd_BUG_ON(rate >= 50000 && |
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chip->digital_mode == DIGITAL_MODE_ADAT)) |
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return -EINVAL; |
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clock = 0; |
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control_reg = le32_to_cpu(chip->comm_page->control_register); |
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control_reg &= E3G_CLOCK_CLEAR_MASK; |
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switch (rate) { |
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case 96000: |
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clock = E3G_96KHZ; |
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break; |
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case 88200: |
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clock = E3G_88KHZ; |
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break; |
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case 48000: |
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clock = E3G_48KHZ; |
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break; |
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case 44100: |
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clock = E3G_44KHZ; |
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break; |
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case 32000: |
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clock = E3G_32KHZ; |
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break; |
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default: |
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clock = E3G_CONTINUOUS_CLOCK; |
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if (rate > 50000) |
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clock |= E3G_DOUBLE_SPEED_MODE; |
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break; |
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} |
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control_reg |= clock; |
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control_reg = set_spdif_bits(chip, control_reg, rate); |
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base_rate = rate; |
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if (base_rate > 50000) |
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base_rate /= 2; |
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if (base_rate < 32000) |
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base_rate = 32000; |
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frq_reg = E3G_MAGIC_NUMBER / base_rate - 2; |
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if (frq_reg > E3G_FREQ_REG_MAX) |
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frq_reg = E3G_FREQ_REG_MAX; |
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chip->comm_page->sample_rate = cpu_to_le32(rate); /* ignored by the DSP */ |
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chip->sample_rate = rate; |
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dev_dbg(chip->card->dev, |
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"SetSampleRate: %d clock %x\n", rate, control_reg); |
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/* Tell the DSP about it - DSP reads both control reg & freq reg */ |
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return write_control_reg(chip, control_reg, frq_reg, 0); |
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} |
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/* Set the sample clock source to internal, S/PDIF, ADAT */ |
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static int set_input_clock(struct echoaudio *chip, u16 clock) |
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{ |
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u32 control_reg, clocks_from_dsp; |
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/* Mask off the clock select bits */ |
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control_reg = le32_to_cpu(chip->comm_page->control_register) & |
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E3G_CLOCK_CLEAR_MASK; |
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clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks); |
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switch (clock) { |
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case ECHO_CLOCK_INTERNAL: |
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chip->input_clock = ECHO_CLOCK_INTERNAL; |
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return set_sample_rate(chip, chip->sample_rate); |
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case ECHO_CLOCK_SPDIF: |
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if (chip->digital_mode == DIGITAL_MODE_ADAT) |
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return -EAGAIN; |
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control_reg |= E3G_SPDIF_CLOCK; |
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if (clocks_from_dsp & E3G_CLOCK_DETECT_BIT_SPDIF96) |
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control_reg |= E3G_DOUBLE_SPEED_MODE; |
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else |
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control_reg &= ~E3G_DOUBLE_SPEED_MODE; |
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break; |
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case ECHO_CLOCK_ADAT: |
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if (chip->digital_mode != DIGITAL_MODE_ADAT) |
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return -EAGAIN; |
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control_reg |= E3G_ADAT_CLOCK; |
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control_reg &= ~E3G_DOUBLE_SPEED_MODE; |
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break; |
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case ECHO_CLOCK_WORD: |
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control_reg |= E3G_WORD_CLOCK; |
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if (clocks_from_dsp & E3G_CLOCK_DETECT_BIT_WORD96) |
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control_reg |= E3G_DOUBLE_SPEED_MODE; |
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else |
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control_reg &= ~E3G_DOUBLE_SPEED_MODE; |
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break; |
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default: |
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dev_err(chip->card->dev, |
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"Input clock 0x%x not supported for Echo3G\n", clock); |
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return -EINVAL; |
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} |
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chip->input_clock = clock; |
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return write_control_reg(chip, control_reg, get_frq_reg(chip), 1); |
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} |
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static int dsp_set_digital_mode(struct echoaudio *chip, u8 mode) |
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{ |
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u32 control_reg; |
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int err, incompatible_clock; |
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/* Set clock to "internal" if it's not compatible with the new mode */ |
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incompatible_clock = false; |
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switch (mode) { |
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case DIGITAL_MODE_SPDIF_OPTICAL: |
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case DIGITAL_MODE_SPDIF_RCA: |
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if (chip->input_clock == ECHO_CLOCK_ADAT) |
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incompatible_clock = true; |
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break; |
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case DIGITAL_MODE_ADAT: |
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if (chip->input_clock == ECHO_CLOCK_SPDIF) |
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incompatible_clock = true; |
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break; |
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default: |
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dev_err(chip->card->dev, |
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"Digital mode not supported: %d\n", mode); |
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return -EINVAL; |
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} |
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spin_lock_irq(&chip->lock); |
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if (incompatible_clock) { |
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chip->sample_rate = 48000; |
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set_input_clock(chip, ECHO_CLOCK_INTERNAL); |
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} |
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/* Clear the current digital mode */ |
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control_reg = le32_to_cpu(chip->comm_page->control_register); |
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control_reg &= E3G_DIGITAL_MODE_CLEAR_MASK; |
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/* Tweak the control reg */ |
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switch (mode) { |
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case DIGITAL_MODE_SPDIF_OPTICAL: |
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control_reg |= E3G_SPDIF_OPTICAL_MODE; |
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break; |
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case DIGITAL_MODE_SPDIF_RCA: |
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/* E3G_SPDIF_OPTICAL_MODE bit cleared */ |
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break; |
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case DIGITAL_MODE_ADAT: |
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control_reg |= E3G_ADAT_MODE; |
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control_reg &= ~E3G_DOUBLE_SPEED_MODE; /* @@ useless */ |
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break; |
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} |
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err = write_control_reg(chip, control_reg, get_frq_reg(chip), 1); |
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spin_unlock_irq(&chip->lock); |
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if (err < 0) |
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return err; |
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chip->digital_mode = mode; |
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dev_dbg(chip->card->dev, "set_digital_mode(%d)\n", chip->digital_mode); |
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return incompatible_clock; |
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}
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