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30 lines
991 B
30 lines
991 B
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* Copyright (c) 2020 MediaTek Inc. |
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* Author: Yong Liang <[email protected]> |
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*/ |
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#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192 |
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#define _DT_BINDINGS_RESET_CONTROLLER_MT8192 |
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#define MT8192_TOPRGU_MM_SW_RST 1 |
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#define MT8192_TOPRGU_MFG_SW_RST 2 |
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#define MT8192_TOPRGU_VENC_SW_RST 3 |
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#define MT8192_TOPRGU_VDEC_SW_RST 4 |
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#define MT8192_TOPRGU_IMG_SW_RST 5 |
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#define MT8192_TOPRGU_MD_SW_RST 7 |
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#define MT8192_TOPRGU_CONN_SW_RST 9 |
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#define MT8192_TOPRGU_CONN_MCU_SW_RST 12 |
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#define MT8192_TOPRGU_IPU0_SW_RST 14 |
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#define MT8192_TOPRGU_IPU1_SW_RST 15 |
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#define MT8192_TOPRGU_AUDIO_SW_RST 17 |
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#define MT8192_TOPRGU_CAMSYS_SW_RST 18 |
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#define MT8192_TOPRGU_MJC_SW_RST 19 |
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#define MT8192_TOPRGU_C2K_S2_SW_RST 20 |
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#define MT8192_TOPRGU_C2K_SW_RST 21 |
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#define MT8192_TOPRGU_PERI_SW_RST 22 |
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#define MT8192_TOPRGU_PERI_AO_SW_RST 23 |
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#define MT8192_TOPRGU_SW_RST_NUM 23 |
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#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */
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