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801 lines
19 KiB
801 lines
19 KiB
// SPDX-License-Identifier: GPL-2.0 |
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// spi-uniphier.c - Socionext UniPhier SPI controller driver |
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// Copyright 2012 Panasonic Corporation |
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// Copyright 2016-2018 Socionext Inc. |
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#include <linux/kernel.h> |
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#include <linux/bitfield.h> |
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#include <linux/bitops.h> |
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/dmaengine.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/spi/spi.h> |
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#include <asm/unaligned.h> |
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#define SSI_TIMEOUT_MS 2000 |
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#define SSI_POLL_TIMEOUT_US 200 |
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#define SSI_MAX_CLK_DIVIDER 254 |
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#define SSI_MIN_CLK_DIVIDER 4 |
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struct uniphier_spi_priv { |
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void __iomem *base; |
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dma_addr_t base_dma_addr; |
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struct clk *clk; |
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struct spi_master *master; |
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struct completion xfer_done; |
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int error; |
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unsigned int tx_bytes; |
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unsigned int rx_bytes; |
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const u8 *tx_buf; |
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u8 *rx_buf; |
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atomic_t dma_busy; |
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bool is_save_param; |
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u8 bits_per_word; |
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u16 mode; |
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u32 speed_hz; |
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}; |
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#define SSI_CTL 0x00 |
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#define SSI_CTL_EN BIT(0) |
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#define SSI_CKS 0x04 |
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#define SSI_CKS_CKRAT_MASK GENMASK(7, 0) |
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#define SSI_CKS_CKPHS BIT(14) |
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#define SSI_CKS_CKINIT BIT(13) |
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#define SSI_CKS_CKDLY BIT(12) |
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#define SSI_TXWDS 0x08 |
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#define SSI_TXWDS_WDLEN_MASK GENMASK(13, 8) |
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#define SSI_TXWDS_TDTF_MASK GENMASK(7, 6) |
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#define SSI_TXWDS_DTLEN_MASK GENMASK(5, 0) |
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#define SSI_RXWDS 0x0c |
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#define SSI_RXWDS_DTLEN_MASK GENMASK(5, 0) |
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#define SSI_FPS 0x10 |
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#define SSI_FPS_FSPOL BIT(15) |
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#define SSI_FPS_FSTRT BIT(14) |
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#define SSI_SR 0x14 |
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#define SSI_SR_BUSY BIT(7) |
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#define SSI_SR_RNE BIT(0) |
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#define SSI_IE 0x18 |
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#define SSI_IE_TCIE BIT(4) |
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#define SSI_IE_RCIE BIT(3) |
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#define SSI_IE_TXRE BIT(2) |
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#define SSI_IE_RXRE BIT(1) |
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#define SSI_IE_RORIE BIT(0) |
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#define SSI_IE_ALL_MASK GENMASK(4, 0) |
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#define SSI_IS 0x1c |
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#define SSI_IS_RXRS BIT(9) |
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#define SSI_IS_RCID BIT(3) |
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#define SSI_IS_RORID BIT(0) |
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#define SSI_IC 0x1c |
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#define SSI_IC_TCIC BIT(4) |
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#define SSI_IC_RCIC BIT(3) |
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#define SSI_IC_RORIC BIT(0) |
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#define SSI_FC 0x20 |
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#define SSI_FC_TXFFL BIT(12) |
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#define SSI_FC_TXFTH_MASK GENMASK(11, 8) |
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#define SSI_FC_RXFFL BIT(4) |
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#define SSI_FC_RXFTH_MASK GENMASK(3, 0) |
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#define SSI_TXDR 0x24 |
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#define SSI_RXDR 0x24 |
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#define SSI_FIFO_DEPTH 8U |
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#define SSI_FIFO_BURST_NUM 1 |
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#define SSI_DMA_RX_BUSY BIT(1) |
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#define SSI_DMA_TX_BUSY BIT(0) |
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static inline unsigned int bytes_per_word(unsigned int bits) |
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{ |
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return bits <= 8 ? 1 : (bits <= 16 ? 2 : 4); |
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} |
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static inline void uniphier_spi_irq_enable(struct uniphier_spi_priv *priv, |
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u32 mask) |
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{ |
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u32 val; |
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val = readl(priv->base + SSI_IE); |
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val |= mask; |
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writel(val, priv->base + SSI_IE); |
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} |
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static inline void uniphier_spi_irq_disable(struct uniphier_spi_priv *priv, |
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u32 mask) |
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{ |
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u32 val; |
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val = readl(priv->base + SSI_IE); |
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val &= ~mask; |
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writel(val, priv->base + SSI_IE); |
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} |
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static void uniphier_spi_set_mode(struct spi_device *spi) |
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{ |
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struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master); |
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u32 val1, val2; |
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/* |
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* clock setting |
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* CKPHS capture timing. 0:rising edge, 1:falling edge |
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* CKINIT clock initial level. 0:low, 1:high |
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* CKDLY clock delay. 0:no delay, 1:delay depending on FSTRT |
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* (FSTRT=0: 1 clock, FSTRT=1: 0.5 clock) |
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* |
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* frame setting |
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* FSPOL frame signal porarity. 0: low, 1: high |
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* FSTRT start frame timing |
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* 0: rising edge of clock, 1: falling edge of clock |
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*/ |
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switch (spi->mode & SPI_MODE_X_MASK) { |
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case SPI_MODE_0: |
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/* CKPHS=1, CKINIT=0, CKDLY=1, FSTRT=0 */ |
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val1 = SSI_CKS_CKPHS | SSI_CKS_CKDLY; |
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val2 = 0; |
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break; |
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case SPI_MODE_1: |
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/* CKPHS=0, CKINIT=0, CKDLY=0, FSTRT=1 */ |
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val1 = 0; |
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val2 = SSI_FPS_FSTRT; |
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break; |
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case SPI_MODE_2: |
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/* CKPHS=0, CKINIT=1, CKDLY=1, FSTRT=1 */ |
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val1 = SSI_CKS_CKINIT | SSI_CKS_CKDLY; |
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val2 = SSI_FPS_FSTRT; |
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break; |
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case SPI_MODE_3: |
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/* CKPHS=1, CKINIT=1, CKDLY=0, FSTRT=0 */ |
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val1 = SSI_CKS_CKPHS | SSI_CKS_CKINIT; |
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val2 = 0; |
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break; |
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} |
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if (!(spi->mode & SPI_CS_HIGH)) |
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val2 |= SSI_FPS_FSPOL; |
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writel(val1, priv->base + SSI_CKS); |
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writel(val2, priv->base + SSI_FPS); |
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val1 = 0; |
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if (spi->mode & SPI_LSB_FIRST) |
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val1 |= FIELD_PREP(SSI_TXWDS_TDTF_MASK, 1); |
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writel(val1, priv->base + SSI_TXWDS); |
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writel(val1, priv->base + SSI_RXWDS); |
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} |
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static void uniphier_spi_set_transfer_size(struct spi_device *spi, int size) |
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{ |
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struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master); |
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u32 val; |
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val = readl(priv->base + SSI_TXWDS); |
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val &= ~(SSI_TXWDS_WDLEN_MASK | SSI_TXWDS_DTLEN_MASK); |
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val |= FIELD_PREP(SSI_TXWDS_WDLEN_MASK, size); |
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val |= FIELD_PREP(SSI_TXWDS_DTLEN_MASK, size); |
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writel(val, priv->base + SSI_TXWDS); |
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val = readl(priv->base + SSI_RXWDS); |
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val &= ~SSI_RXWDS_DTLEN_MASK; |
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val |= FIELD_PREP(SSI_RXWDS_DTLEN_MASK, size); |
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writel(val, priv->base + SSI_RXWDS); |
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} |
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static void uniphier_spi_set_baudrate(struct spi_device *spi, |
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unsigned int speed) |
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{ |
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struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master); |
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u32 val, ckdiv; |
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/* |
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* the supported rates are even numbers from 4 to 254. (4,6,8...254) |
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* round up as we look for equal or less speed |
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*/ |
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ckdiv = DIV_ROUND_UP(clk_get_rate(priv->clk), speed); |
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ckdiv = round_up(ckdiv, 2); |
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val = readl(priv->base + SSI_CKS); |
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val &= ~SSI_CKS_CKRAT_MASK; |
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val |= ckdiv & SSI_CKS_CKRAT_MASK; |
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writel(val, priv->base + SSI_CKS); |
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} |
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static void uniphier_spi_setup_transfer(struct spi_device *spi, |
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struct spi_transfer *t) |
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{ |
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struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master); |
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u32 val; |
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priv->error = 0; |
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priv->tx_buf = t->tx_buf; |
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priv->rx_buf = t->rx_buf; |
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priv->tx_bytes = priv->rx_bytes = t->len; |
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if (!priv->is_save_param || priv->mode != spi->mode) { |
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uniphier_spi_set_mode(spi); |
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priv->mode = spi->mode; |
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priv->is_save_param = false; |
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} |
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if (!priv->is_save_param || priv->bits_per_word != t->bits_per_word) { |
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uniphier_spi_set_transfer_size(spi, t->bits_per_word); |
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priv->bits_per_word = t->bits_per_word; |
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} |
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if (!priv->is_save_param || priv->speed_hz != t->speed_hz) { |
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uniphier_spi_set_baudrate(spi, t->speed_hz); |
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priv->speed_hz = t->speed_hz; |
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} |
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priv->is_save_param = true; |
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/* reset FIFOs */ |
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val = SSI_FC_TXFFL | SSI_FC_RXFFL; |
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writel(val, priv->base + SSI_FC); |
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} |
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static void uniphier_spi_send(struct uniphier_spi_priv *priv) |
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{ |
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int wsize; |
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u32 val = 0; |
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wsize = min(bytes_per_word(priv->bits_per_word), priv->tx_bytes); |
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priv->tx_bytes -= wsize; |
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if (priv->tx_buf) { |
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switch (wsize) { |
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case 1: |
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val = *priv->tx_buf; |
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break; |
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case 2: |
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val = get_unaligned_le16(priv->tx_buf); |
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break; |
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case 4: |
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val = get_unaligned_le32(priv->tx_buf); |
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break; |
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} |
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priv->tx_buf += wsize; |
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} |
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writel(val, priv->base + SSI_TXDR); |
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} |
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static void uniphier_spi_recv(struct uniphier_spi_priv *priv) |
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{ |
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int rsize; |
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u32 val; |
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rsize = min(bytes_per_word(priv->bits_per_word), priv->rx_bytes); |
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priv->rx_bytes -= rsize; |
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val = readl(priv->base + SSI_RXDR); |
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if (priv->rx_buf) { |
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switch (rsize) { |
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case 1: |
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*priv->rx_buf = val; |
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break; |
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case 2: |
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put_unaligned_le16(val, priv->rx_buf); |
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break; |
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case 4: |
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put_unaligned_le32(val, priv->rx_buf); |
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break; |
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} |
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priv->rx_buf += rsize; |
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} |
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} |
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static void uniphier_spi_set_fifo_threshold(struct uniphier_spi_priv *priv, |
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unsigned int threshold) |
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{ |
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u32 val; |
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val = readl(priv->base + SSI_FC); |
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val &= ~(SSI_FC_TXFTH_MASK | SSI_FC_RXFTH_MASK); |
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val |= FIELD_PREP(SSI_FC_TXFTH_MASK, SSI_FIFO_DEPTH - threshold); |
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val |= FIELD_PREP(SSI_FC_RXFTH_MASK, threshold); |
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writel(val, priv->base + SSI_FC); |
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} |
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static void uniphier_spi_fill_tx_fifo(struct uniphier_spi_priv *priv) |
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{ |
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unsigned int fifo_threshold, fill_words; |
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unsigned int bpw = bytes_per_word(priv->bits_per_word); |
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fifo_threshold = DIV_ROUND_UP(priv->rx_bytes, bpw); |
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fifo_threshold = min(fifo_threshold, SSI_FIFO_DEPTH); |
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uniphier_spi_set_fifo_threshold(priv, fifo_threshold); |
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fill_words = fifo_threshold - |
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DIV_ROUND_UP(priv->rx_bytes - priv->tx_bytes, bpw); |
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while (fill_words--) |
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uniphier_spi_send(priv); |
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} |
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static void uniphier_spi_set_cs(struct spi_device *spi, bool enable) |
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{ |
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struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master); |
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u32 val; |
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val = readl(priv->base + SSI_FPS); |
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if (enable) |
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val |= SSI_FPS_FSPOL; |
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else |
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val &= ~SSI_FPS_FSPOL; |
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writel(val, priv->base + SSI_FPS); |
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} |
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static bool uniphier_spi_can_dma(struct spi_master *master, |
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struct spi_device *spi, |
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struct spi_transfer *t) |
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{ |
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struct uniphier_spi_priv *priv = spi_master_get_devdata(master); |
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unsigned int bpw = bytes_per_word(priv->bits_per_word); |
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if ((!master->dma_tx && !master->dma_rx) |
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|| (!master->dma_tx && t->tx_buf) |
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|| (!master->dma_rx && t->rx_buf)) |
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return false; |
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return DIV_ROUND_UP(t->len, bpw) > SSI_FIFO_DEPTH; |
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} |
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static void uniphier_spi_dma_rxcb(void *data) |
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{ |
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struct spi_master *master = data; |
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struct uniphier_spi_priv *priv = spi_master_get_devdata(master); |
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int state = atomic_fetch_andnot(SSI_DMA_RX_BUSY, &priv->dma_busy); |
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uniphier_spi_irq_disable(priv, SSI_IE_RXRE); |
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if (!(state & SSI_DMA_TX_BUSY)) |
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spi_finalize_current_transfer(master); |
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} |
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static void uniphier_spi_dma_txcb(void *data) |
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{ |
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struct spi_master *master = data; |
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struct uniphier_spi_priv *priv = spi_master_get_devdata(master); |
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int state = atomic_fetch_andnot(SSI_DMA_TX_BUSY, &priv->dma_busy); |
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uniphier_spi_irq_disable(priv, SSI_IE_TXRE); |
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if (!(state & SSI_DMA_RX_BUSY)) |
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spi_finalize_current_transfer(master); |
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} |
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static int uniphier_spi_transfer_one_dma(struct spi_master *master, |
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struct spi_device *spi, |
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struct spi_transfer *t) |
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{ |
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struct uniphier_spi_priv *priv = spi_master_get_devdata(master); |
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struct dma_async_tx_descriptor *rxdesc = NULL, *txdesc = NULL; |
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int buswidth; |
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atomic_set(&priv->dma_busy, 0); |
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uniphier_spi_set_fifo_threshold(priv, SSI_FIFO_BURST_NUM); |
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if (priv->bits_per_word <= 8) |
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buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE; |
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else if (priv->bits_per_word <= 16) |
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buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES; |
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else |
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buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES; |
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if (priv->rx_buf) { |
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struct dma_slave_config rxconf = { |
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.direction = DMA_DEV_TO_MEM, |
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.src_addr = priv->base_dma_addr + SSI_RXDR, |
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.src_addr_width = buswidth, |
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.src_maxburst = SSI_FIFO_BURST_NUM, |
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}; |
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dmaengine_slave_config(master->dma_rx, &rxconf); |
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rxdesc = dmaengine_prep_slave_sg( |
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master->dma_rx, |
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t->rx_sg.sgl, t->rx_sg.nents, |
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DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
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if (!rxdesc) |
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goto out_err_prep; |
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rxdesc->callback = uniphier_spi_dma_rxcb; |
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rxdesc->callback_param = master; |
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uniphier_spi_irq_enable(priv, SSI_IE_RXRE); |
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atomic_or(SSI_DMA_RX_BUSY, &priv->dma_busy); |
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dmaengine_submit(rxdesc); |
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dma_async_issue_pending(master->dma_rx); |
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} |
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if (priv->tx_buf) { |
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struct dma_slave_config txconf = { |
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.direction = DMA_MEM_TO_DEV, |
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.dst_addr = priv->base_dma_addr + SSI_TXDR, |
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.dst_addr_width = buswidth, |
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.dst_maxburst = SSI_FIFO_BURST_NUM, |
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}; |
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dmaengine_slave_config(master->dma_tx, &txconf); |
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txdesc = dmaengine_prep_slave_sg( |
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master->dma_tx, |
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t->tx_sg.sgl, t->tx_sg.nents, |
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DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
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if (!txdesc) |
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goto out_err_prep; |
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txdesc->callback = uniphier_spi_dma_txcb; |
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txdesc->callback_param = master; |
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uniphier_spi_irq_enable(priv, SSI_IE_TXRE); |
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atomic_or(SSI_DMA_TX_BUSY, &priv->dma_busy); |
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dmaengine_submit(txdesc); |
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dma_async_issue_pending(master->dma_tx); |
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} |
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/* signal that we need to wait for completion */ |
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return (priv->tx_buf || priv->rx_buf); |
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out_err_prep: |
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if (rxdesc) |
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dmaengine_terminate_sync(master->dma_rx); |
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return -EINVAL; |
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} |
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static int uniphier_spi_transfer_one_irq(struct spi_master *master, |
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struct spi_device *spi, |
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struct spi_transfer *t) |
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{ |
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struct uniphier_spi_priv *priv = spi_master_get_devdata(master); |
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struct device *dev = master->dev.parent; |
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unsigned long time_left; |
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reinit_completion(&priv->xfer_done); |
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uniphier_spi_fill_tx_fifo(priv); |
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uniphier_spi_irq_enable(priv, SSI_IE_RCIE | SSI_IE_RORIE); |
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time_left = wait_for_completion_timeout(&priv->xfer_done, |
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msecs_to_jiffies(SSI_TIMEOUT_MS)); |
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uniphier_spi_irq_disable(priv, SSI_IE_RCIE | SSI_IE_RORIE); |
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if (!time_left) { |
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dev_err(dev, "transfer timeout.\n"); |
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return -ETIMEDOUT; |
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} |
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return priv->error; |
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} |
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static int uniphier_spi_transfer_one_poll(struct spi_master *master, |
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struct spi_device *spi, |
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struct spi_transfer *t) |
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{ |
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struct uniphier_spi_priv *priv = spi_master_get_devdata(master); |
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int loop = SSI_POLL_TIMEOUT_US * 10; |
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while (priv->tx_bytes) { |
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uniphier_spi_fill_tx_fifo(priv); |
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while ((priv->rx_bytes - priv->tx_bytes) > 0) { |
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while (!(readl(priv->base + SSI_SR) & SSI_SR_RNE) |
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&& loop--) |
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ndelay(100); |
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if (loop == -1) |
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goto irq_transfer; |
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uniphier_spi_recv(priv); |
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} |
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} |
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return 0; |
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irq_transfer: |
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return uniphier_spi_transfer_one_irq(master, spi, t); |
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} |
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|
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static int uniphier_spi_transfer_one(struct spi_master *master, |
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struct spi_device *spi, |
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struct spi_transfer *t) |
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{ |
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struct uniphier_spi_priv *priv = spi_master_get_devdata(master); |
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unsigned long threshold; |
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bool use_dma; |
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|
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/* Terminate and return success for 0 byte length transfer */ |
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if (!t->len) |
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return 0; |
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|
|
uniphier_spi_setup_transfer(spi, t); |
|
|
|
use_dma = master->can_dma ? master->can_dma(master, spi, t) : false; |
|
if (use_dma) |
|
return uniphier_spi_transfer_one_dma(master, spi, t); |
|
|
|
/* |
|
* If the transfer operation will take longer than |
|
* SSI_POLL_TIMEOUT_US, it should use irq. |
|
*/ |
|
threshold = DIV_ROUND_UP(SSI_POLL_TIMEOUT_US * priv->speed_hz, |
|
USEC_PER_SEC * BITS_PER_BYTE); |
|
if (t->len > threshold) |
|
return uniphier_spi_transfer_one_irq(master, spi, t); |
|
else |
|
return uniphier_spi_transfer_one_poll(master, spi, t); |
|
} |
|
|
|
static int uniphier_spi_prepare_transfer_hardware(struct spi_master *master) |
|
{ |
|
struct uniphier_spi_priv *priv = spi_master_get_devdata(master); |
|
|
|
writel(SSI_CTL_EN, priv->base + SSI_CTL); |
|
|
|
return 0; |
|
} |
|
|
|
static int uniphier_spi_unprepare_transfer_hardware(struct spi_master *master) |
|
{ |
|
struct uniphier_spi_priv *priv = spi_master_get_devdata(master); |
|
|
|
writel(0, priv->base + SSI_CTL); |
|
|
|
return 0; |
|
} |
|
|
|
static void uniphier_spi_handle_err(struct spi_master *master, |
|
struct spi_message *msg) |
|
{ |
|
struct uniphier_spi_priv *priv = spi_master_get_devdata(master); |
|
u32 val; |
|
|
|
/* stop running spi transfer */ |
|
writel(0, priv->base + SSI_CTL); |
|
|
|
/* reset FIFOs */ |
|
val = SSI_FC_TXFFL | SSI_FC_RXFFL; |
|
writel(val, priv->base + SSI_FC); |
|
|
|
uniphier_spi_irq_disable(priv, SSI_IE_ALL_MASK); |
|
|
|
if (atomic_read(&priv->dma_busy) & SSI_DMA_TX_BUSY) { |
|
dmaengine_terminate_async(master->dma_tx); |
|
atomic_andnot(SSI_DMA_TX_BUSY, &priv->dma_busy); |
|
} |
|
|
|
if (atomic_read(&priv->dma_busy) & SSI_DMA_RX_BUSY) { |
|
dmaengine_terminate_async(master->dma_rx); |
|
atomic_andnot(SSI_DMA_RX_BUSY, &priv->dma_busy); |
|
} |
|
} |
|
|
|
static irqreturn_t uniphier_spi_handler(int irq, void *dev_id) |
|
{ |
|
struct uniphier_spi_priv *priv = dev_id; |
|
u32 val, stat; |
|
|
|
stat = readl(priv->base + SSI_IS); |
|
val = SSI_IC_TCIC | SSI_IC_RCIC | SSI_IC_RORIC; |
|
writel(val, priv->base + SSI_IC); |
|
|
|
/* rx fifo overrun */ |
|
if (stat & SSI_IS_RORID) { |
|
priv->error = -EIO; |
|
goto done; |
|
} |
|
|
|
/* rx complete */ |
|
if ((stat & SSI_IS_RCID) && (stat & SSI_IS_RXRS)) { |
|
while ((readl(priv->base + SSI_SR) & SSI_SR_RNE) && |
|
(priv->rx_bytes - priv->tx_bytes) > 0) |
|
uniphier_spi_recv(priv); |
|
|
|
if ((readl(priv->base + SSI_SR) & SSI_SR_RNE) || |
|
(priv->rx_bytes != priv->tx_bytes)) { |
|
priv->error = -EIO; |
|
goto done; |
|
} else if (priv->rx_bytes == 0) |
|
goto done; |
|
|
|
/* next tx transfer */ |
|
uniphier_spi_fill_tx_fifo(priv); |
|
|
|
return IRQ_HANDLED; |
|
} |
|
|
|
return IRQ_NONE; |
|
|
|
done: |
|
complete(&priv->xfer_done); |
|
return IRQ_HANDLED; |
|
} |
|
|
|
static int uniphier_spi_probe(struct platform_device *pdev) |
|
{ |
|
struct uniphier_spi_priv *priv; |
|
struct spi_master *master; |
|
struct resource *res; |
|
struct dma_slave_caps caps; |
|
u32 dma_tx_burst = 0, dma_rx_burst = 0; |
|
unsigned long clk_rate; |
|
int irq; |
|
int ret; |
|
|
|
master = spi_alloc_master(&pdev->dev, sizeof(*priv)); |
|
if (!master) |
|
return -ENOMEM; |
|
|
|
platform_set_drvdata(pdev, master); |
|
|
|
priv = spi_master_get_devdata(master); |
|
priv->master = master; |
|
priv->is_save_param = false; |
|
|
|
priv->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); |
|
if (IS_ERR(priv->base)) { |
|
ret = PTR_ERR(priv->base); |
|
goto out_master_put; |
|
} |
|
priv->base_dma_addr = res->start; |
|
|
|
priv->clk = devm_clk_get(&pdev->dev, NULL); |
|
if (IS_ERR(priv->clk)) { |
|
dev_err(&pdev->dev, "failed to get clock\n"); |
|
ret = PTR_ERR(priv->clk); |
|
goto out_master_put; |
|
} |
|
|
|
ret = clk_prepare_enable(priv->clk); |
|
if (ret) |
|
goto out_master_put; |
|
|
|
irq = platform_get_irq(pdev, 0); |
|
if (irq < 0) { |
|
ret = irq; |
|
goto out_disable_clk; |
|
} |
|
|
|
ret = devm_request_irq(&pdev->dev, irq, uniphier_spi_handler, |
|
0, "uniphier-spi", priv); |
|
if (ret) { |
|
dev_err(&pdev->dev, "failed to request IRQ\n"); |
|
goto out_disable_clk; |
|
} |
|
|
|
init_completion(&priv->xfer_done); |
|
|
|
clk_rate = clk_get_rate(priv->clk); |
|
|
|
master->max_speed_hz = DIV_ROUND_UP(clk_rate, SSI_MIN_CLK_DIVIDER); |
|
master->min_speed_hz = DIV_ROUND_UP(clk_rate, SSI_MAX_CLK_DIVIDER); |
|
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST; |
|
master->dev.of_node = pdev->dev.of_node; |
|
master->bus_num = pdev->id; |
|
master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); |
|
|
|
master->set_cs = uniphier_spi_set_cs; |
|
master->transfer_one = uniphier_spi_transfer_one; |
|
master->prepare_transfer_hardware |
|
= uniphier_spi_prepare_transfer_hardware; |
|
master->unprepare_transfer_hardware |
|
= uniphier_spi_unprepare_transfer_hardware; |
|
master->handle_err = uniphier_spi_handle_err; |
|
master->can_dma = uniphier_spi_can_dma; |
|
|
|
master->num_chipselect = 1; |
|
master->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX; |
|
|
|
master->dma_tx = dma_request_chan(&pdev->dev, "tx"); |
|
if (IS_ERR_OR_NULL(master->dma_tx)) { |
|
if (PTR_ERR(master->dma_tx) == -EPROBE_DEFER) { |
|
ret = -EPROBE_DEFER; |
|
goto out_disable_clk; |
|
} |
|
master->dma_tx = NULL; |
|
dma_tx_burst = INT_MAX; |
|
} else { |
|
ret = dma_get_slave_caps(master->dma_tx, &caps); |
|
if (ret) { |
|
dev_err(&pdev->dev, "failed to get TX DMA capacities: %d\n", |
|
ret); |
|
goto out_disable_clk; |
|
} |
|
dma_tx_burst = caps.max_burst; |
|
} |
|
|
|
master->dma_rx = dma_request_chan(&pdev->dev, "rx"); |
|
if (IS_ERR_OR_NULL(master->dma_rx)) { |
|
if (PTR_ERR(master->dma_rx) == -EPROBE_DEFER) { |
|
ret = -EPROBE_DEFER; |
|
goto out_disable_clk; |
|
} |
|
master->dma_rx = NULL; |
|
dma_rx_burst = INT_MAX; |
|
} else { |
|
ret = dma_get_slave_caps(master->dma_rx, &caps); |
|
if (ret) { |
|
dev_err(&pdev->dev, "failed to get RX DMA capacities: %d\n", |
|
ret); |
|
goto out_disable_clk; |
|
} |
|
dma_rx_burst = caps.max_burst; |
|
} |
|
|
|
master->max_dma_len = min(dma_tx_burst, dma_rx_burst); |
|
|
|
ret = devm_spi_register_master(&pdev->dev, master); |
|
if (ret) |
|
goto out_disable_clk; |
|
|
|
return 0; |
|
|
|
out_disable_clk: |
|
clk_disable_unprepare(priv->clk); |
|
|
|
out_master_put: |
|
spi_master_put(master); |
|
return ret; |
|
} |
|
|
|
static int uniphier_spi_remove(struct platform_device *pdev) |
|
{ |
|
struct uniphier_spi_priv *priv = platform_get_drvdata(pdev); |
|
|
|
if (priv->master->dma_tx) |
|
dma_release_channel(priv->master->dma_tx); |
|
if (priv->master->dma_rx) |
|
dma_release_channel(priv->master->dma_rx); |
|
|
|
clk_disable_unprepare(priv->clk); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct of_device_id uniphier_spi_match[] = { |
|
{ .compatible = "socionext,uniphier-scssi" }, |
|
{ /* sentinel */ } |
|
}; |
|
MODULE_DEVICE_TABLE(of, uniphier_spi_match); |
|
|
|
static struct platform_driver uniphier_spi_driver = { |
|
.probe = uniphier_spi_probe, |
|
.remove = uniphier_spi_remove, |
|
.driver = { |
|
.name = "uniphier-spi", |
|
.of_match_table = uniphier_spi_match, |
|
}, |
|
}; |
|
module_platform_driver(uniphier_spi_driver); |
|
|
|
MODULE_AUTHOR("Kunihiko Hayashi <[email protected]>"); |
|
MODULE_AUTHOR("Keiji Hayashibara <[email protected]>"); |
|
MODULE_DESCRIPTION("Socionext UniPhier SPI controller driver"); |
|
MODULE_LICENSE("GPL v2");
|
|
|