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715 lines
18 KiB
715 lines
18 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* PIC32 Quad SPI controller driver. |
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* |
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* Purna Chandra Mandal <[email protected]> |
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* Copyright (c) 2016, Microchip Technology Inc. |
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*/ |
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#include <linux/clk.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/iopoll.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/platform_device.h> |
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#include <linux/slab.h> |
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#include <linux/spi/spi.h> |
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/* SQI registers */ |
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#define PESQI_XIP_CONF1_REG 0x00 |
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#define PESQI_XIP_CONF2_REG 0x04 |
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#define PESQI_CONF_REG 0x08 |
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#define PESQI_CTRL_REG 0x0C |
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#define PESQI_CLK_CTRL_REG 0x10 |
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#define PESQI_CMD_THRES_REG 0x14 |
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#define PESQI_INT_THRES_REG 0x18 |
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#define PESQI_INT_ENABLE_REG 0x1C |
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#define PESQI_INT_STAT_REG 0x20 |
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#define PESQI_TX_DATA_REG 0x24 |
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#define PESQI_RX_DATA_REG 0x28 |
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#define PESQI_STAT1_REG 0x2C |
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#define PESQI_STAT2_REG 0x30 |
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#define PESQI_BD_CTRL_REG 0x34 |
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#define PESQI_BD_CUR_ADDR_REG 0x38 |
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#define PESQI_BD_BASE_ADDR_REG 0x40 |
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#define PESQI_BD_STAT_REG 0x44 |
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#define PESQI_BD_POLL_CTRL_REG 0x48 |
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#define PESQI_BD_TX_DMA_STAT_REG 0x4C |
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#define PESQI_BD_RX_DMA_STAT_REG 0x50 |
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#define PESQI_THRES_REG 0x54 |
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#define PESQI_INT_SIGEN_REG 0x58 |
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/* PESQI_CONF_REG fields */ |
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#define PESQI_MODE 0x7 |
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#define PESQI_MODE_BOOT 0 |
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#define PESQI_MODE_PIO 1 |
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#define PESQI_MODE_DMA 2 |
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#define PESQI_MODE_XIP 3 |
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#define PESQI_MODE_SHIFT 0 |
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#define PESQI_CPHA BIT(3) |
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#define PESQI_CPOL BIT(4) |
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#define PESQI_LSBF BIT(5) |
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#define PESQI_RXLATCH BIT(7) |
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#define PESQI_SERMODE BIT(8) |
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#define PESQI_WP_EN BIT(9) |
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#define PESQI_HOLD_EN BIT(10) |
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#define PESQI_BURST_EN BIT(12) |
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#define PESQI_CS_CTRL_HW BIT(15) |
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#define PESQI_SOFT_RESET BIT(16) |
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#define PESQI_LANES_SHIFT 20 |
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#define PESQI_SINGLE_LANE 0 |
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#define PESQI_DUAL_LANE 1 |
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#define PESQI_QUAD_LANE 2 |
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#define PESQI_CSEN_SHIFT 24 |
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#define PESQI_EN BIT(23) |
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/* PESQI_CLK_CTRL_REG fields */ |
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#define PESQI_CLK_EN BIT(0) |
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#define PESQI_CLK_STABLE BIT(1) |
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#define PESQI_CLKDIV_SHIFT 8 |
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#define PESQI_CLKDIV 0xff |
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/* PESQI_INT_THR/CMD_THR_REG */ |
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#define PESQI_TXTHR_MASK 0x1f |
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#define PESQI_TXTHR_SHIFT 8 |
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#define PESQI_RXTHR_MASK 0x1f |
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#define PESQI_RXTHR_SHIFT 0 |
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/* PESQI_INT_EN/INT_STAT/INT_SIG_EN_REG */ |
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#define PESQI_TXEMPTY BIT(0) |
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#define PESQI_TXFULL BIT(1) |
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#define PESQI_TXTHR BIT(2) |
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#define PESQI_RXEMPTY BIT(3) |
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#define PESQI_RXFULL BIT(4) |
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#define PESQI_RXTHR BIT(5) |
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#define PESQI_BDDONE BIT(9) /* BD processing complete */ |
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#define PESQI_PKTCOMP BIT(10) /* packet processing complete */ |
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#define PESQI_DMAERR BIT(11) /* error */ |
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/* PESQI_BD_CTRL_REG */ |
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#define PESQI_DMA_EN BIT(0) /* enable DMA engine */ |
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#define PESQI_POLL_EN BIT(1) /* enable polling */ |
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#define PESQI_BDP_START BIT(2) /* start BD processor */ |
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/* PESQI controller buffer descriptor */ |
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struct buf_desc { |
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u32 bd_ctrl; /* control */ |
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u32 bd_status; /* reserved */ |
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u32 bd_addr; /* DMA buffer addr */ |
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u32 bd_nextp; /* next item in chain */ |
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}; |
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/* bd_ctrl */ |
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#define BD_BUFLEN 0x1ff |
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#define BD_CBD_INT_EN BIT(16) /* Current BD is processed */ |
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#define BD_PKT_INT_EN BIT(17) /* All BDs of PKT processed */ |
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#define BD_LIFM BIT(18) /* last data of pkt */ |
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#define BD_LAST BIT(19) /* end of list */ |
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#define BD_DATA_RECV BIT(20) /* receive data */ |
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#define BD_DDR BIT(21) /* DDR mode */ |
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#define BD_DUAL BIT(22) /* Dual SPI */ |
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#define BD_QUAD BIT(23) /* Quad SPI */ |
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#define BD_LSBF BIT(25) /* LSB First */ |
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#define BD_STAT_CHECK BIT(27) /* Status poll */ |
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#define BD_DEVSEL_SHIFT 28 /* CS */ |
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#define BD_CS_DEASSERT BIT(30) /* de-assert CS after current BD */ |
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#define BD_EN BIT(31) /* BD owned by H/W */ |
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/** |
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* struct ring_desc - Representation of SQI ring descriptor |
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* @list: list element to add to free or used list. |
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* @bd: PESQI controller buffer descriptor |
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* @bd_dma: DMA address of PESQI controller buffer descriptor |
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* @xfer_len: transfer length |
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*/ |
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struct ring_desc { |
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struct list_head list; |
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struct buf_desc *bd; |
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dma_addr_t bd_dma; |
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u32 xfer_len; |
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}; |
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/* Global constants */ |
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#define PESQI_BD_BUF_LEN_MAX 256 |
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#define PESQI_BD_COUNT 256 /* max 64KB data per spi message */ |
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struct pic32_sqi { |
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void __iomem *regs; |
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struct clk *sys_clk; |
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struct clk *base_clk; /* drives spi clock */ |
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struct spi_master *master; |
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int irq; |
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struct completion xfer_done; |
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struct ring_desc *ring; |
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void *bd; |
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dma_addr_t bd_dma; |
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struct list_head bd_list_free; /* free */ |
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struct list_head bd_list_used; /* allocated */ |
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struct spi_device *cur_spi; |
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u32 cur_speed; |
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u8 cur_mode; |
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}; |
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static inline void pic32_setbits(void __iomem *reg, u32 set) |
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{ |
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writel(readl(reg) | set, reg); |
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} |
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static inline void pic32_clrbits(void __iomem *reg, u32 clr) |
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{ |
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writel(readl(reg) & ~clr, reg); |
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} |
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static int pic32_sqi_set_clk_rate(struct pic32_sqi *sqi, u32 sck) |
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{ |
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u32 val, div; |
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/* div = base_clk / (2 * spi_clk) */ |
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div = clk_get_rate(sqi->base_clk) / (2 * sck); |
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div &= PESQI_CLKDIV; |
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val = readl(sqi->regs + PESQI_CLK_CTRL_REG); |
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/* apply new divider */ |
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val &= ~(PESQI_CLK_STABLE | (PESQI_CLKDIV << PESQI_CLKDIV_SHIFT)); |
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val |= div << PESQI_CLKDIV_SHIFT; |
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writel(val, sqi->regs + PESQI_CLK_CTRL_REG); |
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/* wait for stability */ |
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return readl_poll_timeout(sqi->regs + PESQI_CLK_CTRL_REG, val, |
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val & PESQI_CLK_STABLE, 1, 5000); |
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} |
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static inline void pic32_sqi_enable_int(struct pic32_sqi *sqi) |
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{ |
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u32 mask = PESQI_DMAERR | PESQI_BDDONE | PESQI_PKTCOMP; |
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writel(mask, sqi->regs + PESQI_INT_ENABLE_REG); |
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/* INT_SIGEN works as interrupt-gate to INTR line */ |
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writel(mask, sqi->regs + PESQI_INT_SIGEN_REG); |
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} |
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static inline void pic32_sqi_disable_int(struct pic32_sqi *sqi) |
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{ |
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writel(0, sqi->regs + PESQI_INT_ENABLE_REG); |
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writel(0, sqi->regs + PESQI_INT_SIGEN_REG); |
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} |
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static irqreturn_t pic32_sqi_isr(int irq, void *dev_id) |
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{ |
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struct pic32_sqi *sqi = dev_id; |
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u32 enable, status; |
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enable = readl(sqi->regs + PESQI_INT_ENABLE_REG); |
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status = readl(sqi->regs + PESQI_INT_STAT_REG); |
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/* check spurious interrupt */ |
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if (!status) |
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return IRQ_NONE; |
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if (status & PESQI_DMAERR) { |
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enable = 0; |
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goto irq_done; |
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} |
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if (status & PESQI_TXTHR) |
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enable &= ~(PESQI_TXTHR | PESQI_TXFULL | PESQI_TXEMPTY); |
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if (status & PESQI_RXTHR) |
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enable &= ~(PESQI_RXTHR | PESQI_RXFULL | PESQI_RXEMPTY); |
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if (status & PESQI_BDDONE) |
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enable &= ~PESQI_BDDONE; |
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/* packet processing completed */ |
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if (status & PESQI_PKTCOMP) { |
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/* mask all interrupts */ |
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enable = 0; |
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/* complete trasaction */ |
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complete(&sqi->xfer_done); |
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} |
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irq_done: |
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/* interrupts are sticky, so mask when handled */ |
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writel(enable, sqi->regs + PESQI_INT_ENABLE_REG); |
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return IRQ_HANDLED; |
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} |
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static struct ring_desc *ring_desc_get(struct pic32_sqi *sqi) |
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{ |
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struct ring_desc *rdesc; |
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if (list_empty(&sqi->bd_list_free)) |
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return NULL; |
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rdesc = list_first_entry(&sqi->bd_list_free, struct ring_desc, list); |
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list_move_tail(&rdesc->list, &sqi->bd_list_used); |
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return rdesc; |
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} |
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static void ring_desc_put(struct pic32_sqi *sqi, struct ring_desc *rdesc) |
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{ |
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list_move(&rdesc->list, &sqi->bd_list_free); |
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} |
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static int pic32_sqi_one_transfer(struct pic32_sqi *sqi, |
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struct spi_message *mesg, |
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struct spi_transfer *xfer) |
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{ |
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struct spi_device *spi = mesg->spi; |
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struct scatterlist *sg, *sgl; |
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struct ring_desc *rdesc; |
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struct buf_desc *bd; |
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int nents, i; |
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u32 bd_ctrl; |
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u32 nbits; |
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/* Device selection */ |
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bd_ctrl = spi->chip_select << BD_DEVSEL_SHIFT; |
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/* half-duplex: select transfer buffer, direction and lane */ |
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if (xfer->rx_buf) { |
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bd_ctrl |= BD_DATA_RECV; |
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nbits = xfer->rx_nbits; |
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sgl = xfer->rx_sg.sgl; |
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nents = xfer->rx_sg.nents; |
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} else { |
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nbits = xfer->tx_nbits; |
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sgl = xfer->tx_sg.sgl; |
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nents = xfer->tx_sg.nents; |
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} |
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if (nbits & SPI_NBITS_QUAD) |
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bd_ctrl |= BD_QUAD; |
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else if (nbits & SPI_NBITS_DUAL) |
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bd_ctrl |= BD_DUAL; |
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/* LSB first */ |
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if (spi->mode & SPI_LSB_FIRST) |
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bd_ctrl |= BD_LSBF; |
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/* ownership to hardware */ |
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bd_ctrl |= BD_EN; |
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for_each_sg(sgl, sg, nents, i) { |
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/* get ring descriptor */ |
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rdesc = ring_desc_get(sqi); |
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if (!rdesc) |
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break; |
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bd = rdesc->bd; |
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/* BD CTRL: length */ |
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rdesc->xfer_len = sg_dma_len(sg); |
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bd->bd_ctrl = bd_ctrl; |
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bd->bd_ctrl |= rdesc->xfer_len; |
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/* BD STAT */ |
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bd->bd_status = 0; |
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/* BD BUFFER ADDRESS */ |
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bd->bd_addr = sg->dma_address; |
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} |
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return 0; |
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} |
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static int pic32_sqi_prepare_hardware(struct spi_master *master) |
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{ |
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struct pic32_sqi *sqi = spi_master_get_devdata(master); |
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/* enable spi interface */ |
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pic32_setbits(sqi->regs + PESQI_CONF_REG, PESQI_EN); |
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/* enable spi clk */ |
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pic32_setbits(sqi->regs + PESQI_CLK_CTRL_REG, PESQI_CLK_EN); |
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return 0; |
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} |
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static bool pic32_sqi_can_dma(struct spi_master *master, |
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struct spi_device *spi, |
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struct spi_transfer *x) |
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{ |
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/* Do DMA irrespective of transfer size */ |
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return true; |
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} |
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static int pic32_sqi_one_message(struct spi_master *master, |
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struct spi_message *msg) |
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{ |
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struct spi_device *spi = msg->spi; |
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struct ring_desc *rdesc, *next; |
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struct spi_transfer *xfer; |
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struct pic32_sqi *sqi; |
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int ret = 0, mode; |
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unsigned long timeout; |
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u32 val; |
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sqi = spi_master_get_devdata(master); |
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reinit_completion(&sqi->xfer_done); |
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msg->actual_length = 0; |
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/* We can't handle spi_transfer specific "speed_hz", "bits_per_word" |
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* and "delay_usecs". But spi_device specific speed and mode change |
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* can be handled at best during spi chip-select switch. |
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*/ |
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if (sqi->cur_spi != spi) { |
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/* set spi speed */ |
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if (sqi->cur_speed != spi->max_speed_hz) { |
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sqi->cur_speed = spi->max_speed_hz; |
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ret = pic32_sqi_set_clk_rate(sqi, spi->max_speed_hz); |
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if (ret) |
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dev_warn(&spi->dev, "set_clk, %d\n", ret); |
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} |
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/* set spi mode */ |
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mode = spi->mode & (SPI_MODE_3 | SPI_LSB_FIRST); |
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if (sqi->cur_mode != mode) { |
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val = readl(sqi->regs + PESQI_CONF_REG); |
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val &= ~(PESQI_CPOL | PESQI_CPHA | PESQI_LSBF); |
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if (mode & SPI_CPOL) |
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val |= PESQI_CPOL; |
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if (mode & SPI_LSB_FIRST) |
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val |= PESQI_LSBF; |
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val |= PESQI_CPHA; |
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writel(val, sqi->regs + PESQI_CONF_REG); |
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sqi->cur_mode = mode; |
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} |
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sqi->cur_spi = spi; |
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} |
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/* prepare hardware desc-list(BD) for transfer(s) */ |
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list_for_each_entry(xfer, &msg->transfers, transfer_list) { |
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ret = pic32_sqi_one_transfer(sqi, msg, xfer); |
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if (ret) { |
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dev_err(&spi->dev, "xfer %p err\n", xfer); |
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goto xfer_out; |
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} |
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} |
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/* BDs are prepared and chained. Now mark LAST_BD, CS_DEASSERT at last |
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* element of the list. |
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*/ |
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rdesc = list_last_entry(&sqi->bd_list_used, struct ring_desc, list); |
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rdesc->bd->bd_ctrl |= BD_LAST | BD_CS_DEASSERT | |
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BD_LIFM | BD_PKT_INT_EN; |
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/* set base address BD list for DMA engine */ |
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rdesc = list_first_entry(&sqi->bd_list_used, struct ring_desc, list); |
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writel(rdesc->bd_dma, sqi->regs + PESQI_BD_BASE_ADDR_REG); |
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/* enable interrupt */ |
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pic32_sqi_enable_int(sqi); |
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/* enable DMA engine */ |
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val = PESQI_DMA_EN | PESQI_POLL_EN | PESQI_BDP_START; |
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writel(val, sqi->regs + PESQI_BD_CTRL_REG); |
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/* wait for xfer completion */ |
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timeout = wait_for_completion_timeout(&sqi->xfer_done, 5 * HZ); |
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if (timeout == 0) { |
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dev_err(&sqi->master->dev, "wait timedout/interrupted\n"); |
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ret = -ETIMEDOUT; |
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msg->status = ret; |
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} else { |
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/* success */ |
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msg->status = 0; |
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ret = 0; |
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} |
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/* disable DMA */ |
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writel(0, sqi->regs + PESQI_BD_CTRL_REG); |
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pic32_sqi_disable_int(sqi); |
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xfer_out: |
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list_for_each_entry_safe_reverse(rdesc, next, |
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&sqi->bd_list_used, list) { |
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/* Update total byte transferred */ |
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msg->actual_length += rdesc->xfer_len; |
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/* release ring descr */ |
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ring_desc_put(sqi, rdesc); |
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} |
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spi_finalize_current_message(spi->master); |
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return ret; |
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} |
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static int pic32_sqi_unprepare_hardware(struct spi_master *master) |
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{ |
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struct pic32_sqi *sqi = spi_master_get_devdata(master); |
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/* disable clk */ |
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pic32_clrbits(sqi->regs + PESQI_CLK_CTRL_REG, PESQI_CLK_EN); |
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/* disable spi */ |
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pic32_clrbits(sqi->regs + PESQI_CONF_REG, PESQI_EN); |
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return 0; |
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} |
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static int ring_desc_ring_alloc(struct pic32_sqi *sqi) |
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{ |
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struct ring_desc *rdesc; |
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struct buf_desc *bd; |
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int i; |
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/* allocate coherent DMAable memory for hardware buffer descriptors. */ |
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sqi->bd = dma_alloc_coherent(&sqi->master->dev, |
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sizeof(*bd) * PESQI_BD_COUNT, |
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&sqi->bd_dma, GFP_KERNEL); |
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if (!sqi->bd) { |
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dev_err(&sqi->master->dev, "failed allocating dma buffer\n"); |
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return -ENOMEM; |
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} |
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/* allocate software ring descriptors */ |
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sqi->ring = kcalloc(PESQI_BD_COUNT, sizeof(*rdesc), GFP_KERNEL); |
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if (!sqi->ring) { |
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dma_free_coherent(&sqi->master->dev, |
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sizeof(*bd) * PESQI_BD_COUNT, |
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sqi->bd, sqi->bd_dma); |
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return -ENOMEM; |
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} |
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bd = (struct buf_desc *)sqi->bd; |
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INIT_LIST_HEAD(&sqi->bd_list_free); |
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INIT_LIST_HEAD(&sqi->bd_list_used); |
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/* initialize ring-desc */ |
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for (i = 0, rdesc = sqi->ring; i < PESQI_BD_COUNT; i++, rdesc++) { |
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INIT_LIST_HEAD(&rdesc->list); |
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rdesc->bd = &bd[i]; |
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rdesc->bd_dma = sqi->bd_dma + (void *)&bd[i] - (void *)bd; |
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list_add_tail(&rdesc->list, &sqi->bd_list_free); |
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} |
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/* Prepare BD: chain to next BD(s) */ |
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for (i = 0, rdesc = sqi->ring; i < PESQI_BD_COUNT - 1; i++) |
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bd[i].bd_nextp = rdesc[i + 1].bd_dma; |
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bd[PESQI_BD_COUNT - 1].bd_nextp = 0; |
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return 0; |
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} |
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static void ring_desc_ring_free(struct pic32_sqi *sqi) |
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{ |
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dma_free_coherent(&sqi->master->dev, |
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sizeof(struct buf_desc) * PESQI_BD_COUNT, |
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sqi->bd, sqi->bd_dma); |
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kfree(sqi->ring); |
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} |
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static void pic32_sqi_hw_init(struct pic32_sqi *sqi) |
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{ |
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unsigned long flags; |
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u32 val; |
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/* Soft-reset of PESQI controller triggers interrupt. |
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* We are not yet ready to handle them so disable CPU |
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* interrupt for the time being. |
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*/ |
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local_irq_save(flags); |
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/* assert soft-reset */ |
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writel(PESQI_SOFT_RESET, sqi->regs + PESQI_CONF_REG); |
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/* wait until clear */ |
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readl_poll_timeout_atomic(sqi->regs + PESQI_CONF_REG, val, |
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!(val & PESQI_SOFT_RESET), 1, 5000); |
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/* disable all interrupts */ |
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pic32_sqi_disable_int(sqi); |
|
|
|
/* Now it is safe to enable back CPU interrupt */ |
|
local_irq_restore(flags); |
|
|
|
/* tx and rx fifo interrupt threshold */ |
|
val = readl(sqi->regs + PESQI_CMD_THRES_REG); |
|
val &= ~(PESQI_TXTHR_MASK << PESQI_TXTHR_SHIFT); |
|
val &= ~(PESQI_RXTHR_MASK << PESQI_RXTHR_SHIFT); |
|
val |= (1U << PESQI_TXTHR_SHIFT) | (1U << PESQI_RXTHR_SHIFT); |
|
writel(val, sqi->regs + PESQI_CMD_THRES_REG); |
|
|
|
val = readl(sqi->regs + PESQI_INT_THRES_REG); |
|
val &= ~(PESQI_TXTHR_MASK << PESQI_TXTHR_SHIFT); |
|
val &= ~(PESQI_RXTHR_MASK << PESQI_RXTHR_SHIFT); |
|
val |= (1U << PESQI_TXTHR_SHIFT) | (1U << PESQI_RXTHR_SHIFT); |
|
writel(val, sqi->regs + PESQI_INT_THRES_REG); |
|
|
|
/* default configuration */ |
|
val = readl(sqi->regs + PESQI_CONF_REG); |
|
|
|
/* set mode: DMA */ |
|
val &= ~PESQI_MODE; |
|
val |= PESQI_MODE_DMA << PESQI_MODE_SHIFT; |
|
writel(val, sqi->regs + PESQI_CONF_REG); |
|
|
|
/* DATAEN - SQIID0-ID3 */ |
|
val |= PESQI_QUAD_LANE << PESQI_LANES_SHIFT; |
|
|
|
/* burst/INCR4 enable */ |
|
val |= PESQI_BURST_EN; |
|
|
|
/* CSEN - all CS */ |
|
val |= 3U << PESQI_CSEN_SHIFT; |
|
writel(val, sqi->regs + PESQI_CONF_REG); |
|
|
|
/* write poll count */ |
|
writel(0, sqi->regs + PESQI_BD_POLL_CTRL_REG); |
|
|
|
sqi->cur_speed = 0; |
|
sqi->cur_mode = -1; |
|
} |
|
|
|
static int pic32_sqi_probe(struct platform_device *pdev) |
|
{ |
|
struct spi_master *master; |
|
struct pic32_sqi *sqi; |
|
int ret; |
|
|
|
master = spi_alloc_master(&pdev->dev, sizeof(*sqi)); |
|
if (!master) |
|
return -ENOMEM; |
|
|
|
sqi = spi_master_get_devdata(master); |
|
sqi->master = master; |
|
|
|
sqi->regs = devm_platform_ioremap_resource(pdev, 0); |
|
if (IS_ERR(sqi->regs)) { |
|
ret = PTR_ERR(sqi->regs); |
|
goto err_free_master; |
|
} |
|
|
|
/* irq */ |
|
sqi->irq = platform_get_irq(pdev, 0); |
|
if (sqi->irq < 0) { |
|
ret = sqi->irq; |
|
goto err_free_master; |
|
} |
|
|
|
/* clocks */ |
|
sqi->sys_clk = devm_clk_get(&pdev->dev, "reg_ck"); |
|
if (IS_ERR(sqi->sys_clk)) { |
|
ret = PTR_ERR(sqi->sys_clk); |
|
dev_err(&pdev->dev, "no sys_clk ?\n"); |
|
goto err_free_master; |
|
} |
|
|
|
sqi->base_clk = devm_clk_get(&pdev->dev, "spi_ck"); |
|
if (IS_ERR(sqi->base_clk)) { |
|
ret = PTR_ERR(sqi->base_clk); |
|
dev_err(&pdev->dev, "no base clk ?\n"); |
|
goto err_free_master; |
|
} |
|
|
|
ret = clk_prepare_enable(sqi->sys_clk); |
|
if (ret) { |
|
dev_err(&pdev->dev, "sys clk enable failed\n"); |
|
goto err_free_master; |
|
} |
|
|
|
ret = clk_prepare_enable(sqi->base_clk); |
|
if (ret) { |
|
dev_err(&pdev->dev, "base clk enable failed\n"); |
|
clk_disable_unprepare(sqi->sys_clk); |
|
goto err_free_master; |
|
} |
|
|
|
init_completion(&sqi->xfer_done); |
|
|
|
/* initialize hardware */ |
|
pic32_sqi_hw_init(sqi); |
|
|
|
/* allocate buffers & descriptors */ |
|
ret = ring_desc_ring_alloc(sqi); |
|
if (ret) { |
|
dev_err(&pdev->dev, "ring alloc failed\n"); |
|
goto err_disable_clk; |
|
} |
|
|
|
/* install irq handlers */ |
|
ret = request_irq(sqi->irq, pic32_sqi_isr, 0, |
|
dev_name(&pdev->dev), sqi); |
|
if (ret < 0) { |
|
dev_err(&pdev->dev, "request_irq(%d), failed\n", sqi->irq); |
|
goto err_free_ring; |
|
} |
|
|
|
/* register master */ |
|
master->num_chipselect = 2; |
|
master->max_speed_hz = clk_get_rate(sqi->base_clk); |
|
master->dma_alignment = 32; |
|
master->max_dma_len = PESQI_BD_BUF_LEN_MAX; |
|
master->dev.of_node = pdev->dev.of_node; |
|
master->mode_bits = SPI_MODE_3 | SPI_MODE_0 | SPI_TX_DUAL | |
|
SPI_RX_DUAL | SPI_TX_QUAD | SPI_RX_QUAD; |
|
master->flags = SPI_MASTER_HALF_DUPLEX; |
|
master->can_dma = pic32_sqi_can_dma; |
|
master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32); |
|
master->transfer_one_message = pic32_sqi_one_message; |
|
master->prepare_transfer_hardware = pic32_sqi_prepare_hardware; |
|
master->unprepare_transfer_hardware = pic32_sqi_unprepare_hardware; |
|
|
|
ret = devm_spi_register_master(&pdev->dev, master); |
|
if (ret) { |
|
dev_err(&master->dev, "failed registering spi master\n"); |
|
free_irq(sqi->irq, sqi); |
|
goto err_free_ring; |
|
} |
|
|
|
platform_set_drvdata(pdev, sqi); |
|
|
|
return 0; |
|
|
|
err_free_ring: |
|
ring_desc_ring_free(sqi); |
|
|
|
err_disable_clk: |
|
clk_disable_unprepare(sqi->base_clk); |
|
clk_disable_unprepare(sqi->sys_clk); |
|
|
|
err_free_master: |
|
spi_master_put(master); |
|
return ret; |
|
} |
|
|
|
static int pic32_sqi_remove(struct platform_device *pdev) |
|
{ |
|
struct pic32_sqi *sqi = platform_get_drvdata(pdev); |
|
|
|
/* release resources */ |
|
free_irq(sqi->irq, sqi); |
|
ring_desc_ring_free(sqi); |
|
|
|
/* disable clk */ |
|
clk_disable_unprepare(sqi->base_clk); |
|
clk_disable_unprepare(sqi->sys_clk); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct of_device_id pic32_sqi_of_ids[] = { |
|
{.compatible = "microchip,pic32mzda-sqi",}, |
|
{}, |
|
}; |
|
MODULE_DEVICE_TABLE(of, pic32_sqi_of_ids); |
|
|
|
static struct platform_driver pic32_sqi_driver = { |
|
.driver = { |
|
.name = "sqi-pic32", |
|
.of_match_table = of_match_ptr(pic32_sqi_of_ids), |
|
}, |
|
.probe = pic32_sqi_probe, |
|
.remove = pic32_sqi_remove, |
|
}; |
|
|
|
module_platform_driver(pic32_sqi_driver); |
|
|
|
MODULE_AUTHOR("Purna Chandra Mandal <[email protected]>"); |
|
MODULE_DESCRIPTION("Microchip SPI driver for PIC32 SQI controller."); |
|
MODULE_LICENSE("GPL v2");
|
|
|